nb/i945/raminit: Use common ddr2 decode functions
This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.
This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 4c97d05..7d85557 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -28,12 +28,13 @@
struct sys_info {
u16 memory_frequency; /* 400, 533 or 667 */
u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */
+ u32 tclk;
- u8 trp; /* calculated by sdram_detect_smallest_tRP() */
- u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */
- u8 tras; /* calculated by sdram_detect_smallest_tRAS() */
- u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */
- u8 twr; /* calculated by sdram_detect_smallest_tWR() */
+ u8 trp;
+ u8 trcd;
+ u8 tras;
+ u8 trfc;
+ u8 twr;
u8 cas; /* 3, 4 or 5 */
u8 refresh; /* 0 = 15.6us, 1 = 7.8us */
@@ -52,6 +53,8 @@
#define SYSINFO_PACKAGE_PLANAR 0x00
#define SYSINFO_PACKAGE_STACKED 0x01
u8 dimm[2 * DIMM_SOCKETS];
+ u8 rows[2 * DIMM_SOCKETS];
+ u8 cols[2 * DIMM_SOCKETS];
#define SYSINFO_DIMM_X16DS 0x00
#define SYSINFO_DIMM_X8DS 0x01
#define SYSINFO_DIMM_X16SS 0x02
@@ -59,7 +62,6 @@
#define SYSINFO_DIMM_NOT_POPULATED 0x04
u8 banks[2 * DIMM_SOCKETS];
-
u8 banksize[2 * 2 * DIMM_SOCKETS];
const u8 *spd_addresses;