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review.coreboot.org / coreboot / d9e654321c5a063898f39aa64898fac26a6fd23f / . / src / northbridge / intel / i945 / raminit.h
blob: 0554900587fdb6b430f1ead7c6183d6ddec9bb5b [file] [log] [blame]
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
Stefan Reinauer30140a52009-03-11 16:20:39 +0000[diff] [blame]8 * the Free Software Foundation; version 2 of the License.
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]14 */
15
16#ifndef RAMINIT_H
17#define RAMINIT_H
18
19#define DIMM_SOCKETS 2
20
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]21#define DIMM_TCO_BASE 0x30
22
23/* Burst length is always 8 */
24#define BURSTLENGTH 8
25
26struct sys_info {
27 u16 memory_frequency; /* 400, 533 or 667 */
Elyes HAOUASd9e65432016-12-01 19:59:12 +0100[diff] [blame^]28 u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]29
30 u8 trp; /* calculated by sdram_detect_smallest_tRP() */
31 u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */
32 u8 tras; /* calculated by sdram_detect_smallest_tRAS() */
33 u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */
34 u8 twr; /* calculated by sdram_detect_smallest_tWR() */
35
36 u8 cas; /* 3, 4 or 5 */
37 u8 refresh; /* 0 = 15.6us, 1 = 7.8us */
38
39 u8 dual_channel; /* 0 or 1 */
40 u8 interleaved;
41
42 u8 mvco4x; /* 0 (8x) or 1 (4x) */
43 u8 clkcfg_bit7;
44 u8 boot_path;
Stefan Reinauer71a3d962009-07-21 21:44:24 +0000[diff] [blame]45#define BOOT_PATH_NORMAL 0
46#define BOOT_PATH_RESET 1
47#define BOOT_PATH_RESUME 2
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]48
49 u8 package; /* 0 = planar, 1 = stacked */
50#define SYSINFO_PACKAGE_PLANAR 0x00
51#define SYSINFO_PACKAGE_STACKED 0x01
52 u8 dimm[2 * DIMM_SOCKETS];
53#define SYSINFO_DIMM_X16DS 0x00
54#define SYSINFO_DIMM_X8DS 0x01
55#define SYSINFO_DIMM_X16SS 0x02
56#define SYSINFO_DIMM_X8DDS 0x03
57#define SYSINFO_DIMM_NOT_POPULATED 0x04
58
59 u8 banks[2 * DIMM_SOCKETS];
60
61 u8 banksize[2 * 2 * DIMM_SOCKETS];
Sven Schnelle541269b2011-02-21 09:39:17 +0000[diff] [blame]62 const u8 *spd_addresses;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]63
64} __attribute__ ((packed));
65
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]66void receive_enable_adjust(struct sys_info *sysinfo);
Sven Schnelle541269b2011-02-21 09:39:17 +0000[diff] [blame]67void sdram_initialize(int boot_path, const u8 *sdram_addresses);
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]68int fixup_i945_errata(void);
Patrick Georgid0835952010-10-05 09:07:10 +0000[diff] [blame]69void udelay(u32 us);
Stefan Reinauer3c0bfaf2010-12-27 11:34:57 +0000[diff] [blame]70
71#if CONFIG_DEBUG_RAM_SETUP
72void sdram_dump_mchbar_registers(void);
73#endif
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]74#endif /* RAMINIT_H */