Angel Pons | d32b6de | 2020-04-03 01:23:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 2 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 4 | #include <stdint.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 5 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 6 | #include <bootmode.h> |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 7 | #include <superio/ite/common/ite.h> |
| 8 | #include <superio/ite/it8772f/it8772f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 10 | #include <northbridge/intel/sandybridge/raminit.h> |
| 11 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 12 | #include <southbridge/intel/common/gpio.h> |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 13 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 14 | |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 15 | #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 16 | #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) |
| 17 | #define EC_DEV PNP_DEV(0x2e, IT8772F_EC) |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 18 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 19 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 20 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 21 | /* |
| 22 | * GFX INTA -> PIRQA (MSI) |
| 23 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 24 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 25 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 26 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 27 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 28 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 29 | * D31IP_TTIP THRT INTC -> PIRQH |
| 30 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 31 | */ |
| 32 | |
| 33 | /* Device interrupt pin register (board specific) */ |
| 34 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 35 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 36 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 37 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 38 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 39 | (INTB << D28IP_P4IP); |
| 40 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 41 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 42 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 43 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 44 | |
| 45 | /* Device interrupt route registers */ |
| 46 | DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); |
| 47 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 48 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 49 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 50 | DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); |
| 51 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 52 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 53 | } |
| 54 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 55 | static void setup_sio_gpios(void) |
| 56 | { |
| 57 | /* |
| 58 | * GPIO10 as USBPWRON12# |
| 59 | * GPIO12 as USBPWRON13# |
| 60 | */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 61 | it8772f_gpio_setup(GPIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * GPIO22 as wake SCI# |
| 65 | */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 66 | it8772f_gpio_setup(GPIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * GPIO32 as EXTSMI# |
| 70 | */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 71 | it8772f_gpio_setup(GPIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * GPIO45 as LED_POWER# |
| 75 | */ |
Matt DeVillier | ffae746 | 2016-11-07 16:43:03 -0600 | [diff] [blame] | 76 | it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, |
| 77 | (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 78 | (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 79 | SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * GPIO51 as USBPWRON8# |
| 83 | * GPIO52 as USBPWRON1# |
| 84 | */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 85 | it8772f_gpio_setup(GPIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); |
| 86 | it8772f_gpio_setup(GPIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 87 | } |
| 88 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 89 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 90 | { |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 91 | /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 92 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 93 | |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 94 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 95 | /* enabled power USB oc pin */ |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 96 | { 1, 1, 0 }, /* P0: Front port (OC0) */ |
| 97 | { 1, 0, 1 }, /* P1: Back port (OC1) */ |
| 98 | { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ |
| 99 | { 1, 0, -1 }, /* P3: MMC (no OC) */ |
| 100 | { 1, 1, 2 }, /* P4: Front port (OC2) */ |
| 101 | { 0, 0, -1 }, /* P5: Empty */ |
| 102 | { 0, 0, -1 }, /* P6: Empty */ |
| 103 | { 0, 0, -1 }, /* P7: Empty */ |
| 104 | { 1, 0, 4 }, /* P8: Back port (OC4) */ |
| 105 | { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ |
| 106 | { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ |
| 107 | { 0, 0, -1 }, /* P11: Empty */ |
| 108 | { 1, 0, 6 }, /* P12: Back port (OC6) */ |
| 109 | { 1, 0, 5 }, /* P13: Back port (OC5) */ |
| 110 | }; |
| 111 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 112 | void bootblock_mainboard_early_init(void) |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 113 | { |
Nico Huber | 25128a7 | 2019-11-17 01:24:44 +0100 | [diff] [blame] | 114 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 115 | try_enabling_LPC47N207_uart(); |
| 116 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 117 | setup_sio_gpios(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 118 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 119 | /* Early SuperIO setup */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 120 | ite_ac_resume_southbridge(EC_DEV); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 121 | ite_kill_watchdog(GPIO_DEV); |
| 122 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 123 | } |