Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Cannonlake support |
| 5 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 6 | config SOC_INTEL_COMMON_CANNONLAKE_BASE |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 7 | bool |
| 8 | default n |
| 9 | select SOC_INTEL_CANNONLAKE |
| 10 | help |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 11 | Single Kconfig option to select common base Cannonlake support. |
| 12 | This Kconfig will help to select majority of CNL SoC features. |
| 13 | Major difference that exist today between |
| 14 | SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig |
| 15 | are in FSP Header Files. Hence this Kconfig might help to select |
| 16 | required SoC support FSP headers. Any future Intel SoC would |
| 17 | like to make use of CNL support might just select this Kconfig. |
| 18 | |
| 19 | config SOC_INTEL_COFFEELAKE |
| 20 | bool |
| 21 | default n |
| 22 | select SOC_INTEL_COMMON_CANNONLAKE_BASE |
| 23 | help |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 24 | Intel Coffeelake support |
| 25 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 26 | config SOC_INTEL_WHISKEYLAKE |
| 27 | bool |
| 28 | default n |
| 29 | select SOC_INTEL_COMMON_CANNONLAKE_BASE |
| 30 | help |
| 31 | Intel Whiskeylake support |
| 32 | |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 33 | config SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 34 | bool |
| 35 | default n |
| 36 | help |
| 37 | Choose this option if you have a PCH-H chipset. |
| 38 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 39 | if SOC_INTEL_CANNONLAKE |
| 40 | |
| 41 | config CPU_SPECIFIC_OPTIONS |
| 42 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 43 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 44 | select ACPI_NHLT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 45 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 46 | select ARCH_RAMSTAGE_X86_32 |
| 47 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 48 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 49 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 50 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 51 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 52 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 53 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 54 | select COMMON_FADT |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 55 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 56 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 57 | select HAVE_FSP_GOP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 58 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 59 | select HAVE_MONOTONIC_TIMER |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 60 | select HAVE_SMI_HANDLER |
Aamir Bohra | e462585 | 2018-05-29 10:52:33 +0530 | [diff] [blame] | 61 | select IDT_IN_EVERY_STAGE |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 62 | select INTEL_GMA_ACPI |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 63 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 64 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 65 | select MRC_SETTINGS_PROTECT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 66 | select PARALLEL_MP |
| 67 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 68 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 69 | select POSTCAR_CONSOLE |
| 70 | select POSTCAR_STAGE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 71 | select REG_SCRIPT |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 72 | select SMM_TSEG |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 73 | select SMP |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame] | 74 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 75 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 76 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
praveen hodagatta pranesh | dc4fceb | 2018-10-16 18:06:18 +0800 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_SA |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 87 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_PCH_BASE |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_NHLT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 91 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 92 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 93 | select TSC_CONSTANT_RATE |
| 94 | select TSC_MONOTONIC_TIMER |
| 95 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 96 | select UDK_2017_BINDING |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 97 | select DISPLAY_FSP_VERSION_INFO |
Praveen hodagatta pranesh | b66757f | 2018-10-23 02:43:05 +0800 | [diff] [blame] | 98 | select FSP_T_XIP if FSP_CAR |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 99 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 100 | config DCACHE_RAM_BASE |
| 101 | default 0xfef00000 |
| 102 | |
| 103 | config DCACHE_RAM_SIZE |
| 104 | default 0x40000 |
| 105 | help |
| 106 | The size of the cache-as-ram region required during bootblock |
| 107 | and/or romstage. |
| 108 | |
| 109 | config DCACHE_BSP_STACK_SIZE |
| 110 | hex |
| 111 | default 0x4000 |
| 112 | help |
| 113 | The amount of anticipated stack usage in CAR by bootblock and |
| 114 | other stages. |
| 115 | |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 116 | config IFD_CHIPSET |
| 117 | string |
| 118 | default "cnl" |
| 119 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 120 | config IED_REGION_SIZE |
| 121 | hex |
| 122 | default 0x400000 |
| 123 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 124 | config HEAP_SIZE |
| 125 | hex |
| 126 | default 0x8000 |
| 127 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 128 | config NHLT_DMIC_1CH_16B |
| 129 | bool |
| 130 | depends on ACPI_NHLT |
| 131 | default n |
| 132 | help |
| 133 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 134 | |
| 135 | config NHLT_DMIC_2CH_16B |
| 136 | bool |
| 137 | depends on ACPI_NHLT |
| 138 | default n |
| 139 | help |
| 140 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 141 | |
| 142 | config NHLT_DMIC_4CH_16B |
| 143 | bool |
| 144 | depends on ACPI_NHLT |
| 145 | default n |
| 146 | help |
| 147 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 148 | |
| 149 | config NHLT_MAX98357 |
| 150 | bool |
| 151 | depends on ACPI_NHLT |
| 152 | default n |
| 153 | help |
| 154 | Include DSP firmware settings for headset codec. |
| 155 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 156 | config NHLT_MAX98373 |
| 157 | bool |
| 158 | depends on ACPI_NHLT |
| 159 | default n |
| 160 | help |
| 161 | Include DSP firmware settings for headset codec. |
| 162 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 163 | config NHLT_DA7219 |
| 164 | bool |
| 165 | depends on ACPI_NHLT |
| 166 | default n |
| 167 | help |
| 168 | Include DSP firmware settings for headset codec. |
| 169 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 170 | config MAX_ROOT_PORTS |
| 171 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 172 | default 24 if SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 173 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 174 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 175 | config SMM_TSEG_SIZE |
| 176 | hex |
| 177 | default 0x800000 |
| 178 | |
Subrata Banik | e66600e | 2018-05-10 17:23:56 +0530 | [diff] [blame] | 179 | config SMM_RESERVED_SIZE |
| 180 | hex |
| 181 | default 0x200000 |
| 182 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 183 | config PCR_BASE_ADDRESS |
| 184 | hex |
| 185 | default 0xfd000000 |
| 186 | help |
| 187 | This option allows you to select MMIO Base Address of sideband bus. |
| 188 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 189 | config CPU_BCLK_MHZ |
| 190 | int |
| 191 | default 100 |
| 192 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 193 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 194 | int |
| 195 | default 120 |
| 196 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 197 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 198 | int |
Duncan Laurie | 695f2fe | 2018-12-05 12:51:23 -0800 | [diff] [blame] | 199 | default 216 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 200 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 201 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 202 | int |
| 203 | default 3 |
| 204 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 205 | config SOC_INTEL_I2C_DEV_MAX |
| 206 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 207 | default 4 if SOC_INTEL_CANNONLAKE_PCH_H |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 208 | default 6 |
| 209 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 210 | # Clock divider parameters for 115200 baud rate |
| 211 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 212 | hex |
| 213 | default 0x30 |
| 214 | |
| 215 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 216 | hex |
| 217 | default 0xc35 |
| 218 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 219 | config CHROMEOS |
| 220 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 221 | |
| 222 | config VBOOT |
| 223 | select VBOOT_SEPARATE_VERSTAGE |
| 224 | select VBOOT_OPROM_MATTERS |
| 225 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 226 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 227 | select VBOOT_VBNV_CMOS |
| 228 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 229 | |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 230 | config C_ENV_BOOTBLOCK_SIZE |
| 231 | hex |
Duncan Laurie | 11340e5 | 2018-12-01 16:58:52 -0800 | [diff] [blame] | 232 | default 0xC000 |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 233 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 234 | config CBFS_SIZE |
| 235 | hex |
| 236 | default 0x200000 |
| 237 | |
Rizwan Qureshi | 8aadab7 | 2019-02-17 11:31:21 +0530 | [diff] [blame] | 238 | config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE |
| 239 | bool |
| 240 | default n |
| 241 | help |
| 242 | Select this if the board has a SD_PWR_ENABLE pin connected to a |
| 243 | active high sensing load switch to turn on power to the card reader. |
| 244 | This will enable a workaround in ASL _PS3 and _PS0 methods to force |
| 245 | SD_PWR_ENABLE to stay low in D3. |
| 246 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 247 | choice |
| 248 | prompt "Cache-as-ram implementation" |
| 249 | default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS |
| 250 | default USE_CANNONLAKE_FSP_CAR |
| 251 | help |
| 252 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 253 | |
| 254 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 255 | bool "Enhanced Non-evict mode" |
| 256 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 257 | select INTEL_CAR_NEM_ENHANCED |
| 258 | help |
| 259 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 260 | sizes are derived from the requirement to not write out any modified |
| 261 | cache line. With NEM, if there is no physical memory behind the |
| 262 | cached area, the modified data will be lost and NEM results will be |
| 263 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 264 | kept in cache while clean data is replaced. |
| 265 | |
| 266 | config USE_CANNONLAKE_FSP_CAR |
| 267 | bool "Use FSP CAR" |
| 268 | select FSP_CAR |
| 269 | help |
| 270 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 271 | |
| 272 | endchoice |
| 273 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 274 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 275 | string "Location of FSP headers" |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 276 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
| 277 | default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 278 | |
| 279 | config FSP_FD_PATH |
| 280 | string |
| 281 | depends on FSP_USE_REPO |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 282 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 283 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 284 | endif |