Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Cannonlake support |
| 5 | |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 6 | config SOC_INTEL_COFFEELAKE |
| 7 | bool |
| 8 | default n |
| 9 | select SOC_INTEL_CANNONLAKE |
| 10 | help |
| 11 | Intel Coffeelake support |
| 12 | |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 13 | config SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 14 | bool |
| 15 | default n |
| 16 | help |
| 17 | Choose this option if you have a PCH-H chipset. |
| 18 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 19 | if SOC_INTEL_CANNONLAKE |
| 20 | |
| 21 | config CPU_SPECIFIC_OPTIONS |
| 22 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 23 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 24 | select ACPI_NHLT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 25 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 26 | select ARCH_RAMSTAGE_X86_32 |
| 27 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 28 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 29 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 30 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 31 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 32 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 33 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 34 | select COMMON_FADT |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 35 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 36 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 37 | select HAVE_FSP_GOP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 38 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 39 | select HAVE_MONOTONIC_TIMER |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 40 | select HAVE_SMI_HANDLER |
Aamir Bohra | e462585 | 2018-05-29 10:52:33 +0530 | [diff] [blame] | 41 | select IDT_IN_EVERY_STAGE |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 42 | select INTEL_GMA_ACPI |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 43 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 44 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 45 | select MRC_SETTINGS_PROTECT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 46 | select PARALLEL_MP |
| 47 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 48 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 49 | select POSTCAR_CONSOLE |
| 50 | select POSTCAR_STAGE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 51 | select REG_SCRIPT |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 52 | select SMM_TSEG |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 53 | select SMP |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame] | 54 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 55 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
praveen hodagatta pranesh | dc4fceb | 2018-10-16 18:06:18 +0800 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_SA |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 67 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_PCH_BASE |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_NHLT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 71 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 72 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 73 | select TSC_CONSTANT_RATE |
| 74 | select TSC_MONOTONIC_TIMER |
| 75 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 76 | select UDK_2017_BINDING |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 77 | select DISPLAY_FSP_VERSION_INFO |
Praveen hodagatta pranesh | b66757f | 2018-10-23 02:43:05 +0800 | [diff] [blame^] | 78 | select FSP_T_XIP if FSP_CAR |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 79 | |
| 80 | config UART_DEBUG |
| 81 | bool "Enable UART debug port." |
Subrata Banik | 918ff85 | 2018-06-22 18:55:17 +0530 | [diff] [blame] | 82 | default n |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 83 | select CONSOLE_SERIAL |
| 84 | select BOOTBLOCK_CONSOLE |
| 85 | select DRIVERS_UART |
Lijian Zhao | d37ebdd | 2017-08-30 20:54:16 -0700 | [diff] [blame] | 86 | select DRIVERS_UART_8250MEM_32 |
| 87 | select NO_UART_ON_SUPERIO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 88 | |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 89 | config UART_FOR_CONSOLE |
| 90 | int "Index for LPSS UART port to use for console" |
Lijian Zhao | 0c8237a | 2017-09-14 16:25:18 -0700 | [diff] [blame] | 91 | default 2 if DRIVERS_UART_8250MEM_32 |
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 92 | default 0 |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 93 | help |
| 94 | Index for LPSS UART port to use for console: |
| 95 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 |
| 96 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 97 | config DCACHE_RAM_BASE |
| 98 | default 0xfef00000 |
| 99 | |
| 100 | config DCACHE_RAM_SIZE |
| 101 | default 0x40000 |
| 102 | help |
| 103 | The size of the cache-as-ram region required during bootblock |
| 104 | and/or romstage. |
| 105 | |
| 106 | config DCACHE_BSP_STACK_SIZE |
| 107 | hex |
| 108 | default 0x4000 |
| 109 | help |
| 110 | The amount of anticipated stack usage in CAR by bootblock and |
| 111 | other stages. |
| 112 | |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 113 | config IFD_CHIPSET |
| 114 | string |
| 115 | default "cnl" |
| 116 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 117 | config IED_REGION_SIZE |
| 118 | hex |
| 119 | default 0x400000 |
| 120 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 121 | config HEAP_SIZE |
| 122 | hex |
| 123 | default 0x8000 |
| 124 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 125 | config NHLT_DMIC_1CH_16B |
| 126 | bool |
| 127 | depends on ACPI_NHLT |
| 128 | default n |
| 129 | help |
| 130 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 131 | |
| 132 | config NHLT_DMIC_2CH_16B |
| 133 | bool |
| 134 | depends on ACPI_NHLT |
| 135 | default n |
| 136 | help |
| 137 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 138 | |
| 139 | config NHLT_DMIC_4CH_16B |
| 140 | bool |
| 141 | depends on ACPI_NHLT |
| 142 | default n |
| 143 | help |
| 144 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 145 | |
| 146 | config NHLT_MAX98357 |
| 147 | bool |
| 148 | depends on ACPI_NHLT |
| 149 | default n |
| 150 | help |
| 151 | Include DSP firmware settings for headset codec. |
| 152 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 153 | config NHLT_MAX98373 |
| 154 | bool |
| 155 | depends on ACPI_NHLT |
| 156 | default n |
| 157 | help |
| 158 | Include DSP firmware settings for headset codec. |
| 159 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 160 | config NHLT_DA7219 |
| 161 | bool |
| 162 | depends on ACPI_NHLT |
| 163 | default n |
| 164 | help |
| 165 | Include DSP firmware settings for headset codec. |
| 166 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 167 | config MAX_ROOT_PORTS |
| 168 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 169 | default 24 if SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 170 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 171 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 172 | config SMM_TSEG_SIZE |
| 173 | hex |
| 174 | default 0x800000 |
| 175 | |
Subrata Banik | e66600e | 2018-05-10 17:23:56 +0530 | [diff] [blame] | 176 | config SMM_RESERVED_SIZE |
| 177 | hex |
| 178 | default 0x200000 |
| 179 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 180 | config PCR_BASE_ADDRESS |
| 181 | hex |
| 182 | default 0xfd000000 |
| 183 | help |
| 184 | This option allows you to select MMIO Base Address of sideband bus. |
| 185 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 186 | config CPU_BCLK_MHZ |
| 187 | int |
| 188 | default 100 |
| 189 | |
Lijian Zhao | 903c976 | 2018-08-20 14:06:13 -0700 | [diff] [blame] | 190 | config SOC_INTEL_CANNONLAKE_MEMCFG_INIT |
Nick Vaccaro | 780a1c4 | 2017-12-22 22:50:57 -0800 | [diff] [blame] | 191 | bool |
| 192 | default n |
| 193 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 194 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 195 | int |
| 196 | default 120 |
| 197 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 198 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 199 | int |
Lijian Zhao | e09ba47 | 2018-04-10 10:33:05 -0700 | [diff] [blame] | 200 | default 133 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 201 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 202 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 203 | int |
| 204 | default 3 |
| 205 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 206 | config SOC_INTEL_I2C_DEV_MAX |
| 207 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 208 | default 4 if SOC_INTEL_CANNONLAKE_PCH_H |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 209 | default 6 |
| 210 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 211 | # Clock divider parameters for 115200 baud rate |
| 212 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 213 | hex |
| 214 | default 0x30 |
| 215 | |
| 216 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 217 | hex |
| 218 | default 0xc35 |
| 219 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 220 | config CHROMEOS |
| 221 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 222 | |
| 223 | config VBOOT |
| 224 | select VBOOT_SEPARATE_VERSTAGE |
| 225 | select VBOOT_OPROM_MATTERS |
| 226 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 227 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 228 | select VBOOT_VBNV_CMOS |
| 229 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 230 | |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 231 | config C_ENV_BOOTBLOCK_SIZE |
| 232 | hex |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 233 | default 0x8000 |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 234 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 235 | config CBFS_SIZE |
| 236 | hex |
| 237 | default 0x200000 |
| 238 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 239 | choice |
| 240 | prompt "Cache-as-ram implementation" |
| 241 | default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS |
| 242 | default USE_CANNONLAKE_FSP_CAR |
| 243 | help |
| 244 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 245 | |
| 246 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 247 | bool "Enhanced Non-evict mode" |
| 248 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 249 | select INTEL_CAR_NEM_ENHANCED |
| 250 | help |
| 251 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 252 | sizes are derived from the requirement to not write out any modified |
| 253 | cache line. With NEM, if there is no physical memory behind the |
| 254 | cached area, the modified data will be lost and NEM results will be |
| 255 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 256 | kept in cache while clean data is replaced. |
| 257 | |
| 258 | config USE_CANNONLAKE_FSP_CAR |
| 259 | bool "Use FSP CAR" |
| 260 | select FSP_CAR |
| 261 | help |
| 262 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 263 | |
| 264 | endchoice |
| 265 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 266 | config FSP_HEADER_PATH |
| 267 | string |
| 268 | default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE |
| 269 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE |
| 270 | |
| 271 | config FSP_FD_PATH |
| 272 | string |
| 273 | depends on FSP_USE_REPO |
| 274 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE |
| 275 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 276 | endif |