Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Cannonlake support |
| 5 | |
| 6 | if SOC_INTEL_CANNONLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 11 | select ACPI_NHLT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 12 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 13 | select ARCH_RAMSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 15 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 16 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 18 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 19 | select CACHE_MRC_SETTINGS |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 20 | select COMMON_FADT |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 21 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 23 | select HAVE_FSP_GOP |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 24 | select HAVE_HARD_RESET |
| 25 | select HAVE_INTEL_FIRMWARE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 26 | select HAVE_MONOTONIC_TIMER |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 27 | select HAVE_SMI_HANDLER |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 28 | select INTEL_GMA_ACPI |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 29 | select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 30 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 31 | select MRC_SETTINGS_PROTECT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 32 | select PARALLEL_MP |
| 33 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 34 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 35 | select POSTCAR_CONSOLE |
| 36 | select POSTCAR_STAGE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 37 | select REG_SCRIPT |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 38 | select RELOCATABLE_MODULES |
Lijian Zhao | a77c68a | 2017-07-18 18:14:42 -0700 | [diff] [blame] | 39 | select RELOCATABLE_RAMSTAGE |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 40 | select SMM_TSEG |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 41 | select SMP |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame^] | 42 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_CSE |
Lijian Zhao | 7b2d1ae | 2017-10-30 14:23:56 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_DSP |
Subrata Banik | 47569cf | 2017-10-12 17:59:02 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_EBDA |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Andrey Petrov | c854b49 | 2017-06-05 14:10:17 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_GPIO |
Subrata Banik | 75c6f4a | 2017-11-28 18:37:48 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_GRAPHICS |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_ITSS |
Lijian Zhao | 9bb684a | 2017-10-30 17:03:06 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_I2C |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_LPC |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_LPSS |
Lijian Zhao | 899f5ff | 2017-10-26 12:02:30 -0700 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_P2SB |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_PCR |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_PMC |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 64 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame^] | 65 | select SOC_INTEL_COMMON_BLOCK_SATA |
Bora Guvendik | d2c6365 | 2017-09-19 14:04:37 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_SCS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_SMBUS |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 69 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 5a283ef | 2017-11-07 18:06:36 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_SPI |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 72 | select SOC_INTEL_COMMON_BLOCK_UART |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_NHLT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 75 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 76 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 77 | select TSC_CONSTANT_RATE |
| 78 | select TSC_MONOTONIC_TIMER |
| 79 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 80 | select UDK_2017_BINDING |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 81 | select DISPLAY_FSP_VERSION_INFO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 82 | |
| 83 | config UART_DEBUG |
| 84 | bool "Enable UART debug port." |
| 85 | default y |
| 86 | select CONSOLE_SERIAL |
| 87 | select BOOTBLOCK_CONSOLE |
| 88 | select DRIVERS_UART |
Lijian Zhao | d37ebdd | 2017-08-30 20:54:16 -0700 | [diff] [blame] | 89 | select DRIVERS_UART_8250MEM_32 |
| 90 | select NO_UART_ON_SUPERIO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 91 | |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 92 | config UART_FOR_CONSOLE |
| 93 | int "Index for LPSS UART port to use for console" |
Lijian Zhao | 0c8237a | 2017-09-14 16:25:18 -0700 | [diff] [blame] | 94 | default 2 if DRIVERS_UART_8250MEM_32 |
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 95 | default 0 |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 96 | help |
| 97 | Index for LPSS UART port to use for console: |
| 98 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 |
| 99 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 100 | config DCACHE_RAM_BASE |
| 101 | default 0xfef00000 |
| 102 | |
| 103 | config DCACHE_RAM_SIZE |
| 104 | default 0x40000 |
| 105 | help |
| 106 | The size of the cache-as-ram region required during bootblock |
| 107 | and/or romstage. |
| 108 | |
| 109 | config DCACHE_BSP_STACK_SIZE |
| 110 | hex |
| 111 | default 0x4000 |
| 112 | help |
| 113 | The amount of anticipated stack usage in CAR by bootblock and |
| 114 | other stages. |
| 115 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 116 | config IED_REGION_SIZE |
| 117 | hex |
| 118 | default 0x400000 |
| 119 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 120 | config HEAP_SIZE |
| 121 | hex |
| 122 | default 0x8000 |
| 123 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 124 | config NHLT_DMIC_1CH_16B |
| 125 | bool |
| 126 | depends on ACPI_NHLT |
| 127 | default n |
| 128 | help |
| 129 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 130 | |
| 131 | config NHLT_DMIC_2CH_16B |
| 132 | bool |
| 133 | depends on ACPI_NHLT |
| 134 | default n |
| 135 | help |
| 136 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 137 | |
| 138 | config NHLT_DMIC_4CH_16B |
| 139 | bool |
| 140 | depends on ACPI_NHLT |
| 141 | default n |
| 142 | help |
| 143 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 144 | |
| 145 | config NHLT_MAX98357 |
| 146 | bool |
| 147 | depends on ACPI_NHLT |
| 148 | default n |
| 149 | help |
| 150 | Include DSP firmware settings for headset codec. |
| 151 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 152 | config NHLT_MAX98373 |
| 153 | bool |
| 154 | depends on ACPI_NHLT |
| 155 | default n |
| 156 | help |
| 157 | Include DSP firmware settings for headset codec. |
| 158 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 159 | config NHLT_DA7219 |
| 160 | bool |
| 161 | depends on ACPI_NHLT |
| 162 | default n |
| 163 | help |
| 164 | Include DSP firmware settings for headset codec. |
| 165 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 166 | config MAX_ROOT_PORTS |
| 167 | int |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 168 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 169 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 170 | config SMM_TSEG_SIZE |
| 171 | hex |
| 172 | default 0x800000 |
| 173 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 174 | config PCR_BASE_ADDRESS |
| 175 | hex |
| 176 | default 0xfd000000 |
| 177 | help |
| 178 | This option allows you to select MMIO Base Address of sideband bus. |
| 179 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 180 | config CPU_BCLK_MHZ |
| 181 | int |
| 182 | default 100 |
| 183 | |
Nick Vaccaro | 780a1c4 | 2017-12-22 22:50:57 -0800 | [diff] [blame] | 184 | config SOC_INTEL_CANNONLAKE_LPDDR4_INIT |
| 185 | bool |
| 186 | default n |
| 187 | |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 188 | config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ |
| 189 | int |
| 190 | default 120 |
| 191 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 192 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 193 | int |
| 194 | default SOC_INTEL_COMMON_LPSS_CLOCK_MHZ |
| 195 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 196 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 197 | int |
| 198 | default 3 |
| 199 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 200 | # Clock divider parameters for 115200 baud rate |
| 201 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 202 | hex |
| 203 | default 0x30 |
| 204 | |
| 205 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 206 | hex |
| 207 | default 0xc35 |
| 208 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 209 | config CHROMEOS |
| 210 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 211 | |
| 212 | config VBOOT |
| 213 | select VBOOT_SEPARATE_VERSTAGE |
| 214 | select VBOOT_OPROM_MATTERS |
| 215 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 216 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 217 | select VBOOT_VBNV_CMOS |
| 218 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 219 | |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 220 | config C_ENV_BOOTBLOCK_SIZE |
| 221 | hex |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 222 | default 0x8000 |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 223 | |
John Zhao | 9b6384c | 2017-10-11 19:09:21 -0700 | [diff] [blame] | 224 | config STACK_SIZE |
| 225 | hex |
| 226 | default 0x2000 |
| 227 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 228 | choice |
| 229 | prompt "Cache-as-ram implementation" |
| 230 | default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS |
| 231 | default USE_CANNONLAKE_FSP_CAR |
| 232 | help |
| 233 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 234 | |
| 235 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 236 | bool "Enhanced Non-evict mode" |
| 237 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 238 | select INTEL_CAR_NEM_ENHANCED |
| 239 | help |
| 240 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 241 | sizes are derived from the requirement to not write out any modified |
| 242 | cache line. With NEM, if there is no physical memory behind the |
| 243 | cached area, the modified data will be lost and NEM results will be |
| 244 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 245 | kept in cache while clean data is replaced. |
| 246 | |
| 247 | config USE_CANNONLAKE_FSP_CAR |
| 248 | bool "Use FSP CAR" |
| 249 | select FSP_CAR |
| 250 | help |
| 251 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 252 | |
| 253 | endchoice |
| 254 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 255 | endif |