Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 14 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 15 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 16 | #include <cpu/x86/post_code.h> |
| 17 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 18 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 19 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 20 | |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 21 | #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) |
| 22 | #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" |
| 23 | #endif |
| 24 | #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 25 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 26 | .global bootblock_pre_c_entry |
| 27 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 28 | .code32 |
| 29 | _cache_as_ram_setup: |
| 30 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 31 | bootblock_pre_c_entry: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 32 | |
| 33 | cache_as_ram: |
| 34 | post_code(0x20) |
| 35 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 36 | /* Clear/disable fixed MTRRs */ |
| 37 | mov $fixed_mtrr_list_size, %ebx |
| 38 | xor %eax, %eax |
| 39 | xor %edx, %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 40 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 41 | clear_fixed_mtrr: |
| 42 | add $-2, %ebx |
| 43 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 44 | wrmsr |
| 45 | jnz clear_fixed_mtrr |
| 46 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 47 | /* Figure out how many MTRRs we have, and clear them out */ |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 48 | mov $MTRR_CAP_MSR, %ecx |
| 49 | rdmsr |
| 50 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 51 | mov $MTRR_PHYS_BASE(0), %ecx |
| 52 | xor %eax, %eax |
| 53 | xor %edx, %edx |
| 54 | |
| 55 | clear_var_mtrr: |
| 56 | wrmsr |
| 57 | inc %ecx |
| 58 | wrmsr |
| 59 | inc %ecx |
| 60 | dec %ebx |
| 61 | jnz clear_var_mtrr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 62 | post_code(0x21) |
| 63 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 64 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 65 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 66 | rdmsr |
| 67 | andl $(~0x00000cff), %eax |
| 68 | wrmsr |
| 69 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 70 | post_code(0x22) |
| 71 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 72 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 73 | movl $1, %eax |
| 74 | cpuid |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 75 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 76 | jz addrsize_set_high |
| 77 | movl $0x0f, %edx |
| 78 | |
| 79 | /* Preload high word of address mask (in %edx) for Variable |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 80 | MTRRs 0 and 1. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 81 | addrsize_set_high: |
| 82 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 83 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 84 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 85 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 86 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 87 | |
| 88 | post_code(0x2a) |
| 89 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 90 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 91 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 92 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 93 | xorl %edx, %edx |
| 94 | wrmsr |
| 95 | |
| 96 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 97 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 98 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 99 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 100 | wrmsr |
| 101 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 102 | post_code(0x2b) |
| 103 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 104 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 105 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 106 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 107 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 108 | wrmsr |
| 109 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 110 | post_code(0x2c) |
| 111 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 112 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 113 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 114 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 115 | invd |
| 116 | movl %eax, %cr0 |
| 117 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 118 | /* Read then clear the CAR region. This will also fill up the cache. |
| 119 | * IMPORTANT: The read is mandatory. |
| 120 | */ |
| 121 | movl $CACHE_AS_RAM_BASE, %esi |
| 122 | movl %esi, %edi |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 123 | cld |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 124 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 125 | rep lodsl |
| 126 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 127 | xorl %eax, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 128 | rep stosl |
| 129 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 130 | post_code(0x2d) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 131 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 132 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 133 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 134 | movl %eax, %cr0 |
| 135 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 136 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 137 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 138 | xorl %edx, %edx |
| 139 | /* |
| 140 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame] | 141 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 142 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 143 | movl $_program, %eax |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 144 | andl $(~(XIP_ROM_SIZE - 1)), %eax |
Kyösti Mälkki | dc4820b | 2016-07-21 19:51:01 +0300 | [diff] [blame] | 145 | orl $MTRR_TYPE_WRPROT, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 146 | wrmsr |
| 147 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 148 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 149 | rdmsr |
Arthur Heymans | 942ad6a | 2019-10-12 18:06:46 +0200 | [diff] [blame] | 150 | movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 151 | wrmsr |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 152 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 153 | post_code(0x2e) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 154 | /* Enable cache. */ |
| 155 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 156 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 157 | movl %eax, %cr0 |
| 158 | |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 159 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 160 | mov $_ecar_stack, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 161 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 162 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 163 | the pushes below. */ |
| 164 | andl $0xfffffff0, %esp |
| 165 | subl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 166 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 167 | /* push TSC and BIST to stack */ |
| 168 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 169 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 170 | movd %mm2, %eax |
| 171 | pushl %eax /* tsc[63:32] */ |
| 172 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 173 | pushl %eax /* tsc[31:0] */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 174 | |
| 175 | before_c_entry: |
| 176 | post_code(0x29) |
| 177 | call bootblock_c_entry_bist |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 178 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 179 | /* Should never see this postcode */ |
| 180 | post_code(POST_DEAD_CODE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 181 | |
| 182 | .Lhlt: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 183 | hlt |
| 184 | jmp .Lhlt |
| 185 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 186 | fixed_mtrr_list: |
| 187 | .word MTRR_FIX_64K_00000 |
| 188 | .word MTRR_FIX_16K_80000 |
| 189 | .word MTRR_FIX_16K_A0000 |
| 190 | .word MTRR_FIX_4K_C0000 |
| 191 | .word MTRR_FIX_4K_C8000 |
| 192 | .word MTRR_FIX_4K_D0000 |
| 193 | .word MTRR_FIX_4K_D8000 |
| 194 | .word MTRR_FIX_4K_E0000 |
| 195 | .word MTRR_FIX_4K_E8000 |
| 196 | .word MTRR_FIX_4K_F0000 |
| 197 | .word MTRR_FIX_4K_F8000 |
| 198 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 199 | |
| 200 | _cache_as_ram_setup_end: |