Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 3 | #define PORTSCN_OFFSET 0x480 |
| 4 | #define PORTSCXUSB3_OFFSET 0x540 |
| 5 | |
| 6 | #define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 |
| 7 | #define RO_BITS_OFF_MASK ~0x80FE0012 |
| 8 | |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 9 | /* |
| 10 | * USB Port Wake Enable (UPWE) on usb attach/detach |
| 11 | * Arg0 - Port Number |
| 12 | * Arg1 - Port 1 Status and control offset |
| 13 | * Arg2 - xHCI Memory-mapped address |
| 14 | */ |
| 15 | Method (UPWE, 3, Serialized) |
| 16 | { |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 17 | Local0 = Arg1 + ((Arg0 - 1) * 0x10) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 18 | |
| 19 | /* Map ((XMEM << 16) + Local0 in PSCR */ |
| 20 | OperationRegion (PSCR, SystemMemory, |
| 21 | Add (ShiftLeft (Arg2, 16), Local0), 0x10) |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 22 | Field (PSCR, DWordAcc, NoLock, Preserve) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 23 | { |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 24 | PSCT, 32, |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 25 | } |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 26 | Local0 = PSCT |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 27 | /* |
| 28 | * And port status/control reg with RO and RWS bits |
| 29 | * RO bits: 0, 2:3, 10:13, 24, 28:30 |
| 30 | * RWS bits: 5:9, 14:16, 25:27 |
| 31 | */ |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 32 | Local0 = Local0 & RO_BITS_OFF_MASK |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 33 | /* Set WCE and WDE bits */ |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 34 | Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE |
| 35 | PSCT = Local0 |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | /* |
| 39 | * USB Wake Enable Setup (UWES) |
| 40 | * Arg0 - Port enable bitmap |
| 41 | * Arg1 - Port 1 Status and control offset |
| 42 | * Arg2 - xHCI Memory-mapped address |
| 43 | */ |
| 44 | Method (UWES, 3, Serialized) |
| 45 | { |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 46 | Local0 = Arg0 |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 47 | |
| 48 | While (One) { |
| 49 | FindSetRightBit (Local0, Local1) |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 50 | If (Local1 == Zero) { |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 51 | Break |
| 52 | } |
| 53 | UPWE (Local1, Arg1, Arg2) |
| 54 | /* |
| 55 | * Clear the lowest set bit in Local0 since it was |
| 56 | * processed. |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 57 | */ |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 58 | Local0 = Local0 & (Local0 - 1) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 59 | } |
| 60 | } |
| 61 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 62 | /* XHCI Controller 0:14.0 */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 63 | |
| 64 | Device (XHCI) |
| 65 | { |
| 66 | Name (_ADR, 0x00140000) |
| 67 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 68 | Name (_PRW, Package () { GPE0_PME_B0, 3 }) |
| 69 | |
| 70 | Method (_DSW, 3) |
| 71 | { |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 72 | PMEE = Arg0 |
| 73 | UWES ((\U2WE & 0x3FF), PORTSCN_OFFSET, XMEM) |
| 74 | UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | Name (_S3D, 3) /* D3 supported in S3 */ |
| 78 | Name (_S4D, 3) /* D3 supported in S4 */ |
| 79 | Name (_S0W, 3) /* D3 can wake device in S0 */ |
| 80 | Name (_S3W, 3) /* D3 can wake system from S3 */ |
| 81 | Name (_S4W, 3) /* D3 can wake system from S4 */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 82 | |
| 83 | OperationRegion (XPRT, PCI_Config, 0x00, 0x100) |
| 84 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 85 | { |
| 86 | Offset (0x0), |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 87 | DVID, 16, /* VENDORID */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 88 | Offset (0x10), |
| 89 | , 16, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 90 | XMEM, 16, /* MEM_BASE */ |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 91 | Offset (0x50), /* XHCLKGTEN */ |
| 92 | , 2, |
| 93 | STGE, 1, /* SS Link Trunk clock gating enable */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 94 | Offset (0x74), |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 95 | D0D3, 2, /* POWERSTATE */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 96 | , 6, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 97 | PMEE, 1, /* PME_EN */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 98 | , 6, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 99 | PMES, 1, /* PME_STS */ |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 100 | Offset (0xA2), |
| 101 | , 2, |
| 102 | D3HE, 1, /* D3_hot_en */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 103 | } |
| 104 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 105 | OperationRegion (XREG, SystemMemory, |
| 106 | Add (ShiftLeft (XMEM, 16), 0x8000), 0x200) |
| 107 | Field (XREG, DWordAcc, Lock, Preserve) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 108 | { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 109 | Offset (0x1c4), /* USB2PMCTRL */ |
| 110 | , 2, |
| 111 | UPSW, 2, /* U2PSUSPGP */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 114 | Method (_PSC, 0, Serialized) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 115 | { |
| 116 | Return (^D0D3) |
| 117 | } |
| 118 | |
| 119 | Method (_PS0, 0, Serialized) |
| 120 | { |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 121 | If (!LEqual (^DVID, 0xFFFF)) { |
| 122 | If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 123 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 124 | /* Disable d3hot and SS link trunk clock gating */ |
| 125 | Store(Zero, ^D3HE) |
| 126 | Store(Zero, ^STGE) |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 127 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 128 | /* If device is in D3, set back to D0 */ |
| 129 | If (LEqual (^D0D3, 3)) { |
| 130 | Store (Zero, Local0) |
| 131 | Store (Local0, ^D0D3) |
| 132 | Store (^D0D3, Local0) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 133 | } |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 134 | |
| 135 | /* Disable USB2 PHY SUS Well Power Gating */ |
| 136 | Store (Zero, ^UPSW) |
| 137 | |
| 138 | /* |
| 139 | * Apply USB2 PHPY Power Gating workaround if needed. |
| 140 | */ |
| 141 | If (^^PMC.UWAB) { |
| 142 | /* Write to MTPMC to have PMC disable power gating */ |
| 143 | Store (1, ^^PMC.MPMC) |
| 144 | |
| 145 | /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ |
| 146 | Store (10, Local0) |
| 147 | While (^^PMC.PMFS) { |
| 148 | If (LNot (Local0)) { |
| 149 | Break |
| 150 | } |
| 151 | Decrement (Local0) |
| 152 | Sleep (10) |
| 153 | } |
| 154 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 155 | } |
| 156 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 157 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 158 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 159 | Method (_PS3, 0, Serialized) |
| 160 | { |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 161 | If (!LEqual (^DVID, 0xFFFF)) { |
| 162 | If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 163 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 164 | /* Clear PME Status */ |
| 165 | Store (1, ^PMES) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 166 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 167 | /* Enable PME */ |
| 168 | Store (1, ^PMEE) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 169 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 170 | /* If device is in D3, set back to D0 */ |
| 171 | If (LEqual (^D0D3, 3)) { |
| 172 | Store (Zero, Local0) |
| 173 | Store (Local0, ^D0D3) |
| 174 | Store (^D0D3, Local0) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 175 | } |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 176 | |
| 177 | /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ |
| 178 | Store (3, ^UPSW) |
| 179 | |
| 180 | /* Enable d3hot and SS link trunk clock gating */ |
| 181 | Store(One, ^D3HE) |
| 182 | Store(One, ^STGE) |
| 183 | |
| 184 | /* Now put device in D3 */ |
| 185 | Store (3, Local0) |
| 186 | Store (Local0, ^D0D3) |
| 187 | Store (^D0D3, Local0) |
| 188 | |
| 189 | /* |
| 190 | * Apply USB2 PHPY Power Gating workaround if needed. |
| 191 | * This code assumes XDCI is disabled, if it is enabled |
| 192 | * then this must also check if it is in D3 state too. |
| 193 | */ |
| 194 | If (^^PMC.UWAB) { |
| 195 | /* Write to MTPMC to have PMC enable power gating */ |
| 196 | Store (3, ^^PMC.MPMC) |
| 197 | |
| 198 | /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ |
| 199 | Store (10, Local0) |
| 200 | While (^^PMC.PMFS) { |
| 201 | If (LNot (Local0)) { |
| 202 | Break |
| 203 | } |
| 204 | Decrement (Local0) |
| 205 | Sleep (10) |
| 206 | } |
| 207 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 208 | } |
| 209 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 210 | } |
| 211 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 212 | /* Root Hub for Skylake-LP PCH */ |
| 213 | Device (RHUB) |
| 214 | { |
| 215 | Name (_ADR, Zero) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 216 | |
Matt DeVillier | dc1b781 | 2017-04-22 16:36:10 -0500 | [diff] [blame] | 217 | // GPLD: Generate Port Location Data (PLD) |
| 218 | Method (GPLD, 1, Serialized) |
| 219 | { |
| 220 | |
| 221 | Name (PCKG, Package (0x01) |
| 222 | { |
| 223 | Buffer (0x10) {} |
| 224 | }) |
| 225 | |
| 226 | // REV: Revision 0x02 for ACPI 5.0 |
| 227 | CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 228 | REV = 0x02 |
Matt DeVillier | dc1b781 | 2017-04-22 16:36:10 -0500 | [diff] [blame] | 229 | |
| 230 | // VISI: Port visibility to user per port |
| 231 | CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) |
Edward O'Callaghan | ed31024 | 2020-06-30 13:39:01 +1000 | [diff] [blame^] | 232 | VISI = Arg0 |
Matt DeVillier | dc1b781 | 2017-04-22 16:36:10 -0500 | [diff] [blame] | 233 | |
| 234 | Return (PCKG) |
| 235 | } |
| 236 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 237 | /* USB2 */ |
| 238 | Device (HS01) { Name (_ADR, 1) } |
| 239 | Device (HS02) { Name (_ADR, 2) } |
| 240 | Device (HS03) { Name (_ADR, 3) } |
| 241 | Device (HS04) { Name (_ADR, 4) } |
| 242 | Device (HS05) { Name (_ADR, 5) } |
| 243 | Device (HS06) { Name (_ADR, 6) } |
| 244 | Device (HS07) { Name (_ADR, 7) } |
| 245 | Device (HS08) { Name (_ADR, 8) } |
| 246 | Device (HS09) { Name (_ADR, 9) } |
| 247 | Device (HS10) { Name (_ADR, 10) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 248 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 249 | /* USBr */ |
| 250 | Device (USR1) { Name (_ADR, 11) } |
| 251 | Device (USR2) { Name (_ADR, 12) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 252 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 253 | /* USB3 */ |
| 254 | Device (SS01) { Name (_ADR, 13) } |
| 255 | Device (SS02) { Name (_ADR, 14) } |
| 256 | Device (SS03) { Name (_ADR, 15) } |
| 257 | Device (SS04) { Name (_ADR, 16) } |
| 258 | Device (SS05) { Name (_ADR, 17) } |
| 259 | Device (SS06) { Name (_ADR, 18) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 260 | } |
| 261 | } |