Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | // XHCI Controller 0:14.0 |
| 22 | |
| 23 | Device (XHCI) |
| 24 | { |
| 25 | Name (_ADR, 0x00140000) |
| 26 | |
| 27 | Name (PLSD, 5) // Port Link State - RxDetect |
| 28 | Name (PLSP, 7) // Port Link State - Polling |
| 29 | |
| 30 | OperationRegion (XPRT, PCI_Config, 0x00, 0x100) |
| 31 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 32 | { |
| 33 | Offset (0x0), |
| 34 | DVID, 16, |
| 35 | Offset (0x10), |
| 36 | , 16, |
| 37 | XMEM, 16, // MEM_BASE |
| 38 | Offset (0x40), |
| 39 | , 11, |
| 40 | SWAI, 1, |
| 41 | , 20, |
| 42 | Offset (0x44), |
| 43 | , 12, |
| 44 | SAIP, 2, |
| 45 | , 18, |
| 46 | Offset (0x74), |
| 47 | D0D3, 2, |
| 48 | , 6, |
| 49 | PMEE, 1, // PME_EN |
| 50 | , 6, |
| 51 | PMES, 1, // PME_STS |
| 52 | Offset (0xb0), |
| 53 | , 13, |
| 54 | MB13, 1, |
| 55 | MB14, 1, |
| 56 | Offset (0xd0), |
| 57 | PR2R, 32, // USB2PR |
| 58 | PR2M, 32, // USB2PRM |
| 59 | PR3R, 32, // USB3PR |
| 60 | PR3M, 32, // USB3PRM |
| 61 | } |
| 62 | |
| 63 | // Clear status bits |
| 64 | Method (LPCL, 0, Serialized) |
| 65 | { |
| 66 | OperationRegion (XREG, SystemMemory, |
| 67 | ShiftLeft (^XMEM, 16), 0x600) |
| 68 | Field (XREG, DWordAcc, Lock, Preserve) |
| 69 | { |
| 70 | Offset (0x510), // PORTSCNUSB3[0] |
| 71 | PSC0, 32, |
| 72 | Offset (0x520), // PORTSCNUSB3[1] |
| 73 | PSC1, 32, |
| 74 | Offset (0x530), // PORTSCNUSB3[2] |
| 75 | PSC2, 32, |
| 76 | Offset (0x540), // PORTSCNUSB3[3] |
| 77 | PSC3, 32, |
| 78 | } |
| 79 | |
| 80 | // Port Enabled/Disabled (Bit 1) |
| 81 | Name (PEDB, ShiftLeft (1, 1)) |
| 82 | |
| 83 | // Change Status (Bits 23:17) |
| 84 | Name (CHST, ShiftLeft (0x7f, 17)) |
| 85 | |
| 86 | // Port 0 |
| 87 | And (PSC0, Not (PEDB), Local0) |
| 88 | Or (Local0, CHST, PSC0) |
| 89 | |
| 90 | // Port 1 |
| 91 | And (PSC1, Not (PEDB), Local0) |
| 92 | Or (Local0, CHST, PSC1) |
| 93 | |
| 94 | // Port 2 |
| 95 | And (PSC2, Not (PEDB), Local0) |
| 96 | Or (Local0, CHST, PSC2) |
| 97 | |
| 98 | // Port 3 |
| 99 | And (PSC3, Not (PEDB), Local0) |
| 100 | Or (Local0, CHST, PSC3) |
| 101 | } |
| 102 | |
| 103 | Method (LPS0, 0, Serialized) |
| 104 | { |
| 105 | OperationRegion (XREG, SystemMemory, |
| 106 | ShiftLeft (^XMEM, 16), 0x600) |
| 107 | Field (XREG, DWordAcc, Lock, Preserve) |
| 108 | { |
| 109 | Offset (0x510), // PORTSCNUSB3 |
| 110 | , 5, |
| 111 | PLS1, 4, // [8:5] Port Link State |
| 112 | PPR1, 1, // [9] Port Power |
| 113 | , 7, |
| 114 | CSC1, 1, // [17] Connect Status Change |
| 115 | , 1, |
| 116 | WRC1, 1, // [19] Warm Port Reset Change |
| 117 | , 11, |
| 118 | WPR1, 1, // [31] Warm Port Reset |
| 119 | Offset (0x520), // PORTSCNUSB3 |
| 120 | , 5, |
| 121 | PLS2, 4, // [8:5] Port Link State |
| 122 | PPR2, 1, // [9] Port Power |
| 123 | , 7, |
| 124 | CSC2, 1, // [17] Connect Status Change |
| 125 | , 1, |
| 126 | WRC2, 1, // [19] Warm Port Reset Change |
| 127 | , 11, |
| 128 | WPR2, 1, // [31] Warm Port Reset |
| 129 | Offset (0x530), // PORTSCNUSB3 |
| 130 | , 5, |
| 131 | PLS3, 4, // [8:5] Port Link State |
| 132 | PPR3, 1, // [9] Port Power |
| 133 | , 7, |
| 134 | CSC3, 1, // [17] Connect Status Change |
| 135 | , 1, |
| 136 | WRC3, 1, // [19] Warm Port Reset Change |
| 137 | , 11, |
| 138 | WPR3, 1, // [31] Warm Port Reset |
| 139 | Offset (0x540), // PORTSCNUSB3 |
| 140 | , 5, |
| 141 | PLS4, 4, // [8:5] Port Link State |
| 142 | PPR4, 1, // [9] Port Power |
| 143 | , 7, |
| 144 | CSC4, 1, // [17] Connect Status Change |
| 145 | , 1, |
| 146 | WRC4, 1, // [19] Warm Port Reset Change |
| 147 | , 11, |
| 148 | WPR4, 1, // [31] Warm Port Reset |
| 149 | } |
| 150 | |
| 151 | // Wait for all powered ports to finish polling |
| 152 | Store (10, Local0) |
| 153 | While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), |
| 154 | LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), |
| 155 | LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), |
| 156 | LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) |
| 157 | { |
| 158 | If (LEqual (Local0, 0)) { |
| 159 | Break |
| 160 | } |
| 161 | Decrement (Local0) |
| 162 | Stall (10) |
| 163 | } |
| 164 | |
| 165 | // For each USB3 Port: |
| 166 | // If port is disconnected (PLS=5 PP=1 CSC=0) |
| 167 | // 1) Issue warm reset (WPR=1) |
| 168 | // 2) Poll for warm reset complete (WRC=0) |
| 169 | // 3) Write 1 to port status to clear |
| 170 | |
| 171 | // Local# indicate if port is reset |
| 172 | Store (0, Local1) |
| 173 | Store (0, Local2) |
| 174 | Store (0, Local3) |
| 175 | Store (0, Local4) |
| 176 | |
| 177 | If (LAnd (LEqual (PLS1, PLSD), |
| 178 | LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { |
| 179 | Store (1, WPR1) // Issue warm reset |
| 180 | Store (1, Local1) |
| 181 | } |
| 182 | If (LAnd (LEqual (PLS2, PLSD), |
| 183 | LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { |
| 184 | Store (1, WPR2) // Issue warm reset |
| 185 | Store (1, Local2) |
| 186 | } |
| 187 | If (LAnd (LEqual (PLS3, PLSD), |
| 188 | LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { |
| 189 | Store (1, WPR3) // Issue warm reset |
| 190 | Store (1, Local3) |
| 191 | } |
| 192 | If (LAnd (LEqual (PLS4, PLSD), |
| 193 | LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { |
| 194 | Store (1, WPR4) // Issue warm reset |
| 195 | Store (1, Local4) |
| 196 | } |
| 197 | |
| 198 | // Poll for warm reset complete on all ports that were reset |
| 199 | Store (10, Local0) |
| 200 | While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), |
| 201 | LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), |
| 202 | LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), |
| 203 | LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) |
| 204 | { |
| 205 | If (LEqual (Local0, 0)) { |
| 206 | Break |
| 207 | } |
| 208 | Decrement (Local0) |
| 209 | Stall (10) |
| 210 | } |
| 211 | |
| 212 | // Clear status bits in all ports |
| 213 | LPCL () |
| 214 | } |
| 215 | |
| 216 | Method (_PSC, 0, NotSerialized) |
| 217 | { |
| 218 | Return (^D0D3) |
| 219 | } |
| 220 | |
| 221 | Method (_PS0, 0, Serialized) |
| 222 | { |
| 223 | If (LEqual (^DVID, 0xFFFF)) { |
| 224 | Return () |
| 225 | } |
| 226 | If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
| 227 | Return () |
| 228 | } |
| 229 | |
| 230 | OperationRegion (XREG, SystemMemory, |
| 231 | Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) |
| 232 | Field (XREG, DWordAcc, Lock, Preserve) |
| 233 | { |
| 234 | Offset (0x0e0), // AUX Reset Control 1 |
| 235 | , 15, |
| 236 | AX15, 1, |
| 237 | Offset (0x154), // AUX Domain PM Control Register 2 |
| 238 | , 31, |
| 239 | CLK2, 1, |
| 240 | Offset (0x16c), // AUX Clock Control |
| 241 | , 2, |
| 242 | CLK0, 1, |
| 243 | , 11, |
| 244 | CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable |
| 245 | } |
| 246 | |
| 247 | // If device is in D3, set back to D0 |
| 248 | Store (^D0D3, Local0) |
| 249 | if (LEqual (Local0, 3)) { |
| 250 | Store (0, ^D0D3) |
| 251 | } |
| 252 | |
| 253 | if (LNot (\ISWP())) { |
| 254 | // Clear PCI 0xB0[14:13] |
| 255 | Store (0, ^MB13) |
| 256 | Store (0, ^MB14) |
| 257 | |
| 258 | // Clear MMIO 0x816C[14,2] |
| 259 | Store (0, CLK0) |
| 260 | Store (0, CLK1) |
| 261 | |
| 262 | // Set MMIO 0x8154[31] |
| 263 | Store (1, CLK2) |
| 264 | |
| 265 | // Handle per-port reset if needed |
| 266 | LPS0 () |
| 267 | |
| 268 | // Set MMIO 0x80e0[15] |
| 269 | Store (1, AX15) |
| 270 | |
| 271 | // Clear PCI CFG offset 0x40[11] |
| 272 | Store (0, ^SWAI) |
| 273 | |
| 274 | // Clear PCI CFG offset 0x44[13:12] |
| 275 | Store (0, ^SAIP) |
| 276 | } |
| 277 | |
| 278 | Return () |
| 279 | } |
| 280 | |
| 281 | Method (_PS3, 0, Serialized) |
| 282 | { |
| 283 | If (LEqual (^DVID, 0xFFFF)) { |
| 284 | Return () |
| 285 | } |
| 286 | If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
| 287 | Return () |
| 288 | } |
| 289 | |
| 290 | OperationRegion (XREG, SystemMemory, |
| 291 | Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) |
| 292 | Field (XREG, DWordAcc, Lock, Preserve) |
| 293 | { |
| 294 | Offset (0x0e0), // AUX Reset Control 1 |
| 295 | , 15, |
| 296 | AX15, 1, |
| 297 | Offset (0x154), // AUX Domain PM Control Register 2 |
| 298 | , 31, |
| 299 | CLK2, 1, |
| 300 | Offset (0x16c), // AUX Clock Control |
| 301 | , 2, |
| 302 | CLK0, 1, |
| 303 | , 11, |
| 304 | CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable |
| 305 | } |
| 306 | |
| 307 | Store (1, ^PMES) // Clear PME Status |
| 308 | Store (1, ^PMEE) // Enable PME |
| 309 | |
| 310 | // If device is in D3, set back to D0 |
| 311 | Store (^D0D3, Local0) |
| 312 | if (LEqual (Local0, 3)) { |
| 313 | Store (0, ^D0D3) |
| 314 | } |
| 315 | |
| 316 | if (LNot (\ISWP())) { |
| 317 | // Set PCI 0xB0[14:13] |
| 318 | Store (1, ^MB13) |
| 319 | Store (1, ^MB14) |
| 320 | |
| 321 | // Set MMIO 0x816C[14,2] |
| 322 | Store (1, CLK0) |
| 323 | Store (1, CLK1) |
| 324 | |
| 325 | // Clear MMIO 0x8154[31] |
| 326 | Store (0, CLK2) |
| 327 | |
| 328 | // Clear MMIO 0x80e0[15] |
| 329 | Store (0, AX15) |
| 330 | |
| 331 | // Set PCI CFG offset 0x40[11] |
| 332 | Store (1, ^SWAI) |
| 333 | |
| 334 | // Set PCI CFG offset 0x44[13:12] |
| 335 | Store (1, ^SAIP) |
| 336 | } |
| 337 | |
| 338 | // Put device in D3 |
| 339 | Store (3, ^D0D3) |
| 340 | |
| 341 | Return () |
| 342 | } |
| 343 | |
| 344 | Name (_PRW, Package(){ 0x6d, 3 }) |
| 345 | |
| 346 | // Leave USB ports on for to allow Wake from USB |
| 347 | |
| 348 | Method(_S3D,0) // Highest D State in S3 State |
| 349 | { |
| 350 | Return (3) |
| 351 | } |
| 352 | |
| 353 | Method(_S4D,0) // Highest D State in S4 State |
| 354 | { |
| 355 | Return (3) |
| 356 | } |
| 357 | |
| 358 | Device (HUB7) |
| 359 | { |
| 360 | Name (_ADR, 0x00000000) |
| 361 | |
| 362 | // How many are there? |
| 363 | Device (PRT1) { Name (_ADR, 1) } // USB Port 0 |
| 364 | Device (PRT2) { Name (_ADR, 2) } // USB Port 1 |
| 365 | Device (PRT3) { Name (_ADR, 3) } // USB Port 2 |
| 366 | Device (PRT4) { Name (_ADR, 4) } // USB Port 3 |
| 367 | Device (PRT5) { Name (_ADR, 5) } // USB Port 4 |
| 368 | Device (PRT6) { Name (_ADR, 6) } // USB Port 5 |
| 369 | } |
| 370 | } |
| 371 | |