soc/intel/skylake: Enable XHCI clock gate control in ACPI
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 96f3b6a..4c6625e 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -93,12 +93,18 @@
Offset (0x10),
, 16,
XMEM, 16, /* MEM_BASE */
+ Offset (0x50), /* XHCLKGTEN */
+ , 2,
+ STGE, 1, /* SS Link Trunk clock gating enable */
Offset (0x74),
D0D3, 2, /* POWERSTATE */
, 6,
PMEE, 1, /* PME_EN */
, 6,
PMES, 1, /* PME_STS */
+ Offset (0xA2),
+ , 2,
+ D3HE, 1, /* D3_hot_en */
}
OperationRegion (XREG, SystemMemory,
@@ -124,6 +130,10 @@
Return
}
+ /* Disable d3hot and SS link trunk clock gating */
+ Store(Zero, ^D3HE)
+ Store(Zero, ^STGE)
+
/* If device is in D3, set back to D0 */
If (LEqual (^D0D3, 3)) {
Store (Zero, Local0)
@@ -178,6 +188,10 @@
/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
Store (3, ^UPSW)
+ /* Enable d3hot and SS link trunk clock gating */
+ Store(One, ^D3HE)
+ Store(One, ^STGE)
+
/* Now put device in D3 */
Store (3, Local0)
Store (Local0, ^D0D3)