Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 3 | |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 4 | /* |
| 5 | * USB Port Wake Enable (UPWE) on usb attach/detach |
| 6 | * Arg0 - Port Number |
| 7 | * Arg1 - Port 1 Status and control offset |
| 8 | * Arg2 - xHCI Memory-mapped address |
| 9 | */ |
| 10 | Method (UPWE, 3, Serialized) |
| 11 | { |
| 12 | /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ |
| 13 | Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) |
| 14 | |
| 15 | /* Map ((XMEM << 16) + Local0 in PSCR */ |
| 16 | OperationRegion (PSCR, SystemMemory, |
| 17 | Add (ShiftLeft (Arg2, 16), Local0), 0x10) |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 18 | Field (PSCR, DWordAcc, NoLock, Preserve) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 19 | { |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 20 | PSCT, 32, |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 21 | } |
Kane Chen | c3892c8 | 2018-02-23 10:11:27 +0800 | [diff] [blame] | 22 | Store(PSCT, Local0) |
| 23 | /* |
| 24 | * And port status/control reg with RO and RWS bits |
| 25 | * RO bits: 0, 2:3, 10:13, 24, 28:30 |
| 26 | * RWS bits: 5:9, 14:16, 25:27 |
| 27 | */ |
| 28 | And (Local0, ~0x80FE0012, Local0) |
| 29 | /* Set WCE and WDE bits */ |
| 30 | Or (Local0, 0x6000000, Local0) |
| 31 | Store(Local0, PSCT) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | /* |
| 35 | * USB Wake Enable Setup (UWES) |
| 36 | * Arg0 - Port enable bitmap |
| 37 | * Arg1 - Port 1 Status and control offset |
| 38 | * Arg2 - xHCI Memory-mapped address |
| 39 | */ |
| 40 | Method (UWES, 3, Serialized) |
| 41 | { |
| 42 | Store (Arg0, Local0) |
| 43 | |
| 44 | While (One) { |
| 45 | FindSetRightBit (Local0, Local1) |
| 46 | If (LEqual (Local1, Zero)) { |
| 47 | Break |
| 48 | } |
| 49 | UPWE (Local1, Arg1, Arg2) |
| 50 | /* |
| 51 | * Clear the lowest set bit in Local0 since it was |
| 52 | * processed. |
| 53 | * Local0 = Local0 & (Local0 - 1) |
| 54 | */ |
| 55 | And (Local0, Subtract (Local0, 1), Local0) |
| 56 | } |
| 57 | } |
| 58 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 59 | /* XHCI Controller 0:14.0 */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 60 | |
| 61 | Device (XHCI) |
| 62 | { |
| 63 | Name (_ADR, 0x00140000) |
| 64 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 65 | Name (_PRW, Package () { GPE0_PME_B0, 3 }) |
| 66 | |
| 67 | Method (_DSW, 3) |
| 68 | { |
| 69 | Store (Arg0, PMEE) |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 70 | UWES (And (\U2WE, 0x3FF), 0x480, XMEM) |
| 71 | UWES (And (\U3WE, 0x3F), 0x540, XMEM) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | Name (_S3D, 3) /* D3 supported in S3 */ |
| 75 | Name (_S4D, 3) /* D3 supported in S4 */ |
| 76 | Name (_S0W, 3) /* D3 can wake device in S0 */ |
| 77 | Name (_S3W, 3) /* D3 can wake system from S3 */ |
| 78 | Name (_S4W, 3) /* D3 can wake system from S4 */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 79 | |
| 80 | OperationRegion (XPRT, PCI_Config, 0x00, 0x100) |
| 81 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 82 | { |
| 83 | Offset (0x0), |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 84 | DVID, 16, /* VENDORID */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 85 | Offset (0x10), |
| 86 | , 16, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 87 | XMEM, 16, /* MEM_BASE */ |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 88 | Offset (0x50), /* XHCLKGTEN */ |
| 89 | , 2, |
| 90 | STGE, 1, /* SS Link Trunk clock gating enable */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 91 | Offset (0x74), |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 92 | D0D3, 2, /* POWERSTATE */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 93 | , 6, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 94 | PMEE, 1, /* PME_EN */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 95 | , 6, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 96 | PMES, 1, /* PME_STS */ |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 97 | Offset (0xA2), |
| 98 | , 2, |
| 99 | D3HE, 1, /* D3_hot_en */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 100 | } |
| 101 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 102 | OperationRegion (XREG, SystemMemory, |
| 103 | Add (ShiftLeft (XMEM, 16), 0x8000), 0x200) |
| 104 | Field (XREG, DWordAcc, Lock, Preserve) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 105 | { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 106 | Offset (0x1c4), /* USB2PMCTRL */ |
| 107 | , 2, |
| 108 | UPSW, 2, /* U2PSUSPGP */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 111 | Method (_PSC, 0, Serialized) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 112 | { |
| 113 | Return (^D0D3) |
| 114 | } |
| 115 | |
| 116 | Method (_PS0, 0, Serialized) |
| 117 | { |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 118 | If (!LEqual (^DVID, 0xFFFF)) { |
| 119 | If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 120 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 121 | /* Disable d3hot and SS link trunk clock gating */ |
| 122 | Store(Zero, ^D3HE) |
| 123 | Store(Zero, ^STGE) |
Naresh G Solanki | fb79379 | 2017-03-16 15:30:25 +0530 | [diff] [blame] | 124 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 125 | /* If device is in D3, set back to D0 */ |
| 126 | If (LEqual (^D0D3, 3)) { |
| 127 | Store (Zero, Local0) |
| 128 | Store (Local0, ^D0D3) |
| 129 | Store (^D0D3, Local0) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 130 | } |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 131 | |
| 132 | /* Disable USB2 PHY SUS Well Power Gating */ |
| 133 | Store (Zero, ^UPSW) |
| 134 | |
| 135 | /* |
| 136 | * Apply USB2 PHPY Power Gating workaround if needed. |
| 137 | */ |
| 138 | If (^^PMC.UWAB) { |
| 139 | /* Write to MTPMC to have PMC disable power gating */ |
| 140 | Store (1, ^^PMC.MPMC) |
| 141 | |
| 142 | /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ |
| 143 | Store (10, Local0) |
| 144 | While (^^PMC.PMFS) { |
| 145 | If (LNot (Local0)) { |
| 146 | Break |
| 147 | } |
| 148 | Decrement (Local0) |
| 149 | Sleep (10) |
| 150 | } |
| 151 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 152 | } |
| 153 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 154 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 155 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 156 | Method (_PS3, 0, Serialized) |
| 157 | { |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 158 | If (!LEqual (^DVID, 0xFFFF)) { |
| 159 | If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 160 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 161 | /* Clear PME Status */ |
| 162 | Store (1, ^PMES) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 163 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 164 | /* Enable PME */ |
| 165 | Store (1, ^PMEE) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 166 | |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 167 | /* If device is in D3, set back to D0 */ |
| 168 | If (LEqual (^D0D3, 3)) { |
| 169 | Store (Zero, Local0) |
| 170 | Store (Local0, ^D0D3) |
| 171 | Store (^D0D3, Local0) |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 172 | } |
Christian Walter | 343e134 | 2019-06-07 10:36:24 +0200 | [diff] [blame] | 173 | |
| 174 | /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ |
| 175 | Store (3, ^UPSW) |
| 176 | |
| 177 | /* Enable d3hot and SS link trunk clock gating */ |
| 178 | Store(One, ^D3HE) |
| 179 | Store(One, ^STGE) |
| 180 | |
| 181 | /* Now put device in D3 */ |
| 182 | Store (3, Local0) |
| 183 | Store (Local0, ^D0D3) |
| 184 | Store (^D0D3, Local0) |
| 185 | |
| 186 | /* |
| 187 | * Apply USB2 PHPY Power Gating workaround if needed. |
| 188 | * This code assumes XDCI is disabled, if it is enabled |
| 189 | * then this must also check if it is in D3 state too. |
| 190 | */ |
| 191 | If (^^PMC.UWAB) { |
| 192 | /* Write to MTPMC to have PMC enable power gating */ |
| 193 | Store (3, ^^PMC.MPMC) |
| 194 | |
| 195 | /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ |
| 196 | Store (10, Local0) |
| 197 | While (^^PMC.PMFS) { |
| 198 | If (LNot (Local0)) { |
| 199 | Break |
| 200 | } |
| 201 | Decrement (Local0) |
| 202 | Sleep (10) |
| 203 | } |
| 204 | } |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 205 | } |
| 206 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 207 | } |
| 208 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 209 | /* Root Hub for Skylake-LP PCH */ |
| 210 | Device (RHUB) |
| 211 | { |
| 212 | Name (_ADR, Zero) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 213 | |
Matt DeVillier | dc1b781 | 2017-04-22 16:36:10 -0500 | [diff] [blame] | 214 | // GPLD: Generate Port Location Data (PLD) |
| 215 | Method (GPLD, 1, Serialized) |
| 216 | { |
| 217 | |
| 218 | Name (PCKG, Package (0x01) |
| 219 | { |
| 220 | Buffer (0x10) {} |
| 221 | }) |
| 222 | |
| 223 | // REV: Revision 0x02 for ACPI 5.0 |
| 224 | CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) |
| 225 | Store (0x02, REV) |
| 226 | |
| 227 | // VISI: Port visibility to user per port |
| 228 | CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) |
| 229 | Store (Arg0, VISI) |
| 230 | |
| 231 | Return (PCKG) |
| 232 | } |
| 233 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 234 | /* USB2 */ |
| 235 | Device (HS01) { Name (_ADR, 1) } |
| 236 | Device (HS02) { Name (_ADR, 2) } |
| 237 | Device (HS03) { Name (_ADR, 3) } |
| 238 | Device (HS04) { Name (_ADR, 4) } |
| 239 | Device (HS05) { Name (_ADR, 5) } |
| 240 | Device (HS06) { Name (_ADR, 6) } |
| 241 | Device (HS07) { Name (_ADR, 7) } |
| 242 | Device (HS08) { Name (_ADR, 8) } |
| 243 | Device (HS09) { Name (_ADR, 9) } |
| 244 | Device (HS10) { Name (_ADR, 10) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 245 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 246 | /* USBr */ |
| 247 | Device (USR1) { Name (_ADR, 11) } |
| 248 | Device (USR2) { Name (_ADR, 12) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 249 | |
Duncan Laurie | e32da95 | 2015-08-27 17:09:02 -0700 | [diff] [blame] | 250 | /* USB3 */ |
| 251 | Device (SS01) { Name (_ADR, 13) } |
| 252 | Device (SS02) { Name (_ADR, 14) } |
| 253 | Device (SS03) { Name (_ADR, 15) } |
| 254 | Device (SS04) { Name (_ADR, 16) } |
| 255 | Device (SS05) { Name (_ADR, 17) } |
| 256 | Device (SS06) { Name (_ADR, 18) } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 257 | } |
| 258 | } |