Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <console/console.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/romcc_io.h> |
| 25 | #include <device/pci_def.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | #include "i945.h" |
| 27 | #include "pcie_config.c" |
| 28 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 29 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 30 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 31 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 34 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 35 | { |
| 36 | u8 reg8; |
| 37 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 38 | printk(BIOS_INFO, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 39 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 40 | switch (reg8) { |
| 41 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 42 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 43 | break; |
| 44 | case 2: |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 45 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | break; |
| 47 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 48 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | break; |
| 50 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 51 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | break; |
| 53 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 54 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 55 | break; |
| 56 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 57 | printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 58 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 59 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 60 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 62 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 63 | switch (reg8) { |
| 64 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | break; |
| 67 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 68 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 69 | break; |
| 70 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 72 | break; |
| 73 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 75 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 76 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 77 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 79 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 80 | switch (reg8) { |
| 81 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 82 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | break; |
| 84 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 86 | break; |
| 87 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | break; |
| 90 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 91 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 92 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 93 | printk(BIOS_DEBUG, "\n"); |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame^] | 94 | #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 95 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
| 96 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 97 | } |
| 98 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 99 | static void i945_detect_chipset(void) |
| 100 | { |
| 101 | u8 reg8; |
| 102 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 103 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 104 | |
| 105 | reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 106 | switch (reg8) { |
| 107 | case 0: |
| 108 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 109 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 110 | break; |
| 111 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 112 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 113 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 114 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 115 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 117 | break; |
| 118 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 119 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 120 | break; |
| 121 | case 6: |
| 122 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 123 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 124 | break; |
| 125 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 126 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 127 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 128 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 129 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 131 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 132 | switch (reg8) { |
| 133 | case 0: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 135 | break; |
| 136 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 137 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 138 | break; |
| 139 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 140 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 141 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "\n"); |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame^] | 143 | #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 144 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
| 145 | #endif |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 148 | static void i945_setup_bars(void) |
| 149 | { |
| 150 | u8 reg8; |
| 151 | |
| 152 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 153 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 154 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 155 | |
| 156 | /* Setting up Southbridge. In the northbridge code. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 157 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 158 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); |
| 159 | |
| 160 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 161 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 162 | |
| 163 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 164 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 165 | setup_ich7_gpios(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 166 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 167 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 169 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 170 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 171 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 172 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 174 | /* Set up all hardcoded northbridge BARs */ |
| 175 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 176 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 177 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 178 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 179 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 180 | |
| 181 | /* Hardware default is 8MB UMA. If someone wants to make this a |
| 182 | * CMOS or compile time option, send a patch. |
| 183 | * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); |
| 184 | */ |
| 185 | |
| 186 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 187 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 188 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 189 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 190 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 191 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 192 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 193 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 194 | |
Sven Schnelle | d8c68a9 | 2011-06-15 09:26:34 +0200 | [diff] [blame] | 195 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 196 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 197 | |
| 198 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 199 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 200 | if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ |
| 201 | do { |
| 202 | reg8 = *(volatile u8 *)0xfed40000; |
| 203 | } while (!(reg8 & 0x80)); |
| 204 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 205 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | static void i945_setup_egress_port(void) |
| 209 | { |
| 210 | u32 reg32; |
| 211 | u32 timeout; |
| 212 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 214 | |
| 215 | /* Egress Port Virtual Channel 0 Configuration */ |
| 216 | |
| 217 | /* map only TC0 to VC0 */ |
| 218 | reg32 = EPBAR32(EPVC0RCTL); |
| 219 | reg32 &= 0xffffff01; |
| 220 | EPBAR32(EPVC0RCTL) = reg32; |
| 221 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 222 | reg32 = EPBAR32(EPPVCCAP1); |
| 223 | reg32 &= ~(7 << 0); |
| 224 | reg32 |= 1; |
| 225 | EPBAR32(EPPVCCAP1) = reg32; |
| 226 | |
| 227 | /* Egress Port Virtual Channel 1 Configuration */ |
| 228 | reg32 = EPBAR32(0x2c); |
| 229 | reg32 &= 0xffffff00; |
| 230 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 231 | reg32 |= 0x0d; /* 533MHz */ |
| 232 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 233 | reg32 |= 0x10; /* 667MHz */ |
| 234 | EPBAR32(0x2c) = reg32; |
| 235 | |
| 236 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 237 | |
| 238 | reg32 = EPBAR32(EPVC1RCAP); |
| 239 | reg32 &= ~(0x7f << 16); |
| 240 | reg32 |= (0x0a << 16); |
| 241 | EPBAR32(EPVC1RCAP) = reg32; |
| 242 | |
| 243 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 244 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 245 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 246 | } |
| 247 | |
| 248 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 249 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 250 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 251 | } |
| 252 | |
| 253 | /* Is internal graphics enabled? */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 254 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 255 | MCHBAR32(MMARB1) |= (1 << 17); |
| 256 | } |
| 257 | |
| 258 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 259 | reg32 = EPBAR32(EPVC1RCTL); |
| 260 | reg32 &= ~(7 << 24); |
| 261 | reg32 |= (1 << 24); |
| 262 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 263 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 264 | reg32 = EPBAR32(EPVC1RCTL); |
| 265 | reg32 &= 0xffffff01; |
| 266 | reg32 |= (1 << 7); |
| 267 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 268 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 269 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 270 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 271 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 272 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 273 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 274 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 275 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 276 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 277 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 278 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 279 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 280 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 281 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 282 | /* Loop until bit 0 becomes 0 */ |
| 283 | timeout = 0x7fffff; |
| 284 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; |
| 285 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 286 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 287 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 288 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 289 | |
| 290 | /* Now enable VC1 */ |
| 291 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 292 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 293 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 294 | /* Wait for VC1 negotiation pending */ |
| 295 | timeout = 0x7fff; |
| 296 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; |
| 297 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 298 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 299 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 300 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 301 | |
| 302 | } |
| 303 | |
| 304 | static void ich7_setup_dmi_rcrb(void) |
| 305 | { |
| 306 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 307 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 308 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 309 | reg16 = RCBA16(LCTL); |
| 310 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 311 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 312 | RCBA16(LCTL) = reg16; |
| 313 | |
| 314 | RCBA32(V0CTL) = 0x80000001; |
| 315 | RCBA32(V1CAP) = 0x03128010; |
| 316 | RCBA32(ESD) = 0x00000810; |
| 317 | RCBA32(RP1D) = 0x01000003; |
| 318 | RCBA32(RP2D) = 0x02000002; |
| 319 | RCBA32(RP3D) = 0x03000002; |
| 320 | RCBA32(RP4D) = 0x04000002; |
| 321 | RCBA32(HDD) = 0x0f000003; |
| 322 | RCBA32(RP5D) = 0x05000002; |
| 323 | |
| 324 | RCBA32(RPFN) = 0x00543210; |
| 325 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 326 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 327 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 328 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 329 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 330 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 331 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 332 | |
| 333 | reg32 = RCBA32(V1CTL); |
| 334 | reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) ); |
| 335 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 336 | RCBA32(V1CTL) = reg32; |
| 337 | |
| 338 | RCBA32(ESD) |= (2 << 16); |
| 339 | |
| 340 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 341 | |
| 342 | RCBA32(ULBA) = DEFAULT_DMIBAR; |
| 343 | |
| 344 | RCBA32(RP1D) |= (2 << 16); |
| 345 | RCBA32(RP2D) |= (2 << 16); |
| 346 | RCBA32(RP3D) |= (2 << 16); |
| 347 | RCBA32(RP4D) |= (2 << 16); |
| 348 | RCBA32(HDD) |= (2 << 16); |
| 349 | RCBA32(RP5D) |= (2 << 16); |
| 350 | RCBA32(RP6D) |= (2 << 16); |
| 351 | |
| 352 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 353 | } |
| 354 | |
| 355 | static void i945_setup_dmi_rcrb(void) |
| 356 | { |
| 357 | u32 reg32; |
| 358 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 359 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 360 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 361 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 362 | |
| 363 | /* Virtual Channel 0 Configuration */ |
| 364 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 365 | reg32 &= 0xffffff01; |
| 366 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 367 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 368 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 369 | reg32 &= ~(7 << 0); |
| 370 | reg32 |= 1; |
| 371 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 372 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 373 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 374 | reg32 &= ~(7 << 24); |
| 375 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 376 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 377 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 378 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 379 | reg32 &= 0xffffff01; |
| 380 | reg32 |= (1 << 7); |
| 381 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 382 | |
| 383 | /* Now enable VC1 */ |
| 384 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 385 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 386 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 387 | /* Wait for VC1 negotiation pending */ |
| 388 | timeout = 0x7ffff; |
| 389 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; |
| 390 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 391 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 392 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 393 | printk(BIOS_DEBUG, "done..\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 394 | #if 1 |
| 395 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 396 | |
| 397 | reg32 = DMIBAR32(DMILCAP); |
| 398 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 399 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 400 | |
| 401 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 402 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 403 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 404 | DMIBAR32(DMILCAP) = reg32; |
| 405 | |
| 406 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 407 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 408 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 409 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 410 | reg32 &= ~(3 << 20); |
| 411 | reg32 |= (1 << 20); |
| 412 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 413 | DMIBAR32(DMICC) = reg32; |
| 414 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 415 | if (activate_aspm) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 416 | DMIBAR32(DMILCTL) |= (3 << 0); |
| 417 | } |
| 418 | #endif |
| 419 | |
| 420 | /* Last but not least, some additional steps */ |
| 421 | reg32 = MCHBAR32(FSBSNPCTL); |
| 422 | reg32 &= ~(0xff << 2); |
| 423 | reg32 |= (0xaa << 2); |
| 424 | MCHBAR32(FSBSNPCTL) = reg32; |
| 425 | |
| 426 | DMIBAR32(0x2c) = 0x86000040; |
| 427 | |
| 428 | reg32 = DMIBAR32(0x204); |
| 429 | reg32 &= ~0x3ff; |
| 430 | #if 1 |
| 431 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 432 | #else |
| 433 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 434 | #endif |
| 435 | DMIBAR32(0x204) = reg32; |
| 436 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 437 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 438 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 439 | DMIBAR32(0x200) |= (1 << 21); |
| 440 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 441 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 442 | DMIBAR32(0x200) &= ~(1 << 21); |
| 443 | } |
| 444 | |
| 445 | reg32 = DMIBAR32(0x204); |
| 446 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 447 | DMIBAR32(0x204) = reg32; |
| 448 | |
| 449 | reg32 = DMIBAR32(0x204); |
| 450 | reg32 &= ~(0xff << 12); |
| 451 | reg32 |= (0x0d << 12); |
| 452 | DMIBAR32(0x204) = reg32; |
| 453 | |
| 454 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 455 | |
| 456 | reg32 = DMIBAR32(0x200); |
| 457 | reg32 &= ~(0x3 << 26); |
| 458 | reg32 |= (0x02 << 26); |
| 459 | DMIBAR32(0x200) = reg32; |
| 460 | |
| 461 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 462 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 463 | |
| 464 | if (i945_silicon_revision() >= 3) { |
| 465 | reg32 = DMIBAR32(0xec0); |
| 466 | reg32 &= 0x0fffffff; |
| 467 | reg32 |= (2 << 28); |
| 468 | DMIBAR32(0xec0) = reg32; |
| 469 | |
| 470 | reg32 = DMIBAR32(0xed4); |
| 471 | reg32 &= 0x0fffffff; |
| 472 | reg32 |= (2 << 28); |
| 473 | DMIBAR32(0xed4) = reg32; |
| 474 | |
| 475 | reg32 = DMIBAR32(0xee8); |
| 476 | reg32 &= 0x0fffffff; |
| 477 | reg32 |= (2 << 28); |
| 478 | DMIBAR32(0xee8) = reg32; |
| 479 | |
| 480 | reg32 = DMIBAR32(0xefc); |
| 481 | reg32 &= 0x0fffffff; |
| 482 | reg32 |= (2 << 28); |
| 483 | DMIBAR32(0xefc) = reg32; |
| 484 | } |
| 485 | |
| 486 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 487 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 488 | timeout = 0x7fffff; |
| 489 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; |
| 490 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 491 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 492 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 493 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 494 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 495 | /* Clear Error Status Bits! */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 496 | DMIBAR32(0x1c4) = 0xffffffff; |
| 497 | DMIBAR32(0x1d0) = 0xffffffff; |
| 498 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 499 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 500 | /* Program Read-Only Write-Once Registers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 501 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 502 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 503 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 504 | DMIBAR32(0x328) = DMIBAR32(0x328); |
| 505 | DMIBAR32(0x338) = DMIBAR32(0x334); |
| 506 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 507 | |
| 508 | if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 509 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 510 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 511 | reg32 = DMIBAR32(0x224); |
| 512 | reg32 &= ~(7 << 0); |
| 513 | reg32 |= (3 << 0); |
| 514 | DMIBAR32(0x224) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 515 | outb(0x06, 0xcf9); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 516 | for (;;) asm("hlt"); /* wait for reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 517 | } |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | static void i945_setup_pci_express_x16(void) |
| 522 | { |
| 523 | u32 timeout; |
| 524 | u32 reg32; |
| 525 | u16 reg16; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 526 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 527 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 528 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 529 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 530 | |
| 531 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 532 | reg16 |= DEVEN_D1F0; |
| 533 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 534 | |
| 535 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208); |
| 536 | reg32 &= ~(1 << 8); |
| 537 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); |
| 538 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 539 | /* We have no success with querying the usual PCIe registers |
| 540 | * for link setup success on the i945. Hence we assign a temporary |
| 541 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 542 | */ |
| 543 | |
| 544 | /* First we reset the secondary bus */ |
| 545 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 546 | reg16 |= (1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 547 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 548 | /* Read back and clear reset bit. */ |
| 549 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 550 | reg16 &= ~(1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 551 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 552 | |
| 553 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 554 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 555 | if (!(reg16 & 0x48)) { |
| 556 | goto disable_pciexpress_x16_link; |
| 557 | } |
| 558 | reg16 |= (1 << 4) | (1 << 0); |
| 559 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); |
| 560 | |
| 561 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00); |
| 562 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00); |
| 563 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); |
| 564 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); |
| 565 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 566 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 567 | reg32 &= ~(1 << 8); |
| 568 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 569 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 570 | MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) ); |
| 571 | |
| 572 | /* Initialze PEG_CAP */ |
| 573 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); |
| 574 | reg16 |= (1 << 8); |
| 575 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); |
| 576 | |
| 577 | /* Setup SLOTCAP */ |
| 578 | /* TODO: These values are mainboard dependent and should |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 579 | * be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 580 | */ |
| 581 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
| 582 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 583 | reg32 &= 0x0007ffff; |
| 584 | |
| 585 | reg32 &= 0xfffe007f; |
| 586 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 587 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); |
| 588 | |
| 589 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 590 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 591 | timeout = 0x7ffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 592 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 593 | |
| 594 | reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); |
| 595 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 596 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 597 | reg32 & 0xffff, reg32 >> 16); |
| 598 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 599 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 600 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 601 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 602 | |
| 603 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 604 | reg32 &= ~(0xf << 1); |
| 605 | reg32 |=1; |
| 606 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); |
| 607 | |
| 608 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
| 609 | |
| 610 | reg16 |= (1 << 6); |
| 611 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 612 | reg16 &= ~(1 << 6); |
| 613 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 614 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 615 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 616 | timeout = 0x7ffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 617 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 618 | |
| 619 | reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); |
| 620 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 621 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 622 | reg32 & 0xffff, reg32 >> 16); |
| 623 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 624 | printk(BIOS_DEBUG, " timeout!\n"); |
| 625 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 626 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 627 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); |
| 631 | reg16 >>= 4; |
| 632 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 633 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 634 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 635 | |
| 636 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 637 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 638 | if (reg16 == 1) { |
| 639 | reg32 |= 0x32b; |
| 640 | // TODO |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 641 | /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 642 | } else if (reg16 == 16) { |
| 643 | reg32 |= 0x0f4; |
| 644 | // TODO |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 645 | /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 648 | reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 649 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 650 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 651 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 652 | reg16 = (1 << 1); |
| 653 | pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); |
| 654 | |
| 655 | /* DEVEN */ |
| 656 | reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54); |
| 657 | reg32 &= ~((1 << 3) | (1 << 4)); |
| 658 | pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32); |
| 659 | |
| 660 | /* Set VGA enable bit in PCIe bridge */ |
| 661 | reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e); |
| 662 | reg16 |= (1 << 3); |
| 663 | pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16); |
| 664 | } |
| 665 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 666 | /* Enable GPEs */ |
| 667 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec); |
| 668 | reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ |
| 669 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 670 | |
| 671 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
| 672 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114); |
| 673 | reg32 &= 0xffffff01; |
| 674 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 675 | |
| 676 | /* Extended VC count */ |
| 677 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104); |
| 678 | reg32 &= ~(7 << 0); |
| 679 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); |
| 680 | |
| 681 | /* Active State Power Management ASPM */ |
| 682 | |
| 683 | /* TODO */ |
| 684 | |
| 685 | /* Clear error bits */ |
| 686 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); |
| 687 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); |
| 688 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); |
| 689 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); |
| 690 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); |
| 691 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); |
| 692 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); |
| 693 | |
| 694 | /* Program R/WO registers */ |
| 695 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308); |
| 696 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); |
| 697 | |
| 698 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314); |
| 699 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); |
| 700 | |
| 701 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324); |
| 702 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); |
| 703 | |
| 704 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328); |
| 705 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); |
| 706 | |
| 707 | reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); |
| 708 | pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); |
| 709 | |
| 710 | /* Additional PCIe graphics setup */ |
| 711 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 712 | reg32 |= (3 << 26); |
| 713 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 714 | |
| 715 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 716 | reg32 |= (3 << 24); |
| 717 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 718 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 719 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 720 | reg32 |= (1 << 5); |
| 721 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 722 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 723 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200); |
| 724 | reg32 &= ~(3 << 26); |
| 725 | reg32 |= (2 << 26); |
| 726 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); |
| 727 | |
| 728 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
| 729 | if (i945_silicon_revision() >= 2) { |
| 730 | reg32 |= (1 << 12); |
| 731 | } else { |
| 732 | reg32 &= ~(1 << 12); |
| 733 | } |
| 734 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 735 | |
| 736 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); |
| 737 | reg32 &= ~(1 << 31); |
| 738 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); |
| 739 | |
| 740 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); |
| 741 | reg32 |= (1 << 31); |
| 742 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); |
| 743 | |
| 744 | if (i945_silicon_revision() >= 3) { |
| 745 | static const u32 reglist[] = { |
| 746 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, |
| 747 | 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, |
| 748 | 0xfb0, 0xfc4, 0xfd8, 0xfec |
| 749 | }; |
| 750 | |
| 751 | int i; |
| 752 | for (i=0; i<ARRAY_SIZE(reglist); i++) { |
| 753 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); |
| 754 | reg32 &= 0x0fffffff; |
| 755 | reg32 |= (2 << 28); |
| 756 | pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); |
| 757 | } |
| 758 | } |
| 759 | |
| 760 | if (i945_silicon_revision() <= 2 ) { |
| 761 | /* Set voltage specific parameters */ |
| 762 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 763 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
| 764 | if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 765 | reg32 |= (7 << 4); |
| 766 | } |
| 767 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 768 | } |
| 769 | |
| 770 | return; |
| 771 | |
| 772 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 773 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 774 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 775 | |
| 776 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 777 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 778 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 779 | reg16 |= (1 << 6); |
| 780 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 781 | |
| 782 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 783 | reg32 |= (1 << 8); |
| 784 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 785 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 786 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 787 | reg16 &= ~(1 << 6); |
| 788 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 789 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 790 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 791 | timeout = 0x7fffff; |
| 792 | for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 793 | (reg32 & 0x000f0000) && --timeout;) ; |
| 794 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 795 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 796 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 797 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 798 | |
| 799 | /* Finally: Disable the PCI config header */ |
| 800 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 801 | reg16 &= ~DEVEN_D1F0; |
| 802 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 803 | } |
| 804 | |
| 805 | static void i945_setup_root_complex_topology(void) |
| 806 | { |
| 807 | u32 reg32; |
| 808 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 809 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 810 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 811 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 812 | reg32 = EPBAR32(EPESD); |
| 813 | reg32 &= 0xff00ffff; |
| 814 | reg32 |= (1 << 16); |
| 815 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 816 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 817 | EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 818 | |
| 819 | EPBAR32(EPLE1A) = DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 820 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 821 | EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 822 | |
| 823 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 824 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 825 | reg32 = DMIBAR32(DMILE1D); |
| 826 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 827 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 828 | reg32 &= 0xff00ffff; |
| 829 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 830 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 831 | reg32 |= (1 << 0); |
| 832 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 833 | |
| 834 | DMIBAR32(DMILE1A) = DEFAULT_RCBA; |
| 835 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 836 | DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 837 | |
| 838 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 839 | |
| 840 | /* PCI Express x16 Port Root Topology */ |
| 841 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 842 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 843 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); |
| 844 | reg32 |= (1 << 0); |
| 845 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | static void ich7_setup_root_complex_topology(void) |
| 850 | { |
| 851 | RCBA32(0x104) = 0x00000802; |
| 852 | RCBA32(0x110) = 0x00000001; |
| 853 | RCBA32(0x114) = 0x00000000; |
| 854 | RCBA32(0x118) = 0x00000000; |
| 855 | } |
| 856 | |
| 857 | static void ich7_setup_pci_express(void) |
| 858 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 859 | RCBA32(CG) |= (1 << 0); |
| 860 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 861 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 862 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 863 | #if 0 |
| 864 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 865 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 866 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 867 | |
| 868 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 869 | } |
| 870 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 871 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 872 | { |
| 873 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 874 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 875 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 876 | i945_detect_chipset(); |
| 877 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 878 | case 0x27a08086: /* 945GME/GSE */ |
| 879 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 880 | i945m_detect_chipset(); |
| 881 | break; |
| 882 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 883 | |
| 884 | /* Setup all BARs required for early PCIe and raminit */ |
| 885 | i945_setup_bars(); |
| 886 | |
| 887 | /* Change port80 to LPC */ |
| 888 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 889 | |
| 890 | /* Just do it that way */ |
| 891 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 892 | } |
| 893 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 894 | void i945_late_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 895 | { |
| 896 | i945_setup_egress_port(); |
| 897 | |
| 898 | ich7_setup_root_complex_topology(); |
| 899 | |
| 900 | ich7_setup_pci_express(); |
| 901 | |
| 902 | ich7_setup_dmi_rcrb(); |
| 903 | |
| 904 | i945_setup_dmi_rcrb(); |
| 905 | |
| 906 | i945_setup_pci_express_x16(); |
| 907 | |
| 908 | i945_setup_root_complex_topology(); |
| 909 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 910 | |