Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <console/console.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/romcc_io.h> |
| 25 | #include <device/pci_def.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | #include "i945.h" |
| 27 | #include "pcie_config.c" |
| 28 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 29 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 30 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 31 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 34 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 35 | { |
| 36 | u8 reg8; |
| 37 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 38 | printk(BIOS_INFO, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 39 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 40 | switch (reg8) { |
| 41 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 42 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 43 | break; |
| 44 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 45 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | break; |
| 47 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 48 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | break; |
| 50 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 51 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | break; |
| 53 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 54 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 55 | break; |
| 56 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 57 | printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 58 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 59 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 60 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 62 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 63 | switch (reg8) { |
| 64 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | break; |
| 67 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 68 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 69 | break; |
| 70 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 72 | break; |
| 73 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 75 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 76 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 77 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 79 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 80 | switch (reg8) { |
| 81 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 82 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | break; |
| 84 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 86 | break; |
| 87 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | break; |
| 90 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 91 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 92 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 93 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 96 | static void i945_detect_chipset(void) |
| 97 | { |
| 98 | u8 reg8; |
| 99 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 100 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 101 | |
| 102 | reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 103 | switch (reg8) { |
| 104 | case 0: |
| 105 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 106 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 107 | break; |
| 108 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 109 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 110 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 111 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 112 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 113 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 114 | break; |
| 115 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 117 | break; |
| 118 | case 6: |
| 119 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 120 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 121 | break; |
| 122 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 123 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 124 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 125 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 126 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 127 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 128 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 129 | switch (reg8) { |
| 130 | case 0: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 132 | break; |
| 133 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 135 | break; |
| 136 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 137 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 138 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 140 | } |
| 141 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 142 | static void i945_setup_bars(void) |
| 143 | { |
| 144 | u8 reg8; |
| 145 | |
| 146 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 147 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 148 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 149 | |
| 150 | /* Setting up Southbridge. In the northbridge code. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 151 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 152 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); |
| 153 | |
| 154 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 155 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 156 | |
| 157 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 158 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 159 | setup_ich7_gpios(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 160 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 161 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 162 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 163 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 164 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 165 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 166 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 167 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 168 | /* Set up all hardcoded northbridge BARs */ |
| 169 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 170 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 171 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 172 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 173 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 174 | |
| 175 | /* Hardware default is 8MB UMA. If someone wants to make this a |
| 176 | * CMOS or compile time option, send a patch. |
| 177 | * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); |
| 178 | */ |
| 179 | |
| 180 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 181 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 182 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 183 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 184 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 185 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 186 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 187 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 188 | |
Sven Schnelle | d8c68a9 | 2011-06-15 09:26:34 +0200 | [diff] [blame^] | 189 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 190 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 191 | |
| 192 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 193 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 194 | if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ |
| 195 | do { |
| 196 | reg8 = *(volatile u8 *)0xfed40000; |
| 197 | } while (!(reg8 & 0x80)); |
| 198 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 199 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static void i945_setup_egress_port(void) |
| 203 | { |
| 204 | u32 reg32; |
| 205 | u32 timeout; |
| 206 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 207 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 208 | |
| 209 | /* Egress Port Virtual Channel 0 Configuration */ |
| 210 | |
| 211 | /* map only TC0 to VC0 */ |
| 212 | reg32 = EPBAR32(EPVC0RCTL); |
| 213 | reg32 &= 0xffffff01; |
| 214 | EPBAR32(EPVC0RCTL) = reg32; |
| 215 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 216 | reg32 = EPBAR32(EPPVCCAP1); |
| 217 | reg32 &= ~(7 << 0); |
| 218 | reg32 |= 1; |
| 219 | EPBAR32(EPPVCCAP1) = reg32; |
| 220 | |
| 221 | /* Egress Port Virtual Channel 1 Configuration */ |
| 222 | reg32 = EPBAR32(0x2c); |
| 223 | reg32 &= 0xffffff00; |
| 224 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 225 | reg32 |= 0x0d; /* 533MHz */ |
| 226 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 227 | reg32 |= 0x10; /* 667MHz */ |
| 228 | EPBAR32(0x2c) = reg32; |
| 229 | |
| 230 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 231 | |
| 232 | reg32 = EPBAR32(EPVC1RCAP); |
| 233 | reg32 &= ~(0x7f << 16); |
| 234 | reg32 |= (0x0a << 16); |
| 235 | EPBAR32(EPVC1RCAP) = reg32; |
| 236 | |
| 237 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 238 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 239 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 240 | } |
| 241 | |
| 242 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 243 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 244 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 245 | } |
| 246 | |
| 247 | /* Is internal graphics enabled? */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 248 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 249 | MCHBAR32(MMARB1) |= (1 << 17); |
| 250 | } |
| 251 | |
| 252 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 253 | reg32 = EPBAR32(EPVC1RCTL); |
| 254 | reg32 &= ~(7 << 24); |
| 255 | reg32 |= (1 << 24); |
| 256 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 257 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 258 | reg32 = EPBAR32(EPVC1RCTL); |
| 259 | reg32 &= 0xffffff01; |
| 260 | reg32 |= (1 << 7); |
| 261 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 262 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 263 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 264 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 265 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 266 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 267 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 268 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 269 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 270 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 271 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 272 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 273 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 274 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 275 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 276 | /* Loop until bit 0 becomes 0 */ |
| 277 | timeout = 0x7fffff; |
| 278 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; |
| 279 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 280 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 281 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 282 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 283 | |
| 284 | /* Now enable VC1 */ |
| 285 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 286 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 287 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 288 | /* Wait for VC1 negotiation pending */ |
| 289 | timeout = 0x7fff; |
| 290 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; |
| 291 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 292 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 293 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 294 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 295 | |
| 296 | } |
| 297 | |
| 298 | static void ich7_setup_dmi_rcrb(void) |
| 299 | { |
| 300 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 301 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 302 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 303 | reg16 = RCBA16(LCTL); |
| 304 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 305 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 306 | RCBA16(LCTL) = reg16; |
| 307 | |
| 308 | RCBA32(V0CTL) = 0x80000001; |
| 309 | RCBA32(V1CAP) = 0x03128010; |
| 310 | RCBA32(ESD) = 0x00000810; |
| 311 | RCBA32(RP1D) = 0x01000003; |
| 312 | RCBA32(RP2D) = 0x02000002; |
| 313 | RCBA32(RP3D) = 0x03000002; |
| 314 | RCBA32(RP4D) = 0x04000002; |
| 315 | RCBA32(HDD) = 0x0f000003; |
| 316 | RCBA32(RP5D) = 0x05000002; |
| 317 | |
| 318 | RCBA32(RPFN) = 0x00543210; |
| 319 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 320 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 321 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 322 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 323 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 324 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 325 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 326 | |
| 327 | reg32 = RCBA32(V1CTL); |
| 328 | reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) ); |
| 329 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 330 | RCBA32(V1CTL) = reg32; |
| 331 | |
| 332 | RCBA32(ESD) |= (2 << 16); |
| 333 | |
| 334 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 335 | |
| 336 | RCBA32(ULBA) = DEFAULT_DMIBAR; |
| 337 | |
| 338 | RCBA32(RP1D) |= (2 << 16); |
| 339 | RCBA32(RP2D) |= (2 << 16); |
| 340 | RCBA32(RP3D) |= (2 << 16); |
| 341 | RCBA32(RP4D) |= (2 << 16); |
| 342 | RCBA32(HDD) |= (2 << 16); |
| 343 | RCBA32(RP5D) |= (2 << 16); |
| 344 | RCBA32(RP6D) |= (2 << 16); |
| 345 | |
| 346 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | static void i945_setup_dmi_rcrb(void) |
| 350 | { |
| 351 | u32 reg32; |
| 352 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 353 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 354 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 355 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 356 | |
| 357 | /* Virtual Channel 0 Configuration */ |
| 358 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 359 | reg32 &= 0xffffff01; |
| 360 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 361 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 362 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 363 | reg32 &= ~(7 << 0); |
| 364 | reg32 |= 1; |
| 365 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 366 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 367 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 368 | reg32 &= ~(7 << 24); |
| 369 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 370 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 371 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 372 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 373 | reg32 &= 0xffffff01; |
| 374 | reg32 |= (1 << 7); |
| 375 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 376 | |
| 377 | /* Now enable VC1 */ |
| 378 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 379 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 380 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 381 | /* Wait for VC1 negotiation pending */ |
| 382 | timeout = 0x7ffff; |
| 383 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; |
| 384 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 385 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 386 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 387 | printk(BIOS_DEBUG, "done..\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 388 | #if 1 |
| 389 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 390 | |
| 391 | reg32 = DMIBAR32(DMILCAP); |
| 392 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 393 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 394 | |
| 395 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 396 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 397 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 398 | DMIBAR32(DMILCAP) = reg32; |
| 399 | |
| 400 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 401 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 402 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 403 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 404 | reg32 &= ~(3 << 20); |
| 405 | reg32 |= (1 << 20); |
| 406 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 407 | DMIBAR32(DMICC) = reg32; |
| 408 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 409 | if (activate_aspm) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 410 | DMIBAR32(DMILCTL) |= (3 << 0); |
| 411 | } |
| 412 | #endif |
| 413 | |
| 414 | /* Last but not least, some additional steps */ |
| 415 | reg32 = MCHBAR32(FSBSNPCTL); |
| 416 | reg32 &= ~(0xff << 2); |
| 417 | reg32 |= (0xaa << 2); |
| 418 | MCHBAR32(FSBSNPCTL) = reg32; |
| 419 | |
| 420 | DMIBAR32(0x2c) = 0x86000040; |
| 421 | |
| 422 | reg32 = DMIBAR32(0x204); |
| 423 | reg32 &= ~0x3ff; |
| 424 | #if 1 |
| 425 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 426 | #else |
| 427 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 428 | #endif |
| 429 | DMIBAR32(0x204) = reg32; |
| 430 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 431 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 432 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 433 | DMIBAR32(0x200) |= (1 << 21); |
| 434 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 435 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 436 | DMIBAR32(0x200) &= ~(1 << 21); |
| 437 | } |
| 438 | |
| 439 | reg32 = DMIBAR32(0x204); |
| 440 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 441 | DMIBAR32(0x204) = reg32; |
| 442 | |
| 443 | reg32 = DMIBAR32(0x204); |
| 444 | reg32 &= ~(0xff << 12); |
| 445 | reg32 |= (0x0d << 12); |
| 446 | DMIBAR32(0x204) = reg32; |
| 447 | |
| 448 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 449 | |
| 450 | reg32 = DMIBAR32(0x200); |
| 451 | reg32 &= ~(0x3 << 26); |
| 452 | reg32 |= (0x02 << 26); |
| 453 | DMIBAR32(0x200) = reg32; |
| 454 | |
| 455 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 456 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 457 | |
| 458 | if (i945_silicon_revision() >= 3) { |
| 459 | reg32 = DMIBAR32(0xec0); |
| 460 | reg32 &= 0x0fffffff; |
| 461 | reg32 |= (2 << 28); |
| 462 | DMIBAR32(0xec0) = reg32; |
| 463 | |
| 464 | reg32 = DMIBAR32(0xed4); |
| 465 | reg32 &= 0x0fffffff; |
| 466 | reg32 |= (2 << 28); |
| 467 | DMIBAR32(0xed4) = reg32; |
| 468 | |
| 469 | reg32 = DMIBAR32(0xee8); |
| 470 | reg32 &= 0x0fffffff; |
| 471 | reg32 |= (2 << 28); |
| 472 | DMIBAR32(0xee8) = reg32; |
| 473 | |
| 474 | reg32 = DMIBAR32(0xefc); |
| 475 | reg32 &= 0x0fffffff; |
| 476 | reg32 |= (2 << 28); |
| 477 | DMIBAR32(0xefc) = reg32; |
| 478 | } |
| 479 | |
| 480 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 481 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 482 | timeout = 0x7fffff; |
| 483 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; |
| 484 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 485 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 486 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 487 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 488 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 489 | /* Clear Error Status Bits! */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 490 | DMIBAR32(0x1c4) = 0xffffffff; |
| 491 | DMIBAR32(0x1d0) = 0xffffffff; |
| 492 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 493 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 494 | /* Program Read-Only Write-Once Registers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 495 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 496 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 497 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 498 | DMIBAR32(0x328) = DMIBAR32(0x328); |
| 499 | DMIBAR32(0x338) = DMIBAR32(0x334); |
| 500 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 501 | |
| 502 | if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 503 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 504 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 505 | reg32 = DMIBAR32(0x224); |
| 506 | reg32 &= ~(7 << 0); |
| 507 | reg32 |= (3 << 0); |
| 508 | DMIBAR32(0x224) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 509 | outb(0x06, 0xcf9); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 510 | for (;;) asm("hlt"); /* wait for reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | static void i945_setup_pci_express_x16(void) |
| 516 | { |
| 517 | u32 timeout; |
| 518 | u32 reg32; |
| 519 | u16 reg16; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 520 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 521 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 522 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 523 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 524 | |
| 525 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 526 | reg16 |= DEVEN_D1F0; |
| 527 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 528 | |
| 529 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208); |
| 530 | reg32 &= ~(1 << 8); |
| 531 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); |
| 532 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 533 | /* We have no success with querying the usual PCIe registers |
| 534 | * for link setup success on the i945. Hence we assign a temporary |
| 535 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 536 | */ |
| 537 | |
| 538 | /* First we reset the secondary bus */ |
| 539 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 540 | reg16 |= (1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 541 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 542 | /* Read back and clear reset bit. */ |
| 543 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 544 | reg16 &= ~(1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 545 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 546 | |
| 547 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 548 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 549 | if (!(reg16 & 0x48)) { |
| 550 | goto disable_pciexpress_x16_link; |
| 551 | } |
| 552 | reg16 |= (1 << 4) | (1 << 0); |
| 553 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); |
| 554 | |
| 555 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00); |
| 556 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00); |
| 557 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); |
| 558 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); |
| 559 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 560 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 561 | reg32 &= ~(1 << 8); |
| 562 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 563 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 564 | MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) ); |
| 565 | |
| 566 | /* Initialze PEG_CAP */ |
| 567 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); |
| 568 | reg16 |= (1 << 8); |
| 569 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); |
| 570 | |
| 571 | /* Setup SLOTCAP */ |
| 572 | /* TODO: These values are mainboard dependent and should |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 573 | * be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 574 | */ |
| 575 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
| 576 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 577 | reg32 &= 0x0007ffff; |
| 578 | |
| 579 | reg32 &= 0xfffe007f; |
| 580 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 581 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); |
| 582 | |
| 583 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 584 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 585 | timeout = 0x7ffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 586 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 587 | |
| 588 | reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); |
| 589 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 590 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 591 | reg32 & 0xffff, reg32 >> 16); |
| 592 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 593 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 594 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 595 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 596 | |
| 597 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 598 | reg32 &= ~(0xf << 1); |
| 599 | reg32 |=1; |
| 600 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); |
| 601 | |
| 602 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
| 603 | |
| 604 | reg16 |= (1 << 6); |
| 605 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 606 | reg16 &= ~(1 << 6); |
| 607 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 608 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 609 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 610 | timeout = 0x7ffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 611 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 612 | |
| 613 | reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); |
| 614 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 615 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 616 | reg32 & 0xffff, reg32 >> 16); |
| 617 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 618 | printk(BIOS_DEBUG, " timeout!\n"); |
| 619 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 620 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 621 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 622 | } |
| 623 | |
| 624 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); |
| 625 | reg16 >>= 4; |
| 626 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 627 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 628 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 629 | |
| 630 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 631 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 632 | if (reg16 == 1) { |
| 633 | reg32 |= 0x32b; |
| 634 | // TODO |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 635 | /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 636 | } else if (reg16 == 16) { |
| 637 | reg32 |= 0x0f4; |
| 638 | // TODO |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 639 | /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 640 | } |
| 641 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 642 | reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 643 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 644 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 645 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 646 | reg16 = (1 << 1); |
| 647 | pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); |
| 648 | |
| 649 | /* DEVEN */ |
| 650 | reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54); |
| 651 | reg32 &= ~((1 << 3) | (1 << 4)); |
| 652 | pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32); |
| 653 | |
| 654 | /* Set VGA enable bit in PCIe bridge */ |
| 655 | reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e); |
| 656 | reg16 |= (1 << 3); |
| 657 | pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16); |
| 658 | } |
| 659 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 660 | /* Enable GPEs */ |
| 661 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec); |
| 662 | reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ |
| 663 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 664 | |
| 665 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
| 666 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114); |
| 667 | reg32 &= 0xffffff01; |
| 668 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 669 | |
| 670 | /* Extended VC count */ |
| 671 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104); |
| 672 | reg32 &= ~(7 << 0); |
| 673 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); |
| 674 | |
| 675 | /* Active State Power Management ASPM */ |
| 676 | |
| 677 | /* TODO */ |
| 678 | |
| 679 | /* Clear error bits */ |
| 680 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); |
| 681 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); |
| 682 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); |
| 683 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); |
| 684 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); |
| 685 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); |
| 686 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); |
| 687 | |
| 688 | /* Program R/WO registers */ |
| 689 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308); |
| 690 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); |
| 691 | |
| 692 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314); |
| 693 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); |
| 694 | |
| 695 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324); |
| 696 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); |
| 697 | |
| 698 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328); |
| 699 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); |
| 700 | |
| 701 | reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); |
| 702 | pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); |
| 703 | |
| 704 | /* Additional PCIe graphics setup */ |
| 705 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 706 | reg32 |= (3 << 26); |
| 707 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 708 | |
| 709 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 710 | reg32 |= (3 << 24); |
| 711 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 712 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 713 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 714 | reg32 |= (1 << 5); |
| 715 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 716 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 717 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200); |
| 718 | reg32 &= ~(3 << 26); |
| 719 | reg32 |= (2 << 26); |
| 720 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); |
| 721 | |
| 722 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
| 723 | if (i945_silicon_revision() >= 2) { |
| 724 | reg32 |= (1 << 12); |
| 725 | } else { |
| 726 | reg32 &= ~(1 << 12); |
| 727 | } |
| 728 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 729 | |
| 730 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); |
| 731 | reg32 &= ~(1 << 31); |
| 732 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); |
| 733 | |
| 734 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); |
| 735 | reg32 |= (1 << 31); |
| 736 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); |
| 737 | |
| 738 | if (i945_silicon_revision() >= 3) { |
| 739 | static const u32 reglist[] = { |
| 740 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, |
| 741 | 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, |
| 742 | 0xfb0, 0xfc4, 0xfd8, 0xfec |
| 743 | }; |
| 744 | |
| 745 | int i; |
| 746 | for (i=0; i<ARRAY_SIZE(reglist); i++) { |
| 747 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); |
| 748 | reg32 &= 0x0fffffff; |
| 749 | reg32 |= (2 << 28); |
| 750 | pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); |
| 751 | } |
| 752 | } |
| 753 | |
| 754 | if (i945_silicon_revision() <= 2 ) { |
| 755 | /* Set voltage specific parameters */ |
| 756 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 757 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
| 758 | if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 759 | reg32 |= (7 << 4); |
| 760 | } |
| 761 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 762 | } |
| 763 | |
| 764 | return; |
| 765 | |
| 766 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 767 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 768 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 769 | |
| 770 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 771 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 772 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 773 | reg16 |= (1 << 6); |
| 774 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 775 | |
| 776 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 777 | reg32 |= (1 << 8); |
| 778 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 779 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 780 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 781 | reg16 &= ~(1 << 6); |
| 782 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 783 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 784 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 785 | timeout = 0x7fffff; |
| 786 | for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 787 | (reg32 & 0x000f0000) && --timeout;) ; |
| 788 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 789 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 790 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 791 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 792 | |
| 793 | /* Finally: Disable the PCI config header */ |
| 794 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 795 | reg16 &= ~DEVEN_D1F0; |
| 796 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 797 | } |
| 798 | |
| 799 | static void i945_setup_root_complex_topology(void) |
| 800 | { |
| 801 | u32 reg32; |
| 802 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 803 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 804 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 805 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 806 | reg32 = EPBAR32(EPESD); |
| 807 | reg32 &= 0xff00ffff; |
| 808 | reg32 |= (1 << 16); |
| 809 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 810 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 811 | EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 812 | |
| 813 | EPBAR32(EPLE1A) = DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 814 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 815 | EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 816 | |
| 817 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 818 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 819 | reg32 = DMIBAR32(DMILE1D); |
| 820 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 821 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 822 | reg32 &= 0xff00ffff; |
| 823 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 824 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 825 | reg32 |= (1 << 0); |
| 826 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 827 | |
| 828 | DMIBAR32(DMILE1A) = DEFAULT_RCBA; |
| 829 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 830 | DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 831 | |
| 832 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 833 | |
| 834 | /* PCI Express x16 Port Root Topology */ |
| 835 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 836 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 837 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); |
| 838 | reg32 |= (1 << 0); |
| 839 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | static void ich7_setup_root_complex_topology(void) |
| 844 | { |
| 845 | RCBA32(0x104) = 0x00000802; |
| 846 | RCBA32(0x110) = 0x00000001; |
| 847 | RCBA32(0x114) = 0x00000000; |
| 848 | RCBA32(0x118) = 0x00000000; |
| 849 | } |
| 850 | |
| 851 | static void ich7_setup_pci_express(void) |
| 852 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 853 | RCBA32(CG) |= (1 << 0); |
| 854 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 855 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 856 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 857 | #if 0 |
| 858 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 859 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 860 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 861 | |
| 862 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 863 | } |
| 864 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 865 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 866 | { |
| 867 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 868 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 869 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 870 | i945_detect_chipset(); |
| 871 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 872 | case 0x27a08086: /* 945GME/GSE */ |
| 873 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 874 | i945m_detect_chipset(); |
| 875 | break; |
| 876 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 877 | |
| 878 | /* Setup all BARs required for early PCIe and raminit */ |
| 879 | i945_setup_bars(); |
| 880 | |
| 881 | /* Change port80 to LPC */ |
| 882 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 883 | |
| 884 | /* Just do it that way */ |
| 885 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 886 | } |
| 887 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 888 | void i945_late_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 889 | { |
| 890 | i945_setup_egress_port(); |
| 891 | |
| 892 | ich7_setup_root_complex_topology(); |
| 893 | |
| 894 | ich7_setup_pci_express(); |
| 895 | |
| 896 | ich7_setup_dmi_rcrb(); |
| 897 | |
| 898 | i945_setup_dmi_rcrb(); |
| 899 | |
| 900 | i945_setup_pci_express_x16(); |
| 901 | |
| 902 | i945_setup_root_complex_topology(); |
| 903 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 904 | |