Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __NORTHBRIDGE_INTEL_X4X_H__ |
| 19 | #define __NORTHBRIDGE_INTEL_X4X_H__ |
| 20 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | /* |
| 22 | * D0:F0 |
| 23 | */ |
| 24 | #define D0F0_EPBAR_LO 0x40 |
| 25 | #define D0F0_EPBAR_HI 0x44 |
| 26 | #define D0F0_MCHBAR_LO 0x48 |
| 27 | #define D0F0_MCHBAR_HI 0x4c |
| 28 | #define D0F0_GGC 0x52 |
| 29 | #define D0F0_DEVEN 0x54 |
Damien Zammit | fe9876a | 2016-01-22 19:11:05 +1100 | [diff] [blame] | 30 | #define D0EN (1 << 0) |
| 31 | #define D1EN (1 << 1) |
| 32 | #define IGD0EN (1 << 3) |
| 33 | #define IGD1EN (1 << 4) |
| 34 | #define D3F0EN (1 << 6) |
| 35 | #define D3F1EN (1 << 7) |
| 36 | #define D3F2EN (1 << 8) |
| 37 | #define D3F3EN (1 << 9) |
| 38 | #define PEG1EN (1 << 13) |
Damien Zammit | a99c64e | 2016-09-05 02:36:02 +1000 | [diff] [blame] | 39 | #define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 40 | #define D0F0_PCIEXBAR_LO 0x60 |
| 41 | #define D0F0_PCIEXBAR_HI 0x64 |
| 42 | #define D0F0_DMIBAR_LO 0x68 |
| 43 | #define D0F0_DMIBAR_HI 0x6c |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 44 | #define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ |
| 45 | #define D0F0_REMAPBASE 0x98 |
| 46 | #define D0F0_REMAPLIMIT 0x9a |
| 47 | #define D0F0_SMRAM 0x9d |
| 48 | #define D0F0_ESMRAMC 0x9e |
| 49 | #define D0F0_TOM 0xa0 |
| 50 | #define D0F0_TOUUD 0xa2 |
| 51 | #define D0F0_TOLUD 0xb0 |
| 52 | #define D0F0_GBSM 0xa4 |
| 53 | #define D0F0_BGSM 0xa8 |
| 54 | #define D0F0_TSEG 0xac |
| 55 | #define D0F0_SKPD 0xdc /* Scratchpad Data */ |
| 56 | #define D0F0_CAPID0 0xe0 |
| 57 | |
| 58 | /* |
| 59 | * D1:F0 PEG |
| 60 | */ |
| 61 | #define PEG_CAP 0xa2 |
| 62 | #define SLOTCAP 0xb4 |
| 63 | #define PEGLC 0xec |
| 64 | #define D1F0_VCCAP 0x104 |
| 65 | #define D1F0_VC0RCTL 0x114 |
| 66 | |
| 67 | /* |
| 68 | * Graphics frequencies |
| 69 | */ |
| 70 | #define GCFGC_PCIDEV PCI_DEV(0, 2, 0) |
| 71 | #define GCFGC_OFFSET 0xf0 |
| 72 | #define GCFGC_CR_SHIFT 0 |
| 73 | #define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) |
| 74 | #define GCFGC_CS_SHIFT 8 |
| 75 | #define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT) |
| 76 | #define GCFGC_CD_SHIFT 12 |
| 77 | #define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT) |
| 78 | #define GCFGC_UPDATE_SHIFT 5 |
| 79 | #define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT) |
| 80 | |
| 81 | /* |
| 82 | * MCHBAR |
| 83 | */ |
| 84 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 85 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 86 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 87 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
Felix Held | 6cd2c2f | 2018-07-29 18:04:14 +0200 | [diff] [blame] | 88 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 89 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 90 | #define MCHBAR8_AND_OR(x, and, or) \ |
| 91 | (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 92 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 93 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 94 | #define MCHBAR16_AND_OR(x, and, or) \ |
| 95 | (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 96 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 97 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 98 | #define MCHBAR32_AND_OR(x, and, or) \ |
| 99 | (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 100 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 101 | #define CHDECMISC 0x111 |
| 102 | #define STACKED_MEM (1 << 1) |
| 103 | |
| 104 | #define C0DRB0 0x200 |
| 105 | #define C0DRB1 0x202 |
| 106 | #define C0DRB2 0x204 |
| 107 | #define C0DRB3 0x206 |
| 108 | #define C0DRA01 0x208 |
| 109 | #define C0DRA23 0x20a |
| 110 | #define C0CKECTRL 0x260 |
| 111 | |
| 112 | #define C1DRB0 0x600 |
| 113 | #define C1DRB1 0x602 |
| 114 | #define C1DRB2 0x604 |
| 115 | #define C1DRB3 0x606 |
| 116 | #define C1DRA01 0x608 |
| 117 | #define C1DRA23 0x60a |
| 118 | #define C1CKECTRL 0x660 |
| 119 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 120 | #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 121 | #define PMSTS_WARM_RESET (1 << 8) |
| 122 | #define PMSTS_BOTH_SELFREFRESH (3 << 0) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 123 | |
| 124 | #define CLKCFG_MCHBAR 0x0c00 |
| 125 | #define CLKCFG_FSBCLK_SHIFT 0 |
| 126 | #define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) |
| 127 | #define CLKCFG_MEMCLK_SHIFT 4 |
| 128 | #define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) |
| 129 | #define CLKCFG_UPDATE (1 << 12) |
| 130 | |
Arthur Heymans | 5b30b82 | 2016-12-01 18:41:50 +0100 | [diff] [blame] | 131 | #define SSKPD_MCHBAR 0x0c20 /* 64 bit */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 132 | |
| 133 | /* |
| 134 | * DMIBAR |
| 135 | */ |
| 136 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 137 | #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) |
| 138 | #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) |
| 139 | #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 140 | |
| 141 | #define DMIVC0RCTL 0x14 |
| 142 | #define DMIVC1RCTL 0x20 |
| 143 | #define DMIVC1RSTS 0x26 |
| 144 | #define DMIESD 0x44 |
| 145 | #define DMILE1D 0x50 |
| 146 | #define DMILE1A 0x58 |
| 147 | #define DMILE2D 0x60 |
| 148 | #define DMILE2A 0x68 |
| 149 | |
| 150 | /* |
| 151 | * EPBAR |
| 152 | */ |
| 153 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 154 | #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) |
| 155 | #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) |
| 156 | #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 157 | |
| 158 | #define EPESD 0x44 |
| 159 | #define EPLE1D 0x50 |
| 160 | #define EPLE1A 0x58 |
| 161 | #define EPLE2D 0x60 |
| 162 | |
| 163 | #define NOP_CMD 0x2 |
| 164 | #define PRECHARGE_CMD 0x4 |
| 165 | #define MRS_CMD 0x6 |
| 166 | #define EMRS_CMD 0x8 |
| 167 | #define EMRS1_CMD (EMRS_CMD | 0x10) |
| 168 | #define EMRS2_CMD (EMRS_CMD | 0x20) |
| 169 | #define EMRS3_CMD (EMRS_CMD | 0x30) |
| 170 | #define ZQCAL_CMD 0xa |
| 171 | #define CBR_CMD 0xc |
| 172 | #define NORMALOP_CMD 0xe |
| 173 | |
| 174 | #define TOTAL_CHANNELS 2 |
| 175 | #define TOTAL_DIMMS 4 |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 176 | #define TOTAL_BYTELANES 8 |
Nico Huber | 3c20906 | 2016-11-26 02:03:25 +0100 | [diff] [blame] | 177 | #define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) |
Damien Zammit | 68e1dcf | 2016-06-03 15:39:30 +1000 | [diff] [blame] | 178 | #define RAW_CARD_UNPOPULATED 0xff |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 179 | #define RAW_CARD_POPULATED 0 |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 180 | |
Damien Zammit | 68e1dcf | 2016-06-03 15:39:30 +1000 | [diff] [blame] | 181 | #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) |
| 182 | #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 183 | #define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ |
| 184 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 185 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) |
| 186 | #define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ |
| 187 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ |
| 188 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) |
| 189 | #define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ |
| 190 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 191 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) |
| 192 | #define FOR_EACH_DIMM(idx) \ |
| 193 | for (idx = 0; idx < TOTAL_DIMMS; ++idx) |
| 194 | #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ |
| 195 | FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) |
Nico Huber | 696abfc | 2016-11-23 23:56:53 +0100 | [diff] [blame] | 196 | #define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ |
Nico Huber | 3c20906 | 2016-11-26 02:03:25 +0100 | [diff] [blame] | 197 | for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) |
Nico Huber | 696abfc | 2016-11-23 23:56:53 +0100 | [diff] [blame] | 198 | #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ |
| 199 | FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 200 | #define CHANNEL_IS_POPULATED(dimms, idx) \ |
| 201 | ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 202 | || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) |
| 203 | #define CHANNEL_IS_CARDF(dimms, idx) \ |
| 204 | ((dimms[idx<<1].card_type == 0xf) \ |
| 205 | || (dimms[(idx<<1) + 1].card_type == 0xf)) |
| 206 | #define IF_CHANNEL_POPULATED(dimms, idx) \ |
| 207 | if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 208 | || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 209 | #define FOR_EACH_CHANNEL(idx) \ |
| 210 | for (idx = 0; idx < TOTAL_CHANNELS; ++idx) |
| 211 | #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ |
| 212 | FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) |
| 213 | |
| 214 | #define RANKS_PER_CHANNEL 4 |
| 215 | #define RANK_IS_POPULATED(dimms, ch, r) \ |
Damien Zammit | 68e1dcf | 2016-06-03 15:39:30 +1000 | [diff] [blame] | 216 | (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ |
| 217 | ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 218 | #define IF_RANK_POPULATED(dimms, ch, r) \ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 219 | if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 220 | && ((r) < dimms[ch<<1].ranks)) \ |
| 221 | || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ |
| 222 | && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 223 | #define FOR_EACH_RANK_IN_CHANNEL(r) \ |
| 224 | for (r = 0; r < RANKS_PER_CHANNEL; ++r) |
| 225 | #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ |
| 226 | FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) |
| 227 | #define FOR_EACH_RANK(ch, r) \ |
| 228 | FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) |
| 229 | #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ |
| 230 | FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 231 | #define FOR_EACH_BYTELANE(l) \ |
| 232 | for (l = 0; l < TOTAL_BYTELANES; l++) |
| 233 | #define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ |
| 234 | FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 235 | |
| 236 | #define DDR3_MAX_CAS 18 |
| 237 | |
| 238 | enum fsb_clock { |
| 239 | FSB_CLOCK_800MHz = 0, |
| 240 | FSB_CLOCK_1066MHz = 1, |
| 241 | FSB_CLOCK_1333MHz = 2, |
| 242 | }; |
| 243 | |
| 244 | enum mem_clock { |
| 245 | MEM_CLOCK_400MHz = 0, |
| 246 | MEM_CLOCK_533MHz = 1, |
| 247 | MEM_CLOCK_667MHz = 2, |
| 248 | MEM_CLOCK_800MHz = 3, |
| 249 | MEM_CLOCK_1066MHz = 4, |
| 250 | MEM_CLOCK_1333MHz = 5, |
| 251 | }; |
| 252 | |
| 253 | enum ddr { |
| 254 | DDR2 = 2, |
| 255 | DDR3 = 3, |
| 256 | }; |
| 257 | |
| 258 | enum ddrxspd { |
| 259 | DDR2SPD = 0x8, |
| 260 | DDR3SPD = 0xb, |
| 261 | }; |
| 262 | |
| 263 | enum chip_width { /* as in DDR3 spd */ |
| 264 | CHIP_WIDTH_x4 = 0, |
| 265 | CHIP_WIDTH_x8 = 1, |
| 266 | CHIP_WIDTH_x16 = 2, |
| 267 | CHIP_WIDTH_x32 = 3, |
| 268 | }; |
| 269 | |
| 270 | enum chip_cap { /* as in DDR3 spd */ |
| 271 | CHIP_CAP_256M = 0, |
| 272 | CHIP_CAP_512M = 1, |
| 273 | CHIP_CAP_1G = 2, |
| 274 | CHIP_CAP_2G = 3, |
| 275 | CHIP_CAP_4G = 4, |
| 276 | CHIP_CAP_8G = 5, |
| 277 | CHIP_CAP_16G = 6, |
| 278 | }; |
| 279 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 280 | struct dll_setting { |
| 281 | u8 tap; |
| 282 | u8 pi; |
| 283 | u8 db_en; |
| 284 | u8 db_sel; |
| 285 | u8 clk_delay; |
| 286 | u8 coarse; |
| 287 | }; |
| 288 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 289 | struct rt_dqs_setting { |
| 290 | u8 tap; |
| 291 | u8 pi; |
| 292 | }; |
| 293 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 294 | enum n_banks { |
| 295 | N_BANKS_4 = 0, |
| 296 | N_BANKS_8 = 1, |
| 297 | }; |
| 298 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 299 | struct timings { |
| 300 | unsigned int CAS; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 301 | unsigned int tclk; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 302 | enum fsb_clock fsb_clk; |
| 303 | enum mem_clock mem_clk; |
| 304 | unsigned int tRAS; |
| 305 | unsigned int tRP; |
| 306 | unsigned int tRCD; |
| 307 | unsigned int tWR; |
| 308 | unsigned int tRFC; |
| 309 | unsigned int tWTR; |
| 310 | unsigned int tRRD; |
| 311 | unsigned int tRTP; |
| 312 | }; |
| 313 | |
| 314 | struct dimminfo { |
Damien Zammit | 68e1dcf | 2016-06-03 15:39:30 +1000 | [diff] [blame] | 315 | unsigned int card_type; /* 0xff: unpopulated, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 316 | 0xa - 0xf: raw card type A - F */ |
| 317 | enum chip_width width; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 318 | unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 319 | enum n_banks n_banks; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 320 | unsigned int ranks; |
| 321 | unsigned int rows; |
| 322 | unsigned int cols; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 323 | u16 spd_crc; |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 324 | u8 mirrored; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | struct rcven_timings { |
| 328 | u8 min_common_coarse; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 329 | u8 coarse_offset[TOTAL_BYTELANES]; |
| 330 | u8 medium[TOTAL_BYTELANES]; |
| 331 | u8 tap[TOTAL_BYTELANES]; |
| 332 | u8 pi[TOTAL_BYTELANES]; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 333 | }; |
| 334 | |
| 335 | /* The setup is up to two DIMMs per channel */ |
| 336 | struct sysinfo { |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 337 | int boot_path; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 338 | enum fsb_clock max_fsb; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 339 | |
| 340 | int dimm_config[2]; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 341 | int spd_type; |
| 342 | int channel_capacity[2]; |
| 343 | struct timings selected_timings; |
| 344 | struct dimminfo dimms[4]; |
| 345 | u8 spd_map[4]; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 346 | struct rcven_timings rcven_t[TOTAL_CHANNELS]; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 347 | /* |
| 348 | * The rt_dqs delay register for rank 0 seems to be used |
| 349 | * for all other ranks on the channel, so only save that |
| 350 | */ |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 351 | struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
| 352 | struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
| 353 | struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
Arthur Heymans | 7a3a319 | 2017-05-15 10:26:29 +0200 | [diff] [blame] | 354 | u8 nmode; |
Arthur Heymans | 0602ce6 | 2018-05-26 14:44:42 +0200 | [diff] [blame] | 355 | u8 stacked_mode; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 356 | }; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 357 | #define BOOT_PATH_NORMAL 0 |
| 358 | #define BOOT_PATH_WARM_RESET 1 |
| 359 | #define BOOT_PATH_RESUME 2 |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 360 | |
| 361 | enum ddr2_signals { |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 362 | CLKSET0 = 0, |
| 363 | CTRL0, |
| 364 | CLKSET1, |
| 365 | CMD, |
| 366 | CTRL1, |
| 367 | CTRL2, |
| 368 | CTRL3, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 369 | }; |
| 370 | |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 371 | #ifndef __BOOTBLOCK__ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 372 | void x4x_early_init(void); |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 373 | void x4x_late_init(int s3resume); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 374 | u32 decode_igd_memory_size(u32 gms); |
| 375 | u32 decode_igd_gtt_size(u32 gsm); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 376 | u32 decode_tseg_size(const u32 esmramc); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 377 | u8 decode_pciebar(u32 *const base, u32 *const len); |
| 378 | void sdram_initialize(int boot_path, const u8 *spd_map); |
Arthur Heymans | a2cc231 | 2017-05-15 10:13:36 +0200 | [diff] [blame] | 379 | void do_raminit(struct sysinfo *, int fast_boot); |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 380 | void rcven(struct sysinfo *s); |
Elyes HAOUAS | e951e8e | 2019-06-15 11:03:00 +0200 | [diff] [blame^] | 381 | u32 fsb_to_mhz(u32 speed); |
| 382 | u32 ddr_to_mhz(u32 speed); |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 383 | u32 test_address(int channel, int rank); |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 384 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); |
| 385 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting); |
| 386 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, |
| 387 | struct rt_dqs_setting *dqs_setting); |
| 388 | int do_write_training(struct sysinfo *s); |
| 389 | int do_read_training(struct sysinfo *s); |
Arthur Heymans | b5170c3 | 2017-12-25 20:13:28 +0100 | [diff] [blame] | 390 | void search_write_leveling(struct sysinfo *s); |
| 391 | void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 392 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 393 | extern const struct dll_setting default_ddr2_667_ctrl[7]; |
| 394 | extern const struct dll_setting default_ddr2_800_ctrl[7]; |
| 395 | extern const struct dll_setting default_ddr3_800_ctrl[2][7]; |
| 396 | extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; |
| 397 | extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 398 | extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; |
| 399 | extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; |
| 400 | extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; |
| 401 | extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; |
| 402 | extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; |
| 403 | extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; |
| 404 | extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; |
| 405 | extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; |
| 406 | extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; |
| 407 | extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 408 | extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 409 | extern const u8 post_jedec_tab[3][4][2]; |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 410 | extern const u32 ddr3_c2_tab[2][3][6][2]; |
| 411 | extern const u8 ddr3_c2_x264[3][6]; |
| 412 | extern const u16 ddr3_c2_x23c[3][6]; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 413 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 414 | struct acpi_rsdp; |
Antonello Dettori | 60a6e15 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 415 | #ifndef __SIMPLE_DEVICE__ |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 416 | unsigned long northbridge_write_acpi_tables(struct device *device, |
| 417 | unsigned long start, struct acpi_rsdp *rsdp); |
Antonello Dettori | 60a6e15 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 418 | #endif /* __SIMPLE_DEVICE__ */ |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 419 | #endif |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 420 | #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */ |