commit 0d284959dcaf16416ce27b480339144fd6068bfe
author Arthur Heymans <arthur@aheymans.xyz> Thu May 25 19:55:52 2017 +0200
committer Martin Roth <martinroth@google.com> Thu May 24 13:05:32 2018 +0000
tree 5add4dd81fba292a6ef487ef2d1980e6b53c0e19
parent 3fa103a60261a3cd1925858a317dc1ffa89797f7

nb/intel/x4x: Adapt post JEDEC for DDR3

Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/x4x/x4x.h

diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 13ca783..95f618d 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -392,6 +392,7 @@
 extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
 extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
 extern const u8 ddr3_emrs1_rtt_nom_config[16][4];
+extern const u8 post_jedec_tab[3][4][2];
 extern const u32 ddr3_c2_tab[2][3][6][2];
 extern const u8 ddr3_c2_x264[3][6];
 extern const u16 ddr3_c2_x23c[3][6];