nb/intel/x4x: Add DDR3 JEDEC init
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)
This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.
The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.
Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 8532d60..53b73ae 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -309,6 +309,7 @@
unsigned int rows;
unsigned int cols;
u16 spd_crc;
+ u8 mirrored;
};
struct rcven_timings {
@@ -388,6 +389,7 @@
extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES];
extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
+extern const u8 ddr3_emrs1_rtt_nom_config[16][4];
struct acpi_rsdp;
#ifndef __SIMPLE_DEVICE__