Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __NORTHBRIDGE_INTEL_X4X_H__ |
| 19 | #define __NORTHBRIDGE_INTEL_X4X_H__ |
| 20 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | /* |
| 22 | * D0:F0 |
| 23 | */ |
| 24 | #define D0F0_EPBAR_LO 0x40 |
| 25 | #define D0F0_EPBAR_HI 0x44 |
| 26 | #define D0F0_MCHBAR_LO 0x48 |
| 27 | #define D0F0_MCHBAR_HI 0x4c |
| 28 | #define D0F0_GGC 0x52 |
| 29 | #define D0F0_DEVEN 0x54 |
| 30 | #define D0F0_PCIEXBAR_LO 0x60 |
| 31 | #define D0F0_PCIEXBAR_HI 0x64 |
| 32 | #define D0F0_DMIBAR_LO 0x68 |
| 33 | #define D0F0_DMIBAR_HI 0x6c |
| 34 | #define D0F0_PMBASE 0x78 |
| 35 | #define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ |
| 36 | #define D0F0_REMAPBASE 0x98 |
| 37 | #define D0F0_REMAPLIMIT 0x9a |
| 38 | #define D0F0_SMRAM 0x9d |
| 39 | #define D0F0_ESMRAMC 0x9e |
| 40 | #define D0F0_TOM 0xa0 |
| 41 | #define D0F0_TOUUD 0xa2 |
| 42 | #define D0F0_TOLUD 0xb0 |
| 43 | #define D0F0_GBSM 0xa4 |
| 44 | #define D0F0_BGSM 0xa8 |
| 45 | #define D0F0_TSEG 0xac |
| 46 | #define D0F0_SKPD 0xdc /* Scratchpad Data */ |
| 47 | #define D0F0_CAPID0 0xe0 |
| 48 | |
| 49 | /* |
| 50 | * D1:F0 PEG |
| 51 | */ |
| 52 | #define PEG_CAP 0xa2 |
| 53 | #define SLOTCAP 0xb4 |
| 54 | #define PEGLC 0xec |
| 55 | #define D1F0_VCCAP 0x104 |
| 56 | #define D1F0_VC0RCTL 0x114 |
| 57 | |
| 58 | /* |
| 59 | * Graphics frequencies |
| 60 | */ |
| 61 | #define GCFGC_PCIDEV PCI_DEV(0, 2, 0) |
| 62 | #define GCFGC_OFFSET 0xf0 |
| 63 | #define GCFGC_CR_SHIFT 0 |
| 64 | #define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) |
| 65 | #define GCFGC_CS_SHIFT 8 |
| 66 | #define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT) |
| 67 | #define GCFGC_CD_SHIFT 12 |
| 68 | #define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT) |
| 69 | #define GCFGC_UPDATE_SHIFT 5 |
| 70 | #define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT) |
| 71 | |
| 72 | /* |
| 73 | * MCHBAR |
| 74 | */ |
| 75 | |
| 76 | #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) |
| 77 | #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) |
| 78 | #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) |
| 79 | |
| 80 | #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ |
| 81 | #define PMSTS_WARM_RESET (1 << 1) |
| 82 | #define PMSTS_BOTH_SELFREFRESH (1 << 0) |
| 83 | |
| 84 | #define CLKCFG_MCHBAR 0x0c00 |
| 85 | #define CLKCFG_FSBCLK_SHIFT 0 |
| 86 | #define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) |
| 87 | #define CLKCFG_MEMCLK_SHIFT 4 |
| 88 | #define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) |
| 89 | #define CLKCFG_UPDATE (1 << 12) |
| 90 | |
| 91 | #define SSKPD_MCHBAR 0x0c1c |
| 92 | #define SSKPD_CLK_SHIFT 0 |
| 93 | #define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT) |
| 94 | |
| 95 | /* |
| 96 | * DMIBAR |
| 97 | */ |
| 98 | |
| 99 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
| 100 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 101 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 102 | |
| 103 | #define DMIVC0RCTL 0x14 |
| 104 | #define DMIVC1RCTL 0x20 |
| 105 | #define DMIVC1RSTS 0x26 |
| 106 | #define DMIESD 0x44 |
| 107 | #define DMILE1D 0x50 |
| 108 | #define DMILE1A 0x58 |
| 109 | #define DMILE2D 0x60 |
| 110 | #define DMILE2A 0x68 |
| 111 | |
| 112 | /* |
| 113 | * EPBAR |
| 114 | */ |
| 115 | |
| 116 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
| 117 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 118 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 119 | |
| 120 | #define EPESD 0x44 |
| 121 | #define EPLE1D 0x50 |
| 122 | #define EPLE1A 0x58 |
| 123 | #define EPLE2D 0x60 |
| 124 | |
| 125 | #define NOP_CMD 0x2 |
| 126 | #define PRECHARGE_CMD 0x4 |
| 127 | #define MRS_CMD 0x6 |
| 128 | #define EMRS_CMD 0x8 |
| 129 | #define EMRS1_CMD (EMRS_CMD | 0x10) |
| 130 | #define EMRS2_CMD (EMRS_CMD | 0x20) |
| 131 | #define EMRS3_CMD (EMRS_CMD | 0x30) |
| 132 | #define ZQCAL_CMD 0xa |
| 133 | #define CBR_CMD 0xc |
| 134 | #define NORMALOP_CMD 0xe |
| 135 | |
| 136 | #define TOTAL_CHANNELS 2 |
| 137 | #define TOTAL_DIMMS 4 |
| 138 | |
| 139 | #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) |
| 140 | #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) |
| 141 | #define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ |
| 142 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 143 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) |
| 144 | #define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ |
| 145 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ |
| 146 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) |
| 147 | #define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ |
| 148 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 149 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) |
| 150 | #define FOR_EACH_DIMM(idx) \ |
| 151 | for (idx = 0; idx < TOTAL_DIMMS; ++idx) |
| 152 | #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ |
| 153 | FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) |
| 154 | #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) |
| 155 | #define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) |
| 156 | #define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) |
| 157 | #define FOR_EACH_CHANNEL(idx) \ |
| 158 | for (idx = 0; idx < TOTAL_CHANNELS; ++idx) |
| 159 | #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ |
| 160 | FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) |
| 161 | |
| 162 | #define RANKS_PER_CHANNEL 4 |
| 163 | #define RANK_IS_POPULATED(dimms, ch, r) \ |
| 164 | ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ |
| 165 | (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
| 166 | #define IF_RANK_POPULATED(dimms, ch, r) \ |
| 167 | if ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ |
| 168 | (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
| 169 | #define FOR_EACH_RANK_IN_CHANNEL(r) \ |
| 170 | for (r = 0; r < RANKS_PER_CHANNEL; ++r) |
| 171 | #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ |
| 172 | FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) |
| 173 | #define FOR_EACH_RANK(ch, r) \ |
| 174 | FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) |
| 175 | #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ |
| 176 | FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) |
| 177 | |
| 178 | #define DDR3_MAX_CAS 18 |
| 179 | |
| 180 | enum fsb_clock { |
| 181 | FSB_CLOCK_800MHz = 0, |
| 182 | FSB_CLOCK_1066MHz = 1, |
| 183 | FSB_CLOCK_1333MHz = 2, |
| 184 | }; |
| 185 | |
| 186 | enum mem_clock { |
| 187 | MEM_CLOCK_400MHz = 0, |
| 188 | MEM_CLOCK_533MHz = 1, |
| 189 | MEM_CLOCK_667MHz = 2, |
| 190 | MEM_CLOCK_800MHz = 3, |
| 191 | MEM_CLOCK_1066MHz = 4, |
| 192 | MEM_CLOCK_1333MHz = 5, |
| 193 | }; |
| 194 | |
| 195 | enum ddr { |
| 196 | DDR2 = 2, |
| 197 | DDR3 = 3, |
| 198 | }; |
| 199 | |
| 200 | enum ddrxspd { |
| 201 | DDR2SPD = 0x8, |
| 202 | DDR3SPD = 0xb, |
| 203 | }; |
| 204 | |
| 205 | enum chip_width { /* as in DDR3 spd */ |
| 206 | CHIP_WIDTH_x4 = 0, |
| 207 | CHIP_WIDTH_x8 = 1, |
| 208 | CHIP_WIDTH_x16 = 2, |
| 209 | CHIP_WIDTH_x32 = 3, |
| 210 | }; |
| 211 | |
| 212 | enum chip_cap { /* as in DDR3 spd */ |
| 213 | CHIP_CAP_256M = 0, |
| 214 | CHIP_CAP_512M = 1, |
| 215 | CHIP_CAP_1G = 2, |
| 216 | CHIP_CAP_2G = 3, |
| 217 | CHIP_CAP_4G = 4, |
| 218 | CHIP_CAP_8G = 5, |
| 219 | CHIP_CAP_16G = 6, |
| 220 | }; |
| 221 | |
| 222 | struct timings { |
| 223 | unsigned int CAS; |
| 224 | enum fsb_clock fsb_clk; |
| 225 | enum mem_clock mem_clk; |
| 226 | unsigned int tRAS; |
| 227 | unsigned int tRP; |
| 228 | unsigned int tRCD; |
| 229 | unsigned int tWR; |
| 230 | unsigned int tRFC; |
| 231 | unsigned int tWTR; |
| 232 | unsigned int tRRD; |
| 233 | unsigned int tRTP; |
| 234 | }; |
| 235 | |
| 236 | struct dimminfo { |
| 237 | unsigned int card_type; /* 0x0: unpopulated, |
| 238 | 0xa - 0xf: raw card type A - F */ |
| 239 | enum chip_width width; |
| 240 | enum chip_cap chip_capacity; |
| 241 | unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ |
| 242 | unsigned int sides; |
| 243 | unsigned int banks; |
| 244 | unsigned int ranks; |
| 245 | unsigned int rows; |
| 246 | unsigned int cols; |
| 247 | unsigned int cas_latencies; |
| 248 | unsigned int tAAmin; |
| 249 | unsigned int tCKmin; |
| 250 | unsigned int tWR; |
| 251 | unsigned int tRP; |
| 252 | unsigned int tRCD; |
| 253 | unsigned int tRAS; |
| 254 | unsigned int rank_capacity_mb; /* per rank in Mega Bytes */ |
| 255 | u8 spd_data[256]; |
| 256 | }; |
| 257 | |
| 258 | /* The setup is up to two DIMMs per channel */ |
| 259 | struct sysinfo { |
| 260 | int txt_enabled; |
| 261 | int cores; |
| 262 | int boot_path; |
| 263 | int max_ddr2_mhz; |
| 264 | int max_ddr3_mt; |
| 265 | enum fsb_clock max_fsb; |
| 266 | int max_fsb_mhz; |
| 267 | int max_render_mhz; |
| 268 | int enable_igd; |
| 269 | int enable_peg; |
| 270 | u16 ggc; |
| 271 | |
| 272 | int dimm_config[2]; |
| 273 | int dimms_per_ch; |
| 274 | int spd_type; |
| 275 | int channel_capacity[2]; |
| 276 | struct timings selected_timings; |
| 277 | struct dimminfo dimms[4]; |
| 278 | u8 spd_map[4]; |
| 279 | }; |
| 280 | |
| 281 | enum ddr2_signals { |
| 282 | CLKSET0 = 0, |
| 283 | CTRL0, |
| 284 | CLKSET1, |
| 285 | CMD, |
| 286 | CTRL1, |
| 287 | CTRL2, |
| 288 | CTRL3, |
| 289 | DQS1, |
| 290 | DQS2, |
| 291 | DQS3, |
| 292 | DQS4, |
| 293 | DQS5, |
| 294 | DQS6, |
| 295 | DQS7, |
| 296 | DQS8, |
| 297 | DQ1, |
| 298 | DQ2, |
| 299 | DQ3, |
| 300 | DQ4, |
| 301 | DQ5, |
| 302 | DQ6, |
| 303 | DQ7, |
| 304 | DQ8 |
| 305 | }; |
| 306 | |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame^] | 307 | #ifndef __BOOTBLOCK__ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 308 | void x4x_early_init(void); |
| 309 | u32 decode_igd_memory_size(u32 gms); |
| 310 | u32 decode_igd_gtt_size(u32 gsm); |
| 311 | u8 decode_pciebar(u32 *const base, u32 *const len); |
| 312 | void sdram_initialize(int boot_path, const u8 *spd_map); |
| 313 | void raminit_ddr2(struct sysinfo *); |
| 314 | |
| 315 | struct acpi_rsdp; |
| 316 | unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame^] | 317 | #endif |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 318 | #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */ |