Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 5 | #include <device/smbus_host.h> |
Angel Pons | e1a616c | 2020-06-21 17:02:43 +0200 | [diff] [blame^] | 6 | #include <southbridge/intel/common/pmutil.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 7 | #include "i82801ix.h" |
Arthur Heymans | 9ed0df4 | 2019-10-12 14:18:18 +0200 | [diff] [blame] | 8 | #include "chip.h" |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 9 | |
Angel Pons | 3bff419 | 2020-06-21 13:22:08 +0200 | [diff] [blame] | 10 | void i82801ix_lpc_setup(void) |
| 11 | { |
| 12 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 13 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 14 | const struct southbridge_intel_i82801ix_config *config = NULL; |
| 15 | |
| 16 | /* Configure serial IRQs.*/ |
| 17 | pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); |
| 18 | /* |
| 19 | * Enable some common LPC IO ranges: |
| 20 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 21 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 22 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 23 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 24 | * - 0x2f8-0x2ff COMB |
| 25 | * - 0x3f8-0x3ff COMA |
| 26 | * - 0x208-0x20f GAMEH |
| 27 | * - 0x200-0x207 GAMEL |
| 28 | */ |
| 29 | pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); |
| 30 | pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); |
| 31 | |
| 32 | /* Set up generic decode ranges */ |
| 33 | if (!dev || !dev->chip_info) |
| 34 | return; |
| 35 | config = dev->chip_info; |
| 36 | |
| 37 | pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); |
| 38 | pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); |
| 39 | pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); |
| 40 | pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); |
| 41 | } |
| 42 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 43 | void i82801ix_early_init(void) |
| 44 | { |
Antonello Dettori | 196e3d4 | 2016-09-01 17:04:14 +0200 | [diff] [blame] | 45 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 46 | |
Kyösti Mälkki | 1cfafe2 | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 47 | if (ENV_ROMSTAGE) |
| 48 | enable_smbus(); |
| 49 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 50 | /* Set up RCBA. */ |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 51 | pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 52 | |
| 53 | /* Set up PMBASE. */ |
| 54 | pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); |
| 55 | /* Enable PMBASE. */ |
| 56 | pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); |
| 57 | |
| 58 | /* Set up GPIOBASE. */ |
| 59 | pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); |
| 60 | /* Enable GPIO. */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 61 | pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 62 | |
| 63 | /* Reset watchdog. */ |
| 64 | outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ |
| 65 | outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ |
| 66 | |
| 67 | /* Enable upper 128bytes of CMOS. */ |
| 68 | RCBA32(0x3400) = (1 << 2); |
| 69 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 70 | /* Initialize power management initialization |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 71 | register early as it affects reboot behavior. */ |
| 72 | /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 |
| 73 | and 0xe (required if ME is disabled but present), bit 31 locks it. |
| 74 | The other bits are 'must write'. */ |
| 75 | u8 reg8 = pci_read_config8(d31f0, 0xac); |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 76 | |
| 77 | /* FIXME: It's a 8-bit variable!!! */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 78 | reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); |
| 79 | pci_write_config8(d31f0, 0xac, reg8); |
| 80 | |
| 81 | /* TODO: If RTC power failed, reset RTC state machine |
| 82 | (set, then reset RTC 0x0b bit7) */ |
| 83 | |
| 84 | /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) |
| 85 | before they get cleared. */ |
| 86 | } |