Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 19 | #include "i82801ix.h" |
Arthur Heymans | 9ed0df4 | 2019-10-12 14:18:18 +0200 | [diff] [blame^] | 20 | #include "chip.h" |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 21 | |
| 22 | void i82801ix_early_init(void) |
| 23 | { |
Antonello Dettori | 196e3d4 | 2016-09-01 17:04:14 +0200 | [diff] [blame] | 24 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 25 | |
| 26 | /* Set up RCBA. */ |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 27 | pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 28 | |
| 29 | /* Set up PMBASE. */ |
| 30 | pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); |
| 31 | /* Enable PMBASE. */ |
| 32 | pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); |
| 33 | |
| 34 | /* Set up GPIOBASE. */ |
| 35 | pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); |
| 36 | /* Enable GPIO. */ |
| 37 | pci_write_config8(d31f0, D31F0_GPIO_CNTL, |
| 38 | pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); |
| 39 | |
| 40 | /* Reset watchdog. */ |
| 41 | outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ |
| 42 | outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ |
| 43 | |
| 44 | /* Enable upper 128bytes of CMOS. */ |
| 45 | RCBA32(0x3400) = (1 << 2); |
| 46 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 47 | /* Initialize power management initialization |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 48 | register early as it affects reboot behavior. */ |
| 49 | /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 |
| 50 | and 0xe (required if ME is disabled but present), bit 31 locks it. |
| 51 | The other bits are 'must write'. */ |
| 52 | u8 reg8 = pci_read_config8(d31f0, 0xac); |
| 53 | reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); |
| 54 | pci_write_config8(d31f0, 0xac, reg8); |
| 55 | |
| 56 | /* TODO: If RTC power failed, reset RTC state machine |
| 57 | (set, then reset RTC 0x0b bit7) */ |
| 58 | |
| 59 | /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) |
| 60 | before they get cleared. */ |
| 61 | } |
Arthur Heymans | 9ed0df4 | 2019-10-12 14:18:18 +0200 | [diff] [blame^] | 62 | |
| 63 | void i82801ix_lpc_decode(void) |
| 64 | { |
| 65 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 66 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 67 | const struct southbridge_intel_i82801ix_config *config = NULL; |
| 68 | |
| 69 | /* Configure serial IRQs.*/ |
| 70 | pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); |
| 71 | /* |
| 72 | * Enable some common LPC IO ranges: |
| 73 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 74 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 75 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 76 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 77 | * - 0x2f8-0x2ff COMB |
| 78 | * - 0x3f8-0x3ff COMA |
| 79 | */ |
| 80 | pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); |
| 81 | pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); |
| 82 | |
| 83 | /* Set up generic decode ranges */ |
| 84 | if (!dev || !dev->chip_info) |
| 85 | return; |
| 86 | config = dev->chip_info; |
| 87 | |
| 88 | pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); |
| 89 | pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); |
| 90 | pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); |
| 91 | pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); |
| 92 | } |