Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 20 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | #include <commonlib/helpers.h> |
| 22 | #include <stdint.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 23 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 24 | #include <device/pci_ops.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 25 | #include <device/pci_def.h> |
| 26 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 27 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 28 | #include <cpu/x86/mtrr.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 29 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 30 | #include <program_loading.h> |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 31 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 32 | #include <stage_cache.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 33 | |
| 34 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 35 | u32 decode_igd_memory_size(const u32 gms) |
| 36 | { |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 37 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 38 | 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
| 39 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 40 | if (gms >= ARRAY_SIZE(ggc2uma)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 41 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 42 | |
| 43 | return ggc2uma[gms] << 10; |
| 44 | } |
| 45 | |
| 46 | /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ |
| 47 | u32 decode_igd_gtt_size(const u32 gsm) |
| 48 | { |
| 49 | static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 50 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 51 | if (gsm >= ARRAY_SIZE(ggc2gtt)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 52 | die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); |
| 53 | |
| 54 | return ggc2gtt[gsm] << 10; |
| 55 | } |
| 56 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 57 | /** Decodes used TSEG size to bytes. */ |
| 58 | u32 decode_tseg_size(const u32 esmramc) |
| 59 | { |
| 60 | if (!(esmramc & 1)) |
| 61 | return 0; |
| 62 | |
| 63 | switch ((esmramc >> 1) & 3) { |
| 64 | case 0: |
| 65 | return 1 << 20; |
| 66 | case 1: |
| 67 | return 2 << 20; |
| 68 | case 2: |
| 69 | return 8 << 20; |
| 70 | case 3: |
| 71 | default: |
| 72 | die("Bad TSEG setting.\n"); |
| 73 | } |
| 74 | } |
| 75 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 76 | u8 decode_pciebar(u32 *const base, u32 *const len) |
| 77 | { |
| 78 | *base = 0; |
| 79 | *len = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 80 | const pci_devfn_t dev = PCI_DEV(0, 0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 81 | u32 pciexbar = 0; |
| 82 | u32 pciexbar_reg; |
| 83 | u32 reg32; |
| 84 | int max_buses; |
| 85 | const struct { |
| 86 | u16 num_buses; |
| 87 | u32 addr_mask; |
| 88 | } busmask[] = { |
| 89 | {256, 0xf0000000}, |
| 90 | {128, 0xf8000000}, |
| 91 | {64, 0xfc000000}, |
| 92 | {0, 0}, |
| 93 | }; |
| 94 | |
| 95 | pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); |
| 96 | |
| 97 | if (!(pciexbar_reg & 1)) { |
| 98 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | reg32 = (pciexbar_reg >> 1) & 3; |
| 103 | pciexbar = pciexbar_reg & busmask[reg32].addr_mask; |
| 104 | max_buses = busmask[reg32].num_buses; |
| 105 | |
| 106 | if (!pciexbar) { |
| 107 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | *base = pciexbar; |
| 112 | *len = max_buses << 20; |
| 113 | return 1; |
| 114 | } |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 115 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 116 | u32 northbridge_get_tseg_size(void) |
| 117 | { |
| 118 | const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); |
| 119 | return decode_tseg_size(esmramc); |
| 120 | } |
| 121 | |
| 122 | u32 northbridge_get_tseg_base(void) |
| 123 | { |
| 124 | return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); |
| 125 | } |
| 126 | |
| 127 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 128 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
Elyes HAOUAS | 64f6b71 | 2018-08-07 12:16:56 +0200 | [diff] [blame] | 129 | * 1 MiB alignment. As this may cause very greedy MTRR setup, push |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 130 | * CBMEM top downwards to 4 MiB boundary. |
| 131 | */ |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 132 | void *cbmem_top(void) |
| 133 | { |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 134 | uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 135 | return (void *) top_of_ram; |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 136 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 137 | |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 138 | void stage_cache_external_region(void **base, size_t *size) |
| 139 | { |
Kyösti Mälkki | bccd2b6 | 2019-08-02 06:12:03 +0300 | [diff] [blame] | 140 | /* The stage cache lives at the end of the TSEG region. |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 141 | * The top of RAM is defined to be the TSEG base address. |
| 142 | */ |
| 143 | *size = CONFIG_SMM_RESERVED_SIZE; |
Kyösti Mälkki | bccd2b6 | 2019-08-02 06:12:03 +0300 | [diff] [blame] | 144 | *base = (void *)((uintptr_t)northbridge_get_tseg_base() |
| 145 | + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 146 | } |
| 147 | |
Arthur Heymans | 4ff675e | 2018-06-03 10:49:11 +0200 | [diff] [blame] | 148 | /* platform_enter_postcar() determines the stack to use after |
| 149 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 150 | * and continues execution in postcar stage. */ |
| 151 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 152 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 153 | struct postcar_frame pcf; |
| 154 | uintptr_t top_of_ram; |
| 155 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 156 | if (postcar_frame_init(&pcf, 0)) |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 157 | die("Unable to initialize postcar frame.\n"); |
| 158 | |
| 159 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 160 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 161 | |
| 162 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 163 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 164 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 165 | /* Cache 8 MiB region below the top of ram and 2 MiB above top of |
| 166 | * ram to cover both cbmem as the TSEG region. |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 167 | */ |
| 168 | top_of_ram = (uintptr_t)cbmem_top(); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 169 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, |
| 170 | MTRR_TYPE_WRBACK); |
| 171 | postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), |
| 172 | northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 173 | |
Arthur Heymans | 4ff675e | 2018-06-03 10:49:11 +0200 | [diff] [blame] | 174 | run_postcar_phase(&pcf); |
| 175 | |
| 176 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 177 | } |