intel i945 gm45 x4x: Apply cbmem_top() alignment
Force modest 4 MiB alignment to help with MTRR assignment.
Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17780
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 09eec47..2a5d7e5 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -89,10 +89,15 @@
return 1;
}
+/* Depending of UMA and TSEG configuration, TSEG might start at any
+ * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * CBMEM top downwards to 4 MiB boundary.
+ */
void *cbmem_top(void)
{
- u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
- return (void*)(ramtop);
+ uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
+ top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
+ return (void *) top_of_ram;
}
void *setup_stack_and_mtrrs(void)