Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
| 20 | #include <commonlib/helpers.h> |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <console/console.h> |
| 25 | #include <northbridge/intel/x4x/x4x.h> |
| 26 | |
| 27 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 28 | u32 decode_igd_memory_size(const u32 gms) |
| 29 | { |
| 30 | static const u16 ggc2uma[] = { 0, 0, 0, 0, 0, |
| 31 | 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
| 32 | |
| 33 | if (gms > ARRAY_SIZE(ggc2uma)) |
| 34 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 35 | |
| 36 | return ggc2uma[gms] << 10; |
| 37 | } |
| 38 | |
| 39 | /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ |
| 40 | u32 decode_igd_gtt_size(const u32 gsm) |
| 41 | { |
| 42 | static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 43 | |
| 44 | if (gsm > ARRAY_SIZE(ggc2gtt)) |
| 45 | die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); |
| 46 | |
| 47 | return ggc2gtt[gsm] << 10; |
| 48 | } |
| 49 | |
| 50 | u8 decode_pciebar(u32 *const base, u32 *const len) |
| 51 | { |
| 52 | *base = 0; |
| 53 | *len = 0; |
| 54 | const pci_devfn_t dev = PCI_DEV(0,0,0); |
| 55 | u32 pciexbar = 0; |
| 56 | u32 pciexbar_reg; |
| 57 | u32 reg32; |
| 58 | int max_buses; |
| 59 | const struct { |
| 60 | u16 num_buses; |
| 61 | u32 addr_mask; |
| 62 | } busmask[] = { |
| 63 | {256, 0xf0000000}, |
| 64 | {128, 0xf8000000}, |
| 65 | {64, 0xfc000000}, |
| 66 | {0, 0}, |
| 67 | }; |
| 68 | |
| 69 | pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); |
| 70 | |
| 71 | if (!(pciexbar_reg & 1)) { |
| 72 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | reg32 = (pciexbar_reg >> 1) & 3; |
| 77 | pciexbar = pciexbar_reg & busmask[reg32].addr_mask; |
| 78 | max_buses = busmask[reg32].num_buses; |
| 79 | |
| 80 | if (!pciexbar) { |
| 81 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | *base = pciexbar; |
| 86 | *len = max_buses << 20; |
| 87 | return 1; |
| 88 | } |