intel/i945,gm45,pineview,x4x: Fix stage cache location
The cache is at the end of TSEG. As SMM_RESERVED_SIZE was
half of TSEG size, offseting from the start gave same
position.
Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 54295a9..dda8387 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -137,13 +137,12 @@
void stage_cache_external_region(void **base, size_t *size)
{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ /* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after