Gitiles
Code Review Sign In
review.coreboot.org / coreboot / db2e11841ad69d52a610577abb0aab288eb094b7 / . / src / vendorcode / amd / agesa / f16kb / Config / PlatformInstall.h
blob: 4606443632319f3d6411dba7d7708c4fac791c9b [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45/*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
50
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]51VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
52 //ModuleHeaderSignature
53 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
54 Int32FromChar ('0', '0', '0', '0'),
55 //ModuleIdentifier[8]
56 AGESA_ID,
57 //ModuleVersion[12]
58 AGESA_VERSION_STRING,
59 //ModuleDispatcher
60 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
61 //NextBlock
62 NULL
63};
64
Angel Pons64829162020-05-21 15:29:17 +0200[diff] [blame]65/* The default fixed MTRR values to be set after memory initialization */
66static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
67{
68 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
69 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
70 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
71 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
72 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
73 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
74 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
75 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
76 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
77 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
78 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
79 { CPU_LIST_TERMINAL },
80};
81
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]82/* Process solution defined socket / family installations
83 *
84 * As part of the release package for each image, define the options below to select the
85 * AGESA processor support included in that image.
86 */
87
88/* Default sockets to off */
89#define OPTION_FT3_SOCKET_SUPPORT FALSE
90
91/* Default families to off */
92#define OPTION_FAMILY15H_MODEL_1x FALSE
93#define OPTION_FAMILY16H_MODEL_0x FALSE
94
95
96/* Enable the appropriate socket support */
97
98#ifdef INSTALL_FT3_SOCKET_SUPPORT
99 #if INSTALL_FT3_SOCKET_SUPPORT == TRUE
100 #undef OPTION_FT3_SOCKET_SUPPORT
101 #define OPTION_FT3_SOCKET_SUPPORT TRUE
102 #endif
103#endif
104
105
106
107// F16_0x is supported in FT3
108#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
109 #if INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
110 #undef OPTION_FAMILY16H
111 #define OPTION_FAMILY16H TRUE
112 #undef OPTION_FAMILY16H_MODEL_0x
113 #define OPTION_FAMILY16H_MODEL_0x TRUE
114 #endif
115#endif
116
117/* Turn off families not required by socket designations */
118#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
119 #undef OPTION_FAMILY15H
120 #define OPTION_FAMILY15H FALSE
121#endif
122
123#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
124 #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
125 #undef OPTION_FAMILY16H_MODEL_0x
126 #define OPTION_FAMILY16H_MODEL_0x FALSE
127 #endif
128#endif
129
130
131#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
132 #undef OPTION_FAMILY16H
133 #define OPTION_FAMILY16H FALSE
134#endif
135
136
137#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
138 #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
139 #error No FT3 supported families included in the build
140 #endif
141#endif
142
143
144/* Process AGESA private data
145 *
146 * Turn on appropriate CPU models and memory controllers,
147 * as well as some other memory controls.
148 */
149
150/* Default all models to off */
151#define OPTION_FAMILY15H_TN FALSE
152#define OPTION_FAMILY16H_KB FALSE
153#define OPTION_FAMILY15H_UNKNOWN FALSE
154
155/* Default all memory controllers to off */
156#define OPTION_MEMCTLR_TN FALSE
157#define OPTION_MEMCTLR_KB FALSE
158
159/* Default all memory controls to off */
160#define OPTION_HW_WRITE_LEV_TRAINING FALSE
161#define OPTION_SW_WRITE_LEV_TRAINING FALSE
162#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
163#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
164#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
165#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
166#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
167#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
168#define OPTION_MAX_RD_LAT_TRAINING FALSE
169#define OPTION_HW_DRAM_INIT FALSE
170#define OPTION_SW_DRAM_INIT FALSE
171#define OPTION_S3_MEM_SUPPORT FALSE
172#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
173#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
174#define OPTION_RDDQS_2D_TRAINING FALSE
175#define OPTION_PRE_MEM_INIT FALSE
176#define OPTION_POST_MEM_INIT FALSE
177
178/* Defaults for public user options */
179#define OPTION_UDIMMS FALSE
180#define OPTION_RDIMMS FALSE
181#define OPTION_SODIMMS FALSE
182#define OPTION_LRDIMMS FALSE
183#define OPTION_DDR2 FALSE
184#define OPTION_DDR3 FALSE
185#define OPTION_ECC FALSE
186#define OPTION_BANK_INTERLEAVE FALSE
187#define OPTION_DCT_INTERLEAVE FALSE
188#define OPTION_NODE_INTERLEAVE FALSE
189#define OPTION_PARALLEL_TRAINING FALSE
190#define OPTION_ONLINE_SPARE FALSE
191#define OPTION_MEM_RESTORE FALSE
192#define OPTION_DIMM_EXCLUDE FALSE
193#define OPTION_AMP FALSE
194#define OPTION_DATA_EYE FALSE
195#define OPTION_AGGRESSOR FALSE
196
197/* Default all CPU controls to off */
198#define OPTION_MULTISOCKET FALSE
199#define OPTION_CRAT FALSE
200#define OPTION_CDIT FALSE
201#define OPTION_SRAT FALSE
202#define OPTION_SLIT FALSE
203#define OPTION_HT_ASSIST FALSE
204#define OPTION_ATM_MODE FALSE
205#define OPTION_NBR_CACHE FALSE
206#define OPTION_CPU_CORELEVELING FALSE
207#define OPTION_MSG_BASED_C1E FALSE
208#define OPTION_CPU_CFOH FALSE
209#define OPTION_C6_STATE FALSE
210#define OPTION_IO_CSTATE FALSE
211#define OPTION_CPB FALSE
212#define OPTION_CPU_APM FALSE
213#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
214#define OPTION_CPU_PSTATE_HPC_MODE FALSE
215#define OPTION_CPU_TDP_LIMITING FALSE
216#define OPTION_CPU_PSI FALSE
217#define OPTION_CPU_HTC FALSE
218#define OPTION_S3SCRIPT FALSE
219#define OPTION_GFX_RECOVERY FALSE
220#define OPTION_CPU_SCS FALSE
221#define OPTION_PREFETCH_MODE FALSE
222
223/* Default FCH controls to off */
224#define FCH_SUPPORT FALSE
225
226/* Enable all private controls based on socket/family enables */
227
228#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
229 #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
230 #undef FCH_SUPPORT
231 #define FCH_SUPPORT TRUE
232 #undef OPTION_FAMILY16H_KB
233 #define OPTION_FAMILY16H_KB TRUE
234 #undef OPTION_MEMCTLR_KB
235 #define OPTION_MEMCTLR_KB TRUE
236 #undef OPTION_HW_WRITE_LEV_TRAINING
237 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
238 #undef OPTION_CONTINOUS_PATTERN_GENERATION
239 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
240 #undef OPTION_HW_DQS_REC_EN_TRAINING
241 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
242 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
243 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
244 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
245 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
246 #undef OPTION_RDDQS_2D_TRAINING
247 #define OPTION_RDDQS_2D_TRAINING TRUE
248 #undef OPTION_MAX_RD_LAT_TRAINING
249 #define OPTION_MAX_RD_LAT_TRAINING TRUE
250 #undef OPTION_SW_DRAM_INIT
251 #define OPTION_SW_DRAM_INIT TRUE
252 #undef OPTION_S3_MEM_SUPPORT
253 #define OPTION_S3_MEM_SUPPORT TRUE
254 #undef OPTION_GFX_RECOVERY
255 #define OPTION_GFX_RECOVERY TRUE
256 #undef OPTION_CPU_CORELEVELING
257 #define OPTION_CPU_CORELEVELING TRUE
258 #undef OPTION_C6_STATE
259 #define OPTION_C6_STATE TRUE
260 #undef OPTION_IO_CSTATE
261 #define OPTION_IO_CSTATE TRUE
262 #undef OPTION_CPU_CFOH
263 #define OPTION_CPU_CFOH TRUE
264 #undef OPTION_CPU_APM
265 #define OPTION_CPU_APM TRUE
266 #undef OPTION_CPB
267 #define OPTION_CPB TRUE
268 #undef OPTION_CPU_HTC
269 #define OPTION_CPU_HTC TRUE
270 #undef OPTION_CPU_PSI
271 #define OPTION_CPU_PSI TRUE
272 #undef OPTION_CDIT
273 #define OPTION_CDIT TRUE
274 #undef OPTION_CRAT
275 #define OPTION_CRAT TRUE
276 #undef OPTION_CPU_SCS
277 #define OPTION_CPU_SCS TRUE
278 #undef OPTION_S3SCRIPT
279 #define OPTION_S3SCRIPT TRUE
280 ///@todo
281 //#undef OPTION_PREFETCH_MODE
282 //#define OPTION_PREFETCH_MODE TRUE
283 #undef OPTION_UDIMMS
284 #define OPTION_UDIMMS TRUE
285 #undef OPTION_SODIMMS
286 #define OPTION_SODIMMS TRUE
287 #undef OPTION_DDR3
288 #define OPTION_DDR3 TRUE
289 #undef OPTION_ECC
290 #define OPTION_ECC TRUE
291 #undef OPTION_BANK_INTERLEAVE
292 #define OPTION_BANK_INTERLEAVE TRUE
293 #undef OPTION_DCT_INTERLEAVE
294 #define OPTION_DCT_INTERLEAVE TRUE
295 #undef OPTION_MEM_RESTORE
296 #define OPTION_MEM_RESTORE TRUE
297 #undef OPTION_DIMM_EXCLUDE
298 #define OPTION_DIMM_EXCLUDE TRUE
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]299 #ifndef OPTION_MICROSERVER
300 #define OPTION_MICROSERVER FALSE
301 #endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]302 #endif
303#endif
304
305
306#if (OPTION_FAMILY16H_KB == TRUE)
307 #undef GNB_SUPPORT
308 #define GNB_SUPPORT TRUE
309#endif
310
311#define OPTION_ACPI_PSTATES TRUE
312#define OPTION_WHEA TRUE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]313#define OPTION_DMI FALSE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]314#define OPTION_EARLY_SAMPLES FALSE
315#define CFG_ACPI_PSTATES_PPC TRUE
316#define CFG_ACPI_PSTATES_PCT TRUE
317#define CFG_ACPI_PSTATES_PSD TRUE
318#define CFG_ACPI_PSTATES_PSS TRUE
319#define CFG_ACPI_PSTATES_XPSS TRUE
320#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]321#define CFG_VRM_HIGH_SPEED_ENABLE TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]322#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
323#define OPTION_ALIB TRUE
324/*---------------------------------------------------------------------------
325 * Processing the options: Second, process the user's selections
326 *--------------------------------------------------------------------------*/
327#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
328 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
329 #undef OPTION_DDR3
330 #define OPTION_DDR3 FALSE
331 #endif
332#endif
333#if ((OPTION_DDR3 == FALSE))
334 #error BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
335#endif
336#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
337 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
338 #undef OPTION_MULTISOCKET
339 #define OPTION_MULTISOCKET FALSE
340 #endif
341#endif
342#ifdef BLDOPT_REMOVE_ECC_SUPPORT
343 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
344 #undef OPTION_ECC
345 #define OPTION_ECC FALSE
346 #endif
347#endif
348#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
349 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
350 #undef OPTION_UDIMMS
351 #define OPTION_UDIMMS FALSE
352 #endif
353#endif
354#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
355 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
356 #undef OPTION_RDIMMS
357 #define OPTION_RDIMMS FALSE
358 #endif
359#endif
360#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
361 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
362 #undef OPTION_SODIMMS
363 #define OPTION_SODIMMS FALSE
364 #endif
365#endif
366#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
367 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
368 #undef OPTION_LRDIMMS
369 #define OPTION_LRDIMMS FALSE
370 #endif
371#endif
372#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
373 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
374 #undef OPTION_BANK_INTERLEAVE
375 #define OPTION_BANK_INTERLEAVE FALSE
376 #endif
377#endif
378#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
379 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
380 #undef OPTION_DCT_INTERLEAVE
381 #define OPTION_DCT_INTERLEAVE FALSE
382 #endif
383#endif
384#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
385 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
386 #undef OPTION_NODE_INTERLEAVE
387 #define OPTION_NODE_INTERLEAVE FALSE
388 #endif
389#endif
390#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
391 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
392 #undef OPTION_PARALLEL_TRAINING
393 #define OPTION_PARALLEL_TRAINING FALSE
394 #endif
395#endif
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]396/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
397#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
398 #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]399 #undef OPTION_ONLINE_SPARE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]400 #define OPTION_ONLINE_SPARE TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]401 #endif
402#endif
403#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
404 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
405 #undef OPTION_MEM_RESTORE
406 #define OPTION_MEM_RESTORE FALSE
407 #endif
408#endif
409#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
410 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
411 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
412 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
413 #endif
414#endif
415#ifdef BLDOPT_REMOVE_ACPI_PSTATES
416 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
417 #undef OPTION_ACPI_PSTATES
418 #define OPTION_ACPI_PSTATES FALSE
419 #endif
420#endif
421#ifdef BLDOPT_REMOVE_CRAT
422 #if BLDOPT_REMOVE_CRAT == TRUE
423 #undef OPTION_CRAT
424 #define OPTION_CRAT FALSE
425 #endif
426#endif
427#ifdef BLDOPT_REMOVE_CDIT
428 #if BLDOPT_REMOVE_CDIT == TRUE
429 #undef OPTION_CDIT
430 #define OPTION_CDIT FALSE
431 #endif
432#endif
433#ifdef BLDOPT_REMOVE_SRAT
434 #if BLDOPT_REMOVE_SRAT == TRUE
435 #undef OPTION_SRAT
436 #define OPTION_SRAT FALSE
437 #endif
438#endif
439#ifdef BLDOPT_REMOVE_SLIT
440 #if BLDOPT_REMOVE_SLIT == TRUE
441 #undef OPTION_SLIT
442 #define OPTION_SLIT FALSE
443 #endif
444#endif
445#ifdef BLDOPT_REMOVE_WHEA
446 #if BLDOPT_REMOVE_WHEA == TRUE
447 #undef OPTION_WHEA
448 #define OPTION_WHEA FALSE
449 #endif
450#endif
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]451/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
452#ifdef BLDOPT_ENABLE_DMI
453 #if BLDOPT_ENABLE_DMI == TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]454 #undef OPTION_DMI
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]455 #define OPTION_DMI TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]456 #endif
457#endif
458#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
459 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
460 #undef OPTION_ADDR_TO_CS_TRANSLATOR
461 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
462 #endif
463#endif
464#ifdef BLDOPT_REMOVE_AMP_SUPPORT
465 #if BLDOPT_REMOVE_AMP_SUPPORT == TRUE
466 #undef OPTION_AMP
467 #define OPTION_AMP FALSE
468 #endif
469#endif
470
471#ifdef OPTION_RDDQS_2D_TRAINING
472 #if OPTION_RDDQS_2D_TRAINING == FALSE
473 #undef OPTION_DATA_EYE
474 #define OPTION_DATA_EYE FALSE
475 #else
476 #ifdef BLDOPT_REMOVE_DATA_EYE
477 #if BLDOPT_REMOVE_DATA_EYE == TRUE
478 #undef OPTION_DATA_EYE
479 #define OPTION_DATA_EYE FALSE
480 #endif
481 #endif
482 #endif
483#else
484 #undef OPTION_DATA_EYE
485 #define OPTION_DATA_EYE FALSE
486#endif
487
488#ifdef BLDOPT_REMOVE_HT_ASSIST
489 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
490 #undef OPTION_HT_ASSIST
491 #define OPTION_HT_ASSIST FALSE
492 #endif
493#endif
494
495#ifdef BLDOPT_REMOVE_ATM_MODE
496 #if BLDOPT_REMOVE_ATM_MODE == TRUE
497 #undef OPTION_ATM_MODE
498 #define OPTION_ATM_MODE FALSE
499 #endif
500#endif
501
502#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
503 #if BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
504 #undef OPTION_NBR_CACHE
505 #define OPTION_NBR_CACHE FALSE
506 #endif
507#endif
508
509#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
510 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
511 #undef OPTION_MSG_BASED_C1E
512 #define OPTION_MSG_BASED_C1E FALSE
513 #endif
514#endif
515
516#ifdef BLDOPT_REMOVE_C6_STATE
517 #if BLDOPT_REMOVE_C6_STATE == TRUE
518 #undef OPTION_C6_STATE
519 #define OPTION_C6_STATE FALSE
520 #endif
521#endif
522
523#ifdef BLDOPT_REMOVE_GFX_RECOVERY
524 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
525 #undef OPTION_GFX_RECOVERY
526 #define OPTION_GFX_RECOVERY FALSE
527 #endif
528#endif
529
530#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
531 #if BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
532 #undef OPTION_RDDQS_2D_TRAINING
533 #define OPTION_RDDQS_2D_TRAINING FALSE
534 #endif
535#endif
536
537#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
538 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
539 #undef CFG_ACPI_PSTATES_PPC
540 #define CFG_ACPI_PSTATES_PPC FALSE
541 #endif
542#endif
543
544#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
545 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
546 #undef CFG_ACPI_PSTATES_PCT
547 #define CFG_ACPI_PSTATES_PCT FALSE
548 #endif
549#endif
550
551#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
552 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
553 #undef CFG_ACPI_PSTATES_PSD
554 #define CFG_ACPI_PSTATES_PSD FALSE
555 #endif
556#endif
557
558#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
559 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
560 #undef CFG_ACPI_PSTATES_PSS
561 #define CFG_ACPI_PSTATES_PSS FALSE
562 #endif
563#endif
564
565#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
566 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
567 #undef CFG_ACPI_PSTATES_XPSS
568 #define CFG_ACPI_PSTATES_XPSS FALSE
569 #endif
570#endif
571
572#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
573 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
574 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
575 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
576 #endif
577#endif
578
579#ifdef BLDOPT_REMOVE_AGGRESSOR
580 #if BLDOPT_REMOVE_AGGRESSOR == TRUE
581 #undef OPTION_AGGRESSOR
582 #define OPTION_AGGRESSOR FALSE
583 #endif
584#endif
585
586#ifdef BLDCFG_PSTATE_HPC_MODE
587 #if BLDCFG_PSTATE_HPC_MODE == TRUE
588 #undef OPTION_CPU_PSTATE_HPC_MODE
589 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
590 #endif
591#endif
592
593#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
594 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
595 #undef CFG_ACPI_PSTATE_PSD_INDPX
596 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
597 #endif
598#endif
599
600#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
601 #define CFG_ACPI_PSTATES_PSD_POLICY (BLDCFG_ACPI_PSTATES_PSD_POLICY)
602#else
603 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
604#endif
605
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]606/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
607#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
608 #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]609 #undef CFG_VRM_HIGH_SPEED_ENABLE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]610 #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]611 #endif
612#endif
613
614#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
615 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
616 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
617 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
618 #endif
619#endif
620
621#ifdef BLDCFG_STARTING_BUSNUM
622 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
623#else
624 #define CFG_STARTING_BUSNUM (0)
625#endif
626
627#ifdef BLDCFG_AMD_PLATFORM_TYPE
628 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
629#else
630 #define CFG_AMD_PLATFORM_TYPE 0
631#endif
632
633CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
634
635#ifdef BLDCFG_MAXIMUM_BUSNUM
636 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
637#else
638 #define CFG_MAXIMUM_BUSNUM (0xF8)
639#endif
640
641#ifdef BLDCFG_ALLOCATED_BUSNUM
642 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
643#else
644 #define CFG_ALLOCATED_BUSNUM (0x20)
645#endif
646
647#ifdef BLDCFG_BUID_SWAP_LIST
648 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
649#else
650 #define CFG_BUID_SWAP_LIST (NULL)
651#endif
652
653#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
654 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
655#else
656 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
657#endif
658
659#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
660 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
661#else
662 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
663#endif
664
665#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
666 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
667#else
668 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
669#endif
670
671#ifdef BLDCFG_BUS_NUMBERS_LIST
672 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
673#else
674 #define CFG_BUS_NUMBERS_LIST (NULL)
675#endif
676
677#ifdef BLDCFG_IGNORE_LINK_LIST
678 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
679#else
680 #define CFG_IGNORE_LINK_LIST (NULL)
681#endif
682
683#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
684 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
685#else
686 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
687#endif
688
689#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
690 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
691#else
692 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
693#endif
694
695#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
696 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
697#else
698 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
699#endif
700
701#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
702 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
703#else
704 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
705#endif
706
707#ifdef BLDCFG_USE_HT_ASSIST
708 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
709#else
710 #define CFG_USE_HT_ASSIST (TRUE)
711#endif
712
713#ifdef BLDCFG_USE_ATM_MODE
714 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
715#else
716 #define CFG_USE_ATM_MODE (TRUE)
717#endif
718
719#ifdef BLDCFG_USE_NEIGHBOR_CACHE
720 #define CFG_USE_NBR_CACHE (BLDCFG_USE_NEIGHBOR_CACHE)
721#else
722 #define CFG_USE_NBR_CACHE (TRUE)
723#endif
724
725#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
726 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
727#else
728 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
729#endif
730
731#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
732 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
733#else
734 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
735#endif
736
737#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
738 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
739#else
740 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
741#endif
742
743#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
744 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
745#else
746 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
747#endif
748
749#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
750 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
751#else
752 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
753#endif
754
755#ifdef BLDCFG_VRM_CURRENT_LIMIT
756 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
757#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]758 #define CFG_VRM_CURRENT_LIMIT 15000
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]759#endif
760
761#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
762 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
763#else
764 #define CFG_VRM_LOW_POWER_THRESHOLD 0
765#endif
766
767#ifdef BLDCFG_VRM_SLEW_RATE
768 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
769#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]770 #define CFG_VRM_SLEW_RATE (10000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]771#endif
772
773#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
774 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
775#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]776 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (21000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]777#endif
778
779#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
780 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
781#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]782 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (17000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]783#endif
784
785#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
786 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
787#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]788 #define CFG_VRM_SVI_OCP_LEVEL CFG_VRM_MAXIMUM_CURRENT_LIMIT
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]789#endif
790
791#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
792 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
793#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]794 #define CFG_VRM_NB_SVI_OCP_LEVEL CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]795#endif
796
797#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
798 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
799#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]800 #define CFG_VRM_NB_CURRENT_LIMIT (13000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]801#endif
802
803#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
804 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
805#else
806 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
807#endif
808
809#ifdef BLDCFG_VRM_NB_SLEW_RATE
810 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
811#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]812 #define CFG_VRM_NB_SLEW_RATE CFG_VRM_SLEW_RATE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]813#endif
814
815#ifdef BLDCFG_PLAT_NUM_IO_APICS
816 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
817#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]818 #define CFG_PLAT_NUM_IO_APICS 3
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]819#endif
820
821#ifdef BLDCFG_MEM_INIT_PSTATE
822 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
823#else
824 #define CFG_MEM_INIT_PSTATE 0
825#endif
826
827#ifdef BLDCFG_PLATFORM_C1E_MODE
828 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
829#else
830 #define CFG_C1E_MODE C1eModeDisabled
831#endif
832
833#ifdef BLDCFG_PLATFORM_C1E_OPDATA
834 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
835#else
836 #define CFG_C1E_OPDATA 0
837#endif
838
839#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
840 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
841#else
842 #define CFG_C1E_OPDATA1 0
843#endif
844
845#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
846 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
847#else
848 #define CFG_C1E_OPDATA2 0
849#endif
850
851#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
852 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
853#else
854 #define CFG_C1E_OPDATA3 0
855#endif
856
857#ifdef BLDCFG_PLATFORM_CSTATE_MODE
858 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
859#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]860 #define CFG_CSTATE_MODE CStateModeDisabled
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]861#endif
862
863#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
864 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
865#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]866 #define CFG_CSTATE_OPDATA 0x1770
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]867#endif
868
869#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
870 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
871#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]872 #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]873#endif
874
875#ifdef BLDCFG_PLATFORM_CPB_MODE
876 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
877#else
878 #define CFG_CPB_MODE CpbModeAuto
879#endif
880
881#ifdef BLDCFG_CORE_LEVELING_MODE
882 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
883#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]884 #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]885#endif
886
887#ifdef BLDCFG_AMD_TDP_LIMIT
888 #define CFG_AMD_POWER_CEILING BLDCFG_AMD_TDP_LIMIT
889#else
890 #define CFG_AMD_POWER_CEILING 0
891#endif
892
893#ifdef BLDCFG_HEAP_DRAM_ADDRESS
894 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
895#else
896 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
897#endif
898
899#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
900 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
901#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]902 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]903#endif
904
905#ifdef BLDCFG_MEMORY_MODE_UNGANGED
906 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
907#else
908 #define CFG_MEMORY_MODE_UNGANGED TRUE
909#endif
910
911#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
912 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
913#else
914 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
915#endif
916
917#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
918 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
919#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]920 #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]921#endif
922
923#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
924 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
925#else
926 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
927#endif
928
929#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
930 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
931#else
932 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
933#endif
934
935#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
936 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
937#else
938 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
939#endif
940
941#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
942 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
943#else
944 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
945#endif
946
947#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
948 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
949#else
950 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
951#endif
952
953#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
954 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
955#else
956 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
957#endif
958
959#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
960 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
961#else
962 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
963#endif
964
965#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
966 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
967#else
968 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
969#endif
970
971#ifdef BLDCFG_MEMORY_POWER_DOWN
972 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
973#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]974 #define CFG_MEMORY_POWER_DOWN TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]975#endif
976
977#ifdef BLDCFG_POWER_DOWN_MODE
978 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
979#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]980 #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]981#endif
982
983#ifdef BLDCFG_ONLINE_SPARE
984 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
985#else
986 #define CFG_ONLINE_SPARE FALSE
987#endif
988
989#ifdef BLDCFG_MEMORY_PARITY_ENABLE
990 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
991#else
992 #define CFG_MEMORY_PARITY_ENABLE FALSE
993#endif
994
995#ifdef BLDCFG_BANK_SWIZZLE
996 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
997#else
998 #define CFG_BANK_SWIZZLE TRUE
999#endif
1000
1001#ifdef BLDCFG_TIMING_MODE_SELECT
1002 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1003#else
1004 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1005#endif
1006
1007#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1008 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1009#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]1010 #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1011#endif
1012
1013#ifdef BLDCFG_DQS_TRAINING_CONTROL
1014 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1015#else
1016 #define CFG_DQS_TRAINING_CONTROL TRUE
1017#endif
1018
1019#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1020 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1021#else
1022 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1023#endif
1024
1025#ifdef BLDCFG_USE_BURST_MODE
1026 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1027#else
1028 #define CFG_USE_BURST_MODE FALSE
1029#endif
1030
1031#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1032 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1033#else
1034 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1035#endif
1036
1037#ifdef BLDCFG_ENABLE_ECC_FEATURE
1038 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1039#else
1040 #define CFG_ENABLE_ECC_FEATURE TRUE
1041#endif
1042
1043#ifdef BLDCFG_ECC_REDIRECTION
1044 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1045#else
1046 #define CFG_ECC_REDIRECTION FALSE
1047#endif
1048
1049#ifdef BLDCFG_SCRUB_DRAM_RATE
1050 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1051#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1052 #define CFG_SCRUB_DRAM_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1053#endif
1054
1055#ifdef BLDCFG_SCRUB_L2_RATE
1056 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1057#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1058 #define CFG_SCRUB_L2_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1059#endif
1060
1061#ifdef BLDCFG_SCRUB_L3_RATE
1062 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1063#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1064 #define CFG_SCRUB_L3_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1065#endif
1066
1067#ifdef BLDCFG_SCRUB_IC_RATE
1068 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1069#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1070 #define CFG_SCRUB_IC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1071#endif
1072
1073#ifdef BLDCFG_SCRUB_DC_RATE
1074 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1075#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1076 #define CFG_SCRUB_DC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1077#endif
1078
1079#ifdef BLDCFG_ECC_SYNC_FLOOD
1080 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1081#else
1082 #define CFG_ECC_SYNC_FLOOD TRUE
1083#endif
1084
1085#ifdef BLDCFG_ECC_SYMBOL_SIZE
1086 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1087#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]1088 #define CFG_ECC_SYMBOL_SIZE 4
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1089#endif
1090
1091#ifdef BLDCFG_1GB_ALIGN
1092 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1093#else
1094 #define CFG_1GB_ALIGN FALSE
1095#endif
1096
1097#ifdef BLDCFG_UMA_ALLOCATION_MODE
1098 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1099#else
1100 #define CFG_UMA_MODE UMA_AUTO
1101#endif
1102
1103#ifdef BLDCFG_FORCE_TRAINING_MODE
1104 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1105#else
1106 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1107#endif
1108
1109#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1110 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1111#else
1112 #define CFG_UMA_SIZE 0
1113#endif
1114
1115#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1116 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1117#else
1118 #define CFG_UMA_ABOVE4G FALSE
1119#endif
1120
1121#ifdef BLDCFG_UMA_ALIGNMENT
1122 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1123#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]1124 #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1125#endif
1126
1127#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1128 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1129#else
1130 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG DDR3_TECHNOLOGY
1131#endif
1132
1133#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1134 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1135#else
1136 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1137#endif
1138
1139#ifdef BLDCFG_S3_LATE_RESTORE
1140 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1141#else
1142 #define CFG_S3_LATE_RESTORE TRUE
1143#endif
1144
1145#ifdef BLDCFG_USE_32_BYTE_REFRESH
1146 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1147#else
1148 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1149#endif
1150
1151#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1152 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1153#else
1154 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1155#endif
1156
1157#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1158 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1159#else
1160 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1161#endif
1162
1163#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1164 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1165#else
1166 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1167#endif
1168
1169#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1170 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1171#else
1172 #define CFG_GNB_HD_AUDIO TRUE
1173#endif
1174
1175#ifdef BLDCFG_CFG_ABM_SUPPORT
1176 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1177#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]1178 #define CFG_ABM_SUPPORT TRUE
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1179#endif
1180
1181#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1182 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1183#else
1184 #define CFG_DYNAMIC_REFRESH_RATE 0
1185#endif
1186
1187#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1188 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1189#else
1190 #define CFG_LCD_BACK_LIGHT_CONTROL 200
1191#endif
1192
1193#ifdef BLDCFG_STEREO_3D_PINOUT
1194 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1195#else
1196 #define CFG_GNB_STEREO_3D_PINOUT 0
1197#endif
1198
1199#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1200 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1201#else
1202 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1203#endif
1204
1205// Define pin configuration for SYNCFLOOD
1206// Default to FALSE (Use pin as SYNCFLOOD)
1207#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
1208 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
1209#else
1210 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
1211#endif
1212
1213#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1214 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1215#else
1216 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
1217#endif
1218
1219#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1220 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1221#else
1222 #define CFG_GNB_IGPU_SSID 0
1223#endif
1224
1225#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1226 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1227#else
1228 #define CFG_GNB_HDAUDIO_SSID 0
1229#endif
1230
1231#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1232 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1233#else
1234 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
1235#endif
1236
1237#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1238 #define CFG_GNB_PCIE_SSID BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1239#else
1240 #define CFG_GNB_PCIE_SSID 0x12341022ul
1241#endif
1242
1243#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1244 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1245#else
1246 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1247#endif
1248
1249#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1250 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1251#else
1252 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1253#endif
1254
1255#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1256 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1257#else
1258 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1259#endif
1260
1261#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1262 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1263#else
1264 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
1265#endif
1266
1267#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1268 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1269#else
1270 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1271#endif
1272
1273#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1274 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1275 #undef OPTION_EARLY_SAMPLES
1276 #define OPTION_EARLY_SAMPLES FALSE
1277 #else
1278 #undef OPTION_EARLY_SAMPLES
1279 #define OPTION_EARLY_SAMPLES TRUE
1280 #endif
1281#endif
1282
1283#ifdef BLDOPT_REMOVE_ALIB
1284 #if BLDOPT_REMOVE_ALIB == TRUE
1285 #undef OPTION_ALIB
1286 #define OPTION_ALIB FALSE
1287 #else
1288 #undef OPTION_ALIB
1289 #define OPTION_ALIB TRUE
1290 #endif
1291#endif
1292
1293#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1294 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1295 #undef FCH_SUPPORT
1296 #define FCH_SUPPORT FALSE
1297 #endif
1298#endif
1299
1300#ifdef BLDCFG_IOMMU_SUPPORT
1301 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1302#else
1303 #define CFG_IOMMU_SUPPORT TRUE
1304#endif
1305
1306#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1307 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1308#else
1309 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1310#endif
1311
1312#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1313 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1314#else
1315 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1316#endif
1317
1318#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1319 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1320#else
1321 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1322#endif
1323
1324#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1325 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1326#else
1327 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1328#endif
1329
1330#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1331 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1332#else
1333 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1334#endif
1335
1336#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1337 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1338#else
1339 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1340#endif
1341
1342#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1343 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1344#else
1345 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1346#endif
1347
1348#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1349 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1350#else
1351 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1352#endif
1353
1354#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1355 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1356#else
1357 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1358#endif
1359
1360
1361// BLDCFG_LVDS_24BBP_PANEL_MODE
1362// This specifies the LVDS 24 BBP mode.
1363// 0 - Use LDI mode (default).
1364// 1 - Use FPDI mode.
1365#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1366 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1367#else
1368 #define CFG_LVDS_24BBP_PANEL_MODE 0
1369#endif
1370
1371#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1372 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1373#else
1374 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1375#endif
1376
1377#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1378 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1379#else
1380 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1381#endif
1382
1383#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1384 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1385#else
1386 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1387#endif
1388
1389#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1390 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1391#else
1392 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1393#endif
1394
1395#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1396 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1397#else
1398 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1399#endif
1400
1401#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1402 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1403#else
1404 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
1405#endif
1406
1407#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1408 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1409#else
1410 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
1411#endif
1412
1413#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1414 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1415#else
1416 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
1417#endif
1418
1419#ifdef BLDCFG_DP_FIXED_VOLT_SWING
1420 #define CFG_DP_FIXED_VOLT_SWING BLDCFG_DP_FIXED_VOLT_SWING
1421#else
1422 #define CFG_DP_FIXED_VOLT_SWING 0
1423#endif
1424
1425#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1426 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1427#else
1428 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1429#endif
1430
1431#ifdef BLDCFG_NB_PSTATES_SUPPORTED
1432 #define CFG_NB_PSTATES_SUPPORTED (BLDCFG_NB_PSTATES_SUPPORTED)
1433#else
1434 #define CFG_NB_PSTATES_SUPPORTED (TRUE)
1435#endif
1436
1437#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
1438 #define CFG_HTC_TEMPERATURE_LIMIT (BLDCFG_HTC_TEMPERATURE_LIMIT)
1439#else
1440 #define CFG_HTC_TEMPERATURE_LIMIT (0)
1441#endif
1442
1443#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
1444 #define CFG_LHTC_TEMPERATURE_LIMIT (BLDCFG_LHTC_TEMPERATURE_LIMIT)
1445#else
1446 #define CFG_LHTC_TEMPERATURE_LIMIT (0)
1447#endif
1448
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1449#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1450
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1451#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1452
1453#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1454 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1455#else
Angel Pons64829162020-05-21 15:29:17 +0200[diff] [blame]1456 #define CFG_AP_MTRR_SETTINGS_LIST (KabiniApMtrrSettingsList)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1457#endif
1458
1459#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
1460 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
1461#else
1462 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
1463#endif
1464
1465#ifdef BLDCFG_HYBRID_BOOST_ENABLE
1466 #define CFG_HYBRID_BOOST_ENABLE BLDCFG_HYBRID_BOOST_ENABLE
1467#else
1468 #define CFG_HYBRID_BOOST_ENABLE TRUE
1469#endif
1470
1471#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
1472 #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
1473#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]1474 #define CFG_GNB_IOAPIC_ADDRESS 0xFEC20000
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1475#endif
1476
1477#ifdef BLDCFG_GNB_IOMMU_ADDRESS
1478 #define CFG_GNB_IOMMU_ADDRESS BLDCFG_GNB_IOMMU_ADDRESS
1479#else
1480 #define CFG_GNB_IOMMU_ADDRESS NULL
1481#endif
1482
1483#ifdef BLDCFG_ENABLE_DATA_EYE
1484 #define CFG_ENABLE_DATA_EYE BLDCFG_ENABLE_DATA_EYE
1485#else
1486 #define CFG_ENABLE_DATA_EYE TRUE
1487#endif
1488
1489#ifdef BLDCFG_ACPI_SET_OEM_ID
1490 #define CFG_ACPI_SET_OEM_ID BLDCFG_ACPI_SET_OEM_ID
1491#else
1492 #define CFG_ACPI_SET_OEM_ID 'A','M','D',' ',' ',' '
1493#endif
1494
1495#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
1496 #define CFG_ACPI_SET_OEM_TABLE_ID BLDCFG_ACPI_SET_OEM_TABLE_ID
1497#else
1498 #define CFG_ACPI_SET_OEM_TABLE_ID 'A','G','E','S','A',' ',' ',' '
1499#endif
1500
1501#ifdef BLDCFG_DOCKED_TDP_HEADROOM
1502 #define CFG_DOCKED_TDP_HEADROOM BLDCFG_DOCKED_TDP_HEADROOM
1503#else
1504 #define CFG_DOCKED_TDP_HEADROOM TRUE
1505#endif
1506
1507#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1508 #define CFG_DRAM_DOUBLE_REFRESH_RATE BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1509#else
1510 #define CFG_DRAM_DOUBLE_REFRESH_RATE FALSE
1511#endif
1512
1513/*---------------------------------------------------------------------------
1514 * Processing the options: Third, perform the option cross checks
1515 *--------------------------------------------------------------------------*/
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1516// Check that deprecated options are not used
1517#ifdef BLDCFG_PCI_MMIO_BASE
1518 #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use!
1519#endif
1520#ifdef BLDCFG_PCI_MMIO_SIZE
1521 #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use!
1522#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1523// Assure that at least one type of memory support is included
1524#if OPTION_UDIMMS == FALSE
1525 #if OPTION_RDIMMS == FALSE
1526 #if OPTION_SODIMMS == FALSE
1527 #if OPTION_LRDIMMS == FALSE
1528 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1529 #endif
1530 #endif
1531 #endif
1532#endif
1533// Ensure at least one dimm type is capable
1534#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1535 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1536 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1537 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1538 #error BLDCFG: No dimm type is capable
1539 #endif
1540 #endif
1541 #endif
1542#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1543// Turn off multi-socket based features if only one node...
1544#if OPTION_MULTISOCKET == FALSE
1545 #undef OPTION_PARALLEL_TRAINING
1546 #define OPTION_PARALLEL_TRAINING FALSE
1547 #undef OPTION_NODE_INTERLEAVE
1548 #define OPTION_NODE_INTERLEAVE FALSE
1549#endif
1550// Ensure the frequency limit is valid
1551#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
1552 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
1553 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
1554 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
1555 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
1556 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
1557 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
1558 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
1559 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
1560 #error BLDCFG: Unsupported memory bus frequency
1561 #endif
1562 #endif
1563 #endif
1564 #endif
1565 #endif
1566 #endif
1567 #endif
1568 #endif
1569#endif
1570// Ensure timing mode is valid
1571#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1572 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1573 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1574 #error BLDCFG: Invalid timing mode is set
1575 #endif
1576 #endif
1577#endif
1578// Ensure the scrub rate is valid
1579#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1580 #error BLDCFG: Unsupported dram scrub rate set
1581#endif
1582#if CFG_SCRUB_L2_RATE > 0x16
1583 #error BLDCFG: Unsupported L2 scrubber rate set
1584#endif
1585#if CFG_SCRUB_L3_RATE > 0x16
1586 #error BLDCFG: unsupported L3 scrubber rate set
1587#endif
1588#if CFG_SCRUB_IC_RATE > 0x16
1589 #error BLDCFG: Unsupported Instruction cache scrub rate set
1590#endif
1591#if CFG_SCRUB_DC_RATE > 0x16
1592 #error BLDCFG: Unsupported Dcache scrub rate set
1593#endif
1594// Ensure Quad rank dimm type is valid
1595#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1596 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1597 #error BLDCFG: Invalid quad rank dimm type set
1598 #endif
1599#endif
1600// Ensure ECC symbol size is valid
1601#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1602 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1603 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1604 #error BLDCFG: Invalid Ecc symbol size set
1605 #endif
1606 #endif
1607#endif
1608// Ensure power down mode is valid
1609#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1610 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1611 #if AGESA_ENTRY_INIT_POST == TRUE
1612 #error BLDCFG: Invalid power down mode set
1613 #endif
1614 #endif
1615#endif
1616
1617// Ensure P-state dependence settings do not conflict
1618#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1619 #error BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
1620#endif
1621
1622#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
1623 #error BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
1624#endif
1625
1626#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
1627 #error BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
1628#endif
1629
1630
1631
1632/*****************************************************************************
1633 *
1634 * Process the option logic, setting local control variables
1635 *
1636 ****************************************************************************/
1637#if OPTION_ACPI_PSTATES == TRUE
1638 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1639 #define OPTFCN_GATHER_DATA PStateGatherData
1640 #if OPTION_MULTISOCKET == TRUE
1641 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1642 #else
1643 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1644 #endif
1645#else
1646 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1647 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1648 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1649#endif
1650
1651// Consolidate P-state dependence setings
1652#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1653 #undef CFG_ACPI_PSTATES_PSD_POLICY
1654 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyIndependent
1655#endif
1656
1657/*****************************************************************************
1658 *
1659 * Include the structure definitions for the defaults table structures
1660 *
1661 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1662#include <CommonReturns.h>
1663#include <agesa-entry-cfg.h>
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1664#include "Options.h"
1665#include "OptionCpuFamiliesInstall.h"
1666#include "OptionsHt.h"
1667#include "OptionHtInstall.h"
1668#include "OptionMemory.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1669#include "OptionMemoryInstall.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1670#include "OptionCpuFeaturesInstall.h"
1671#include "OptionDmi.h"
1672#include "OptionDmiInstall.h"
1673#include "OptionPstate.h"
1674#include "OptionPstateInstall.h"
1675#include "OptionWhea.h"
1676#include "OptionWheaInstall.h"
1677#include "OptionCrat.h"
1678#include "OptionCratInstall.h"
1679#include "OptionCdit.h"
1680#include "OptionCditInstall.h"
1681#include "OptionSrat.h"
1682#include "OptionSratInstall.h"
1683#include "OptionSlit.h"
1684#include "OptionSlitInstall.h"
1685#include "OptionMultiSocket.h"
1686#include "OptionMultiSocketInstall.h"
1687#include "OptionIdsInstall.h"
1688#include "OptionGfxRecovery.h"
1689#include "OptionGfxRecoveryInstall.h"
1690#include "OptionGnb.h"
1691#include "OptionGnbInstall.h"
1692#include "OptionS3ScriptInstall.h"
1693#include "OptionFchInstall.h"
1694#include "OptionMmioMapInstall.h"
1695#include "OptionPrefetchModeInstall.h"
1696
1697
1698/*****************************************************************************
1699 *
1700 * Generate the output structures (defaults tables)
1701 *
1702 ****************************************************************************/
1703
1704FCH_PLATFORM_POLICY FchUserOptions = {
1705 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
1706 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
1707 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
1708 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
1709 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
1710 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
1711 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
1712 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
1713 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
1714 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
1715 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
1716 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
1717 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
1718 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
1719 0x780D1022ul,
1720 CFG_SMBUS_SSID, // CfgSmbusSsid
1721 CFG_IDE_SSID, // CfgIdeSsid
1722 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
1723 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
1724 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
1725 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
1726 CFG_EHCI_SSID, // CfgEhcidSsid
1727 CFG_OHCI_SSID, // CfgOhcidSsid
1728 CFG_LPC_SSID, // CfgLpcSsid
1729 CFG_SD_SSID, // CfgSdSsid
1730 CFG_XHCI_SSID, // CfgXhciSsid
1731 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
1732 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
1733 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
1734 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
1735 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
1736 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
1737 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
1738 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
1739 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
1740 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
1741 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
1742
1743 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
1744 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
1745 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
1746 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
1747 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]1748 CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl
1749 CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1750};
1751
1752BUILD_OPT_CFG UserOptions = {
1753 { // AGESA version string
1754 AGESA_CODE_SIGNATURE, // code header Signature
1755 AGESA_PACKAGE_STRING, // 16 character ID
1756 AGESA_VERSION_STRING, // 12 character version string
1757 0 // null string terminator
1758 },
1759 //Build Option Area
1760 OPTION_UDIMMS, //UDIMMS
1761 OPTION_RDIMMS, //RDIMMS
1762 OPTION_LRDIMMS, //LRDIMMS
1763 OPTION_ECC, //ECC
1764 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1765 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1766 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1767 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1768 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1769 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1770 OPTION_MULTISOCKET, //MULTISOCKET
1771 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1772 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
1773 OPTION_CRAT, //CRAT
1774 OPTION_CDIT, //CDIT
1775 OPTION_SRAT, //SRAT
1776 OPTION_SLIT, //SLIT
1777 OPTION_WHEA, //WHEA
1778 OPTION_DMI, //DMI
1779 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1780 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1781
1782 //Build Configuration Area
1783 CFG_PCI_MMIO_BASE,
1784 CFG_PCI_MMIO_SIZE,
1785 {
1786 // CoreVrm
1787 {
1788 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1789 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1790 CFG_VRM_SLEW_RATE, // VrmSlewRate
1791 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1792 CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmMaximumCurrentLimit
1793 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
1794 },
1795 // NbVrm
1796 {
1797 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1798 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1799 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1800 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1801 CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbMaximumCurrentLimit
1802 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
1803 }
1804 },
1805 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1806 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1807 CFG_C1E_MODE, //C1eMode
1808 CFG_C1E_OPDATA, //C1ePlatformData
1809 CFG_C1E_OPDATA1, //C1ePlatformData1
1810 CFG_C1E_OPDATA2, //C1ePlatformData2
1811 CFG_C1E_OPDATA3, //C1ePlatformData3
1812 CFG_CSTATE_MODE, //CStateMode
1813 CFG_CSTATE_OPDATA, //CStatePlatformData
1814 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1815 CFG_CPB_MODE, //CpbMode
1816 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
1817 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1818 {
1819 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1820 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1821 CFG_USE_ATM_MODE, // CfgUseAtmMode
1822 CFG_USE_NBR_CACHE, // CfgUseNbrCache
1823 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1824 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1825 // ADVANCED_PERFORMANCE_PROFILE
1826 {
1827 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
1828 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
1829 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
1830 },
1831 CFG_PLATFORM_POWER_POLICY_MODE, // The platform's power policy mode.
1832 CFG_NB_PSTATES_SUPPORTED // The Nb-Pstates is supported or not
1833 },
1834 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1835 CFG_AMD_PLATFORM_TYPE, // CfgAmdPlatformType
1836 CFG_AMD_POWER_CEILING, // CfgAmdPowerCeiling
1837 CFG_HTC_TEMPERATURE_LIMIT, // CfgHtcTemperatureLimit
1838 CFG_LHTC_TEMPERATURE_LIMIT, // CfgLhtcTemperatureLimit
1839
1840 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1841 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1842 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1843 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1844 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1845 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1846 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1847 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1848 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
1849 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1850 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1851 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1852 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1853 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1854 CFG_ONLINE_SPARE, // CfgOnlineSpare
1855 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1856 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1857 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1858 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1859 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1860 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1861 CFG_USE_BURST_MODE, // CfgUseBurstMode
1862 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1863 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1864 CFG_ECC_REDIRECTION, // CfgEccRedirection
1865 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1866 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1867 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1868 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1869 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1870 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1871 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1872 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1873 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1874 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1875 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1876 CFG_ACPI_PSTATES_PSD_POLICY, // CfgAcpiPstatesPsdPolicy
1877 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1878 CFG_UMA_MODE, // CfgUmaMode
1879 CFG_UMA_SIZE, // CfgUmaSize
1880 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1881 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1882 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1883 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1884 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1885 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1886 CFG_ABM_SUPPORT, // CfgAbmSupport
1887 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1888 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1889 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1890 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1891 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1892 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1893 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1894 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1895 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1896
1897 &FchUserOptions, // FchBldCfg
1898
1899 CFG_IOMMU_SUPPORT, // CfgIommuSupport
1900 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
1901 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
1902 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
1903 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
1904 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
1905 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
1906 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
1907 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
1908 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
1909 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
1910 {{
1911 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1912 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1913 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1914 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1915 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1916 CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl
1917 }},
1918 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
1919 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
1920 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
1921 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
1922 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
1923 CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi
1924 CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy
1925 CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset
1926 CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment
1927 {{
1928 0, // Reserved
1929 CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
1930 0, // Reserved
1931 }},
1932 CFG_DP_FIXED_VOLT_SWING, // CfgDpFixedVoltSwingType
1933 CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG, // CfgDimmTypeUsedInMixedConfig
1934 CFG_HYBRID_BOOST_ENABLE, // CfgHybridBoostEnable
1935 CFG_GNB_IOAPIC_ADDRESS, // CfgGnbIoapicAddress
1936 CFG_ENABLE_DATA_EYE, // CfgDataEyeEn
1937 CFG_DOCKED_TDP_HEADROOM, // CfgDockedTdpHeadroom
1938 CFG_DRAM_DOUBLE_REFRESH_RATE, // CfgDramDoubleRefreshRateEn
1939 0, //reserved...
1940};
1941
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1942CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1943{
1944 IDS_LATE_RUN_AP_TASK
1945 // Get DMI info
1946 CPU_DMI_AP_GET_TYPE4_TYPE7
1947 // Probe filter enable
1948 L3_FEAT_AP_DISABLE_CACHE
1949 L3_FEAT_AP_ENABLE_CACHE
1950 // Cpu Prefetch Mode
1951 CPU_PREFETCH_MODE_AP_TASK
1952 { 0, NULL }
1953};
1954
1955#if AGESA_ENTRY_INIT_EARLY == TRUE
1956 #if IDSOPT_IDS_ENABLED == TRUE
1957 #if IDSOPT_TRACING_ENABLED == TRUE
1958 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1959 CONST CHAR8 *BldOptDebugOutput[] = {
1960 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1961 //Build Option Area
1962 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1963 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1964 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1965 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1966 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1967 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1968 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1969 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1970 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1971 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1972 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1973 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1974 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1975 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1976 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1977 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1978 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1979 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1980
1981 //Build Configuration Area
1982 // CoreVrm
1983 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1984 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1985 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1986 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1987 MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
1988 MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL)
1989 // NbVrm
1990 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1991 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1992 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1993 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1994 MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
1995 MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL)
1996
1997 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1998 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1999 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2000 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2001 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2002 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2003 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
2004 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2005 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2006 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2007 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2008 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2009
2010 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2011 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2012 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2013 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2014 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2015 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2016
2017 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2018
2019 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2020 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2021 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2022 MAKE_DBG_STR (\nPowerCeiling , CFG_AMD_POWER_CEILING),
2023 MAKE_DBG_STR (\nHtcTempLimit , CFG_HTC_TEMPERATURE_LIMIT)
2024 MAKE_DBG_STR (\nLhtcTempLimit , CFG_LHTC_TEMPERATURE_LIMIT)
2025
2026 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2027 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2028 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2029
2030 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2031 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2032 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2033 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2034 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2035 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2036 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2037 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2038 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2039 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2040 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2041
2042 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2043 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2044 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2045 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2046 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2047 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2048 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2049 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2050 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2051
2052 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2053 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2054 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2055 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2056
2057 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2058 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2059 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2060 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2061 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2062 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2063 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2064 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2065 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2066 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2067 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2068
2069 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2070 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2071 MAKE_DBG_STR (\nAcpiPstatesPsdPolicy , CFG_ACPI_PSTATES_PSD_POLICY)
2072
2073 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2074
2075 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2076 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2077 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2078 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2079 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2080 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2081 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2082 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2083 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2084 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2085 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2086 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2087 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2088 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2089 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2090 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2091 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2092 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2093 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2094 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2095 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2096 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2097 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2098 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2099 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2100 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2101 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2102 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2103 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2104 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2105 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2106 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2107 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2108 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2109 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2110 MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
2111 MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY),
2112 MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION),
2113 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
2114 MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
2115 MAKE_DBG_STR (\nCfgDataEyeEn , CFG_ENABLE_DATA_EYE),
2116 MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn , CFG_DRAM_DOUBLE_REFRESH_RATE),
2117 #endif
2118 NULL
2119 };
2120 #endif
2121 #endif
2122#endif
2123
2124// Needed for floating point support, linker expects this symbol to be defined.
2125#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
2126 CONST INT32 _fltused = 0;
2127#endif
2128