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review.coreboot.org / coreboot / 7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 / . / src / vendorcode / amd / agesa / f16kb / Config / PlatformInstall.h
blob: ff5b91c2913963eba1101e4360c2c4651c7996e0 [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45/*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
50
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]51VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
52 //ModuleHeaderSignature
53 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
54 Int32FromChar ('0', '0', '0', '0'),
55 //ModuleIdentifier[8]
56 AGESA_ID,
57 //ModuleVersion[12]
58 AGESA_VERSION_STRING,
59 //ModuleDispatcher
60 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
61 //NextBlock
62 NULL
63};
64
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]65/* Process solution defined socket / family installations
66 *
67 * As part of the release package for each image, define the options below to select the
68 * AGESA processor support included in that image.
69 */
70
71/* Default sockets to off */
72#define OPTION_FT3_SOCKET_SUPPORT FALSE
73
74/* Default families to off */
75#define OPTION_FAMILY15H_MODEL_1x FALSE
76#define OPTION_FAMILY16H_MODEL_0x FALSE
77
78
79/* Enable the appropriate socket support */
80
81#ifdef INSTALL_FT3_SOCKET_SUPPORT
82 #if INSTALL_FT3_SOCKET_SUPPORT == TRUE
83 #undef OPTION_FT3_SOCKET_SUPPORT
84 #define OPTION_FT3_SOCKET_SUPPORT TRUE
85 #endif
86#endif
87
88
89
90// F16_0x is supported in FT3
91#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
92 #if INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
93 #undef OPTION_FAMILY16H
94 #define OPTION_FAMILY16H TRUE
95 #undef OPTION_FAMILY16H_MODEL_0x
96 #define OPTION_FAMILY16H_MODEL_0x TRUE
97 #endif
98#endif
99
100/* Turn off families not required by socket designations */
101#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
102 #undef OPTION_FAMILY15H
103 #define OPTION_FAMILY15H FALSE
104#endif
105
106#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
107 #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
108 #undef OPTION_FAMILY16H_MODEL_0x
109 #define OPTION_FAMILY16H_MODEL_0x FALSE
110 #endif
111#endif
112
113
114#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
115 #undef OPTION_FAMILY16H
116 #define OPTION_FAMILY16H FALSE
117#endif
118
119
120#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
121 #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
122 #error No FT3 supported families included in the build
123 #endif
124#endif
125
126
127/* Process AGESA private data
128 *
129 * Turn on appropriate CPU models and memory controllers,
130 * as well as some other memory controls.
131 */
132
133/* Default all models to off */
134#define OPTION_FAMILY15H_TN FALSE
135#define OPTION_FAMILY16H_KB FALSE
136#define OPTION_FAMILY15H_UNKNOWN FALSE
137
138/* Default all memory controllers to off */
139#define OPTION_MEMCTLR_TN FALSE
140#define OPTION_MEMCTLR_KB FALSE
141
142/* Default all memory controls to off */
143#define OPTION_HW_WRITE_LEV_TRAINING FALSE
144#define OPTION_SW_WRITE_LEV_TRAINING FALSE
145#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
146#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
147#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
148#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
149#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
150#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
151#define OPTION_MAX_RD_LAT_TRAINING FALSE
152#define OPTION_HW_DRAM_INIT FALSE
153#define OPTION_SW_DRAM_INIT FALSE
154#define OPTION_S3_MEM_SUPPORT FALSE
155#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
156#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
157#define OPTION_RDDQS_2D_TRAINING FALSE
158#define OPTION_PRE_MEM_INIT FALSE
159#define OPTION_POST_MEM_INIT FALSE
160
161/* Defaults for public user options */
162#define OPTION_UDIMMS FALSE
163#define OPTION_RDIMMS FALSE
164#define OPTION_SODIMMS FALSE
165#define OPTION_LRDIMMS FALSE
166#define OPTION_DDR2 FALSE
167#define OPTION_DDR3 FALSE
168#define OPTION_ECC FALSE
169#define OPTION_BANK_INTERLEAVE FALSE
170#define OPTION_DCT_INTERLEAVE FALSE
171#define OPTION_NODE_INTERLEAVE FALSE
172#define OPTION_PARALLEL_TRAINING FALSE
173#define OPTION_ONLINE_SPARE FALSE
174#define OPTION_MEM_RESTORE FALSE
175#define OPTION_DIMM_EXCLUDE FALSE
176#define OPTION_AMP FALSE
177#define OPTION_DATA_EYE FALSE
178#define OPTION_AGGRESSOR FALSE
179
180/* Default all CPU controls to off */
181#define OPTION_MULTISOCKET FALSE
182#define OPTION_CRAT FALSE
183#define OPTION_CDIT FALSE
184#define OPTION_SRAT FALSE
185#define OPTION_SLIT FALSE
186#define OPTION_HT_ASSIST FALSE
187#define OPTION_ATM_MODE FALSE
188#define OPTION_NBR_CACHE FALSE
189#define OPTION_CPU_CORELEVELING FALSE
190#define OPTION_MSG_BASED_C1E FALSE
191#define OPTION_CPU_CFOH FALSE
192#define OPTION_C6_STATE FALSE
193#define OPTION_IO_CSTATE FALSE
194#define OPTION_CPB FALSE
195#define OPTION_CPU_APM FALSE
196#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
197#define OPTION_CPU_PSTATE_HPC_MODE FALSE
198#define OPTION_CPU_TDP_LIMITING FALSE
199#define OPTION_CPU_PSI FALSE
200#define OPTION_CPU_HTC FALSE
201#define OPTION_S3SCRIPT FALSE
202#define OPTION_GFX_RECOVERY FALSE
203#define OPTION_CPU_SCS FALSE
204#define OPTION_PREFETCH_MODE FALSE
205
206/* Default FCH controls to off */
207#define FCH_SUPPORT FALSE
208
209/* Enable all private controls based on socket/family enables */
210
211#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
212 #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
213 #undef FCH_SUPPORT
214 #define FCH_SUPPORT TRUE
215 #undef OPTION_FAMILY16H_KB
216 #define OPTION_FAMILY16H_KB TRUE
217 #undef OPTION_MEMCTLR_KB
218 #define OPTION_MEMCTLR_KB TRUE
219 #undef OPTION_HW_WRITE_LEV_TRAINING
220 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
221 #undef OPTION_CONTINOUS_PATTERN_GENERATION
222 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
223 #undef OPTION_HW_DQS_REC_EN_TRAINING
224 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
225 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
226 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
227 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
228 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
229 #undef OPTION_RDDQS_2D_TRAINING
230 #define OPTION_RDDQS_2D_TRAINING TRUE
231 #undef OPTION_MAX_RD_LAT_TRAINING
232 #define OPTION_MAX_RD_LAT_TRAINING TRUE
233 #undef OPTION_SW_DRAM_INIT
234 #define OPTION_SW_DRAM_INIT TRUE
235 #undef OPTION_S3_MEM_SUPPORT
236 #define OPTION_S3_MEM_SUPPORT TRUE
237 #undef OPTION_GFX_RECOVERY
238 #define OPTION_GFX_RECOVERY TRUE
239 #undef OPTION_CPU_CORELEVELING
240 #define OPTION_CPU_CORELEVELING TRUE
241 #undef OPTION_C6_STATE
242 #define OPTION_C6_STATE TRUE
243 #undef OPTION_IO_CSTATE
244 #define OPTION_IO_CSTATE TRUE
245 #undef OPTION_CPU_CFOH
246 #define OPTION_CPU_CFOH TRUE
247 #undef OPTION_CPU_APM
248 #define OPTION_CPU_APM TRUE
249 #undef OPTION_CPB
250 #define OPTION_CPB TRUE
251 #undef OPTION_CPU_HTC
252 #define OPTION_CPU_HTC TRUE
253 #undef OPTION_CPU_PSI
254 #define OPTION_CPU_PSI TRUE
255 #undef OPTION_CDIT
256 #define OPTION_CDIT TRUE
257 #undef OPTION_CRAT
258 #define OPTION_CRAT TRUE
259 #undef OPTION_CPU_SCS
260 #define OPTION_CPU_SCS TRUE
261 #undef OPTION_S3SCRIPT
262 #define OPTION_S3SCRIPT TRUE
263 ///@todo
264 //#undef OPTION_PREFETCH_MODE
265 //#define OPTION_PREFETCH_MODE TRUE
266 #undef OPTION_UDIMMS
267 #define OPTION_UDIMMS TRUE
268 #undef OPTION_SODIMMS
269 #define OPTION_SODIMMS TRUE
270 #undef OPTION_DDR3
271 #define OPTION_DDR3 TRUE
272 #undef OPTION_ECC
273 #define OPTION_ECC TRUE
274 #undef OPTION_BANK_INTERLEAVE
275 #define OPTION_BANK_INTERLEAVE TRUE
276 #undef OPTION_DCT_INTERLEAVE
277 #define OPTION_DCT_INTERLEAVE TRUE
278 #undef OPTION_MEM_RESTORE
279 #define OPTION_MEM_RESTORE TRUE
280 #undef OPTION_DIMM_EXCLUDE
281 #define OPTION_DIMM_EXCLUDE TRUE
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]282 #ifndef OPTION_MICROSERVER
283 #define OPTION_MICROSERVER FALSE
284 #endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]285 #endif
286#endif
287
288
289#if (OPTION_FAMILY16H_KB == TRUE)
290 #undef GNB_SUPPORT
291 #define GNB_SUPPORT TRUE
292#endif
293
294#define OPTION_ACPI_PSTATES TRUE
295#define OPTION_WHEA TRUE
296#define OPTION_DMI TRUE
297#define OPTION_EARLY_SAMPLES FALSE
298#define CFG_ACPI_PSTATES_PPC TRUE
299#define CFG_ACPI_PSTATES_PCT TRUE
300#define CFG_ACPI_PSTATES_PSD TRUE
301#define CFG_ACPI_PSTATES_PSS TRUE
302#define CFG_ACPI_PSTATES_XPSS TRUE
303#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
304#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
305#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
306#define OPTION_ALIB TRUE
307/*---------------------------------------------------------------------------
308 * Processing the options: Second, process the user's selections
309 *--------------------------------------------------------------------------*/
310#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
311 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
312 #undef OPTION_DDR3
313 #define OPTION_DDR3 FALSE
314 #endif
315#endif
316#if ((OPTION_DDR3 == FALSE))
317 #error BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
318#endif
319#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
320 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
321 #undef OPTION_MULTISOCKET
322 #define OPTION_MULTISOCKET FALSE
323 #endif
324#endif
325#ifdef BLDOPT_REMOVE_ECC_SUPPORT
326 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
327 #undef OPTION_ECC
328 #define OPTION_ECC FALSE
329 #endif
330#endif
331#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
332 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
333 #undef OPTION_UDIMMS
334 #define OPTION_UDIMMS FALSE
335 #endif
336#endif
337#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
338 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
339 #undef OPTION_RDIMMS
340 #define OPTION_RDIMMS FALSE
341 #endif
342#endif
343#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
344 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
345 #undef OPTION_SODIMMS
346 #define OPTION_SODIMMS FALSE
347 #endif
348#endif
349#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
350 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
351 #undef OPTION_LRDIMMS
352 #define OPTION_LRDIMMS FALSE
353 #endif
354#endif
355#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
356 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
357 #undef OPTION_BANK_INTERLEAVE
358 #define OPTION_BANK_INTERLEAVE FALSE
359 #endif
360#endif
361#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
362 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
363 #undef OPTION_DCT_INTERLEAVE
364 #define OPTION_DCT_INTERLEAVE FALSE
365 #endif
366#endif
367#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
368 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
369 #undef OPTION_NODE_INTERLEAVE
370 #define OPTION_NODE_INTERLEAVE FALSE
371 #endif
372#endif
373#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
374 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
375 #undef OPTION_PARALLEL_TRAINING
376 #define OPTION_PARALLEL_TRAINING FALSE
377 #endif
378#endif
379#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
380 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
381 #undef OPTION_ONLINE_SPARE
382 #define OPTION_ONLINE_SPARE FALSE
383 #endif
384#endif
385#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
386 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
387 #undef OPTION_MEM_RESTORE
388 #define OPTION_MEM_RESTORE FALSE
389 #endif
390#endif
391#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
392 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
393 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
394 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
395 #endif
396#endif
397#ifdef BLDOPT_REMOVE_ACPI_PSTATES
398 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
399 #undef OPTION_ACPI_PSTATES
400 #define OPTION_ACPI_PSTATES FALSE
401 #endif
402#endif
403#ifdef BLDOPT_REMOVE_CRAT
404 #if BLDOPT_REMOVE_CRAT == TRUE
405 #undef OPTION_CRAT
406 #define OPTION_CRAT FALSE
407 #endif
408#endif
409#ifdef BLDOPT_REMOVE_CDIT
410 #if BLDOPT_REMOVE_CDIT == TRUE
411 #undef OPTION_CDIT
412 #define OPTION_CDIT FALSE
413 #endif
414#endif
415#ifdef BLDOPT_REMOVE_SRAT
416 #if BLDOPT_REMOVE_SRAT == TRUE
417 #undef OPTION_SRAT
418 #define OPTION_SRAT FALSE
419 #endif
420#endif
421#ifdef BLDOPT_REMOVE_SLIT
422 #if BLDOPT_REMOVE_SLIT == TRUE
423 #undef OPTION_SLIT
424 #define OPTION_SLIT FALSE
425 #endif
426#endif
427#ifdef BLDOPT_REMOVE_WHEA
428 #if BLDOPT_REMOVE_WHEA == TRUE
429 #undef OPTION_WHEA
430 #define OPTION_WHEA FALSE
431 #endif
432#endif
433#ifdef BLDOPT_REMOVE_DMI
434 #if BLDOPT_REMOVE_DMI == TRUE
435 #undef OPTION_DMI
436 #define OPTION_DMI FALSE
437 #endif
438#endif
439#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
440 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
441 #undef OPTION_ADDR_TO_CS_TRANSLATOR
442 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
443 #endif
444#endif
445#ifdef BLDOPT_REMOVE_AMP_SUPPORT
446 #if BLDOPT_REMOVE_AMP_SUPPORT == TRUE
447 #undef OPTION_AMP
448 #define OPTION_AMP FALSE
449 #endif
450#endif
451
452#ifdef OPTION_RDDQS_2D_TRAINING
453 #if OPTION_RDDQS_2D_TRAINING == FALSE
454 #undef OPTION_DATA_EYE
455 #define OPTION_DATA_EYE FALSE
456 #else
457 #ifdef BLDOPT_REMOVE_DATA_EYE
458 #if BLDOPT_REMOVE_DATA_EYE == TRUE
459 #undef OPTION_DATA_EYE
460 #define OPTION_DATA_EYE FALSE
461 #endif
462 #endif
463 #endif
464#else
465 #undef OPTION_DATA_EYE
466 #define OPTION_DATA_EYE FALSE
467#endif
468
469#ifdef BLDOPT_REMOVE_HT_ASSIST
470 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
471 #undef OPTION_HT_ASSIST
472 #define OPTION_HT_ASSIST FALSE
473 #endif
474#endif
475
476#ifdef BLDOPT_REMOVE_ATM_MODE
477 #if BLDOPT_REMOVE_ATM_MODE == TRUE
478 #undef OPTION_ATM_MODE
479 #define OPTION_ATM_MODE FALSE
480 #endif
481#endif
482
483#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
484 #if BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
485 #undef OPTION_NBR_CACHE
486 #define OPTION_NBR_CACHE FALSE
487 #endif
488#endif
489
490#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
491 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
492 #undef OPTION_MSG_BASED_C1E
493 #define OPTION_MSG_BASED_C1E FALSE
494 #endif
495#endif
496
497#ifdef BLDOPT_REMOVE_C6_STATE
498 #if BLDOPT_REMOVE_C6_STATE == TRUE
499 #undef OPTION_C6_STATE
500 #define OPTION_C6_STATE FALSE
501 #endif
502#endif
503
504#ifdef BLDOPT_REMOVE_GFX_RECOVERY
505 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
506 #undef OPTION_GFX_RECOVERY
507 #define OPTION_GFX_RECOVERY FALSE
508 #endif
509#endif
510
511#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
512 #if BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
513 #undef OPTION_RDDQS_2D_TRAINING
514 #define OPTION_RDDQS_2D_TRAINING FALSE
515 #endif
516#endif
517
518#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
519 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
520 #undef CFG_ACPI_PSTATES_PPC
521 #define CFG_ACPI_PSTATES_PPC FALSE
522 #endif
523#endif
524
525#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
526 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
527 #undef CFG_ACPI_PSTATES_PCT
528 #define CFG_ACPI_PSTATES_PCT FALSE
529 #endif
530#endif
531
532#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
533 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
534 #undef CFG_ACPI_PSTATES_PSD
535 #define CFG_ACPI_PSTATES_PSD FALSE
536 #endif
537#endif
538
539#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
540 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
541 #undef CFG_ACPI_PSTATES_PSS
542 #define CFG_ACPI_PSTATES_PSS FALSE
543 #endif
544#endif
545
546#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
547 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
548 #undef CFG_ACPI_PSTATES_XPSS
549 #define CFG_ACPI_PSTATES_XPSS FALSE
550 #endif
551#endif
552
553#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
554 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
555 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
556 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
557 #endif
558#endif
559
560#ifdef BLDOPT_REMOVE_AGGRESSOR
561 #if BLDOPT_REMOVE_AGGRESSOR == TRUE
562 #undef OPTION_AGGRESSOR
563 #define OPTION_AGGRESSOR FALSE
564 #endif
565#endif
566
567#ifdef BLDCFG_PSTATE_HPC_MODE
568 #if BLDCFG_PSTATE_HPC_MODE == TRUE
569 #undef OPTION_CPU_PSTATE_HPC_MODE
570 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
571 #endif
572#endif
573
574#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
575 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
576 #undef CFG_ACPI_PSTATE_PSD_INDPX
577 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
578 #endif
579#endif
580
581#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
582 #define CFG_ACPI_PSTATES_PSD_POLICY (BLDCFG_ACPI_PSTATES_PSD_POLICY)
583#else
584 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
585#endif
586
587#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
588 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
589 #undef CFG_VRM_HIGH_SPEED_ENABLE
590 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
591 #endif
592#endif
593
594#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
595 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
596 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
597 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
598 #endif
599#endif
600
601#ifdef BLDCFG_STARTING_BUSNUM
602 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
603#else
604 #define CFG_STARTING_BUSNUM (0)
605#endif
606
607#ifdef BLDCFG_AMD_PLATFORM_TYPE
608 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
609#else
610 #define CFG_AMD_PLATFORM_TYPE 0
611#endif
612
613CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
614
615#ifdef BLDCFG_MAXIMUM_BUSNUM
616 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
617#else
618 #define CFG_MAXIMUM_BUSNUM (0xF8)
619#endif
620
621#ifdef BLDCFG_ALLOCATED_BUSNUM
622 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
623#else
624 #define CFG_ALLOCATED_BUSNUM (0x20)
625#endif
626
627#ifdef BLDCFG_BUID_SWAP_LIST
628 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
629#else
630 #define CFG_BUID_SWAP_LIST (NULL)
631#endif
632
633#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
634 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
635#else
636 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
637#endif
638
639#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
640 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
641#else
642 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
643#endif
644
645#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
646 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
647#else
648 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
649#endif
650
651#ifdef BLDCFG_BUS_NUMBERS_LIST
652 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
653#else
654 #define CFG_BUS_NUMBERS_LIST (NULL)
655#endif
656
657#ifdef BLDCFG_IGNORE_LINK_LIST
658 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
659#else
660 #define CFG_IGNORE_LINK_LIST (NULL)
661#endif
662
663#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
664 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
665#else
666 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
667#endif
668
669#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
670 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
671#else
672 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
673#endif
674
675#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
676 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
677#else
678 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
679#endif
680
681#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
682 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
683#else
684 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
685#endif
686
687#ifdef BLDCFG_USE_HT_ASSIST
688 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
689#else
690 #define CFG_USE_HT_ASSIST (TRUE)
691#endif
692
693#ifdef BLDCFG_USE_ATM_MODE
694 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
695#else
696 #define CFG_USE_ATM_MODE (TRUE)
697#endif
698
699#ifdef BLDCFG_USE_NEIGHBOR_CACHE
700 #define CFG_USE_NBR_CACHE (BLDCFG_USE_NEIGHBOR_CACHE)
701#else
702 #define CFG_USE_NBR_CACHE (TRUE)
703#endif
704
705#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
706 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
707#else
708 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
709#endif
710
711#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
712 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
713#else
714 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
715#endif
716
717#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
718 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
719#else
720 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
721#endif
722
723#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
724 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
725#else
726 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
727#endif
728
729#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
730 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
731#else
732 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
733#endif
734
735#ifdef BLDCFG_VRM_CURRENT_LIMIT
736 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
737#else
738 #define CFG_VRM_CURRENT_LIMIT 0
739#endif
740
741#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
742 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
743#else
744 #define CFG_VRM_LOW_POWER_THRESHOLD 0
745#endif
746
747#ifdef BLDCFG_VRM_SLEW_RATE
748 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
749#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]750 #define CFG_VRM_SLEW_RATE (5000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]751#endif
752
753#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
754 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
755#else
756 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
757#endif
758
759#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
760 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
761#else
762 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
763#endif
764
765#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
766 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
767#else
768 #define CFG_VRM_SVI_OCP_LEVEL 0
769#endif
770
771#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
772 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
773#else
774 #define CFG_VRM_NB_SVI_OCP_LEVEL 0
775#endif
776
777#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
778 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
779#else
780 #define CFG_VRM_NB_CURRENT_LIMIT (0)
781#endif
782
783#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
784 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
785#else
786 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
787#endif
788
789#ifdef BLDCFG_VRM_NB_SLEW_RATE
790 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
791#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]792 #define CFG_VRM_NB_SLEW_RATE (5000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]793#endif
794
795#ifdef BLDCFG_PLAT_NUM_IO_APICS
796 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
797#else
798 #define CFG_PLAT_NUM_IO_APICS 0
799#endif
800
801#ifdef BLDCFG_MEM_INIT_PSTATE
802 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
803#else
804 #define CFG_MEM_INIT_PSTATE 0
805#endif
806
807#ifdef BLDCFG_PLATFORM_C1E_MODE
808 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
809#else
810 #define CFG_C1E_MODE C1eModeDisabled
811#endif
812
813#ifdef BLDCFG_PLATFORM_C1E_OPDATA
814 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
815#else
816 #define CFG_C1E_OPDATA 0
817#endif
818
819#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
820 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
821#else
822 #define CFG_C1E_OPDATA1 0
823#endif
824
825#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
826 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
827#else
828 #define CFG_C1E_OPDATA2 0
829#endif
830
831#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
832 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
833#else
834 #define CFG_C1E_OPDATA3 0
835#endif
836
837#ifdef BLDCFG_PLATFORM_CSTATE_MODE
838 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
839#else
840 #define CFG_CSTATE_MODE CStateModeC6
841#endif
842
843#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
844 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
845#else
846 #define CFG_CSTATE_OPDATA 0
847#endif
848
849#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
850 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
851#else
852 #define CFG_CSTATE_IO_BASE_ADDRESS 0
853#endif
854
855#ifdef BLDCFG_PLATFORM_CPB_MODE
856 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
857#else
858 #define CFG_CPB_MODE CpbModeAuto
859#endif
860
861#ifdef BLDCFG_CORE_LEVELING_MODE
862 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
863#else
864 #define CFG_CORE_LEVELING_MODE 0
865#endif
866
867#ifdef BLDCFG_AMD_TDP_LIMIT
868 #define CFG_AMD_POWER_CEILING BLDCFG_AMD_TDP_LIMIT
869#else
870 #define CFG_AMD_POWER_CEILING 0
871#endif
872
873#ifdef BLDCFG_HEAP_DRAM_ADDRESS
874 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
875#else
876 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
877#endif
878
879#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
880 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
881#else
882 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
883#endif
884
885#ifdef BLDCFG_MEMORY_MODE_UNGANGED
886 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
887#else
888 #define CFG_MEMORY_MODE_UNGANGED TRUE
889#endif
890
891#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
892 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
893#else
894 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
895#endif
896
897#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
898 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
899#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]900 #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]901#endif
902
903#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
904 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
905#else
906 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
907#endif
908
909#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
910 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
911#else
912 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
913#endif
914
915#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
916 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
917#else
918 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
919#endif
920
921#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
922 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
923#else
924 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
925#endif
926
927#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
928 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
929#else
930 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
931#endif
932
933#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
934 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
935#else
936 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
937#endif
938
939#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
940 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
941#else
942 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
943#endif
944
945#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
946 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
947#else
948 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
949#endif
950
951#ifdef BLDCFG_MEMORY_POWER_DOWN
952 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
953#else
954 #define CFG_MEMORY_POWER_DOWN FALSE
955#endif
956
957#ifdef BLDCFG_POWER_DOWN_MODE
958 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
959#else
960 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
961#endif
962
963#ifdef BLDCFG_ONLINE_SPARE
964 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
965#else
966 #define CFG_ONLINE_SPARE FALSE
967#endif
968
969#ifdef BLDCFG_MEMORY_PARITY_ENABLE
970 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
971#else
972 #define CFG_MEMORY_PARITY_ENABLE FALSE
973#endif
974
975#ifdef BLDCFG_BANK_SWIZZLE
976 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
977#else
978 #define CFG_BANK_SWIZZLE TRUE
979#endif
980
981#ifdef BLDCFG_TIMING_MODE_SELECT
982 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
983#else
984 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
985#endif
986
987#ifdef BLDCFG_MEMORY_CLOCK_SELECT
988 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
989#else
990 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
991#endif
992
993#ifdef BLDCFG_DQS_TRAINING_CONTROL
994 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
995#else
996 #define CFG_DQS_TRAINING_CONTROL TRUE
997#endif
998
999#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1000 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1001#else
1002 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1003#endif
1004
1005#ifdef BLDCFG_USE_BURST_MODE
1006 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1007#else
1008 #define CFG_USE_BURST_MODE FALSE
1009#endif
1010
1011#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1012 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1013#else
1014 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1015#endif
1016
1017#ifdef BLDCFG_ENABLE_ECC_FEATURE
1018 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1019#else
1020 #define CFG_ENABLE_ECC_FEATURE TRUE
1021#endif
1022
1023#ifdef BLDCFG_ECC_REDIRECTION
1024 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1025#else
1026 #define CFG_ECC_REDIRECTION FALSE
1027#endif
1028
1029#ifdef BLDCFG_SCRUB_DRAM_RATE
1030 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1031#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]1032 #define CFG_SCRUB_DRAM_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1033#endif
1034
1035#ifdef BLDCFG_SCRUB_L2_RATE
1036 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1037#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]1038 #define CFG_SCRUB_L2_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1039#endif
1040
1041#ifdef BLDCFG_SCRUB_L3_RATE
1042 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1043#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]1044 #define CFG_SCRUB_L3_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1045#endif
1046
1047#ifdef BLDCFG_SCRUB_IC_RATE
1048 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1049#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]1050 #define CFG_SCRUB_IC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1051#endif
1052
1053#ifdef BLDCFG_SCRUB_DC_RATE
1054 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1055#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame^]1056 #define CFG_SCRUB_DC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1057#endif
1058
1059#ifdef BLDCFG_ECC_SYNC_FLOOD
1060 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1061#else
1062 #define CFG_ECC_SYNC_FLOOD TRUE
1063#endif
1064
1065#ifdef BLDCFG_ECC_SYMBOL_SIZE
1066 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1067#else
1068 #define CFG_ECC_SYMBOL_SIZE 0
1069#endif
1070
1071#ifdef BLDCFG_1GB_ALIGN
1072 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1073#else
1074 #define CFG_1GB_ALIGN FALSE
1075#endif
1076
1077#ifdef BLDCFG_UMA_ALLOCATION_MODE
1078 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1079#else
1080 #define CFG_UMA_MODE UMA_AUTO
1081#endif
1082
1083#ifdef BLDCFG_FORCE_TRAINING_MODE
1084 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1085#else
1086 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1087#endif
1088
1089#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1090 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1091#else
1092 #define CFG_UMA_SIZE 0
1093#endif
1094
1095#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1096 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1097#else
1098 #define CFG_UMA_ABOVE4G FALSE
1099#endif
1100
1101#ifdef BLDCFG_UMA_ALIGNMENT
1102 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1103#else
1104 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1105#endif
1106
1107#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1108 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1109#else
1110 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG DDR3_TECHNOLOGY
1111#endif
1112
1113#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1114 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1115#else
1116 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1117#endif
1118
1119#ifdef BLDCFG_S3_LATE_RESTORE
1120 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1121#else
1122 #define CFG_S3_LATE_RESTORE TRUE
1123#endif
1124
1125#ifdef BLDCFG_USE_32_BYTE_REFRESH
1126 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1127#else
1128 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1129#endif
1130
1131#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1132 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1133#else
1134 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1135#endif
1136
1137#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1138 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1139#else
1140 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1141#endif
1142
1143#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1144 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1145#else
1146 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1147#endif
1148
1149#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1150 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1151#else
1152 #define CFG_GNB_HD_AUDIO TRUE
1153#endif
1154
1155#ifdef BLDCFG_CFG_ABM_SUPPORT
1156 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1157#else
1158 #define CFG_ABM_SUPPORT FALSE
1159#endif
1160
1161#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1162 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1163#else
1164 #define CFG_DYNAMIC_REFRESH_RATE 0
1165#endif
1166
1167#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1168 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1169#else
1170 #define CFG_LCD_BACK_LIGHT_CONTROL 200
1171#endif
1172
1173#ifdef BLDCFG_STEREO_3D_PINOUT
1174 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1175#else
1176 #define CFG_GNB_STEREO_3D_PINOUT 0
1177#endif
1178
1179#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1180 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1181#else
1182 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1183#endif
1184
1185// Define pin configuration for SYNCFLOOD
1186// Default to FALSE (Use pin as SYNCFLOOD)
1187#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
1188 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
1189#else
1190 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
1191#endif
1192
1193#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1194 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1195#else
1196 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
1197#endif
1198
1199#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1200 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1201#else
1202 #define CFG_GNB_IGPU_SSID 0
1203#endif
1204
1205#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1206 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1207#else
1208 #define CFG_GNB_HDAUDIO_SSID 0
1209#endif
1210
1211#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1212 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1213#else
1214 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
1215#endif
1216
1217#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1218 #define CFG_GNB_PCIE_SSID BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1219#else
1220 #define CFG_GNB_PCIE_SSID 0x12341022ul
1221#endif
1222
1223#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1224 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1225#else
1226 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1227#endif
1228
1229#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1230 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1231#else
1232 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1233#endif
1234
1235#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1236 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1237#else
1238 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1239#endif
1240
1241#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1242 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1243#else
1244 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
1245#endif
1246
1247#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1248 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1249#else
1250 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1251#endif
1252
1253#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1254 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1255 #undef OPTION_EARLY_SAMPLES
1256 #define OPTION_EARLY_SAMPLES FALSE
1257 #else
1258 #undef OPTION_EARLY_SAMPLES
1259 #define OPTION_EARLY_SAMPLES TRUE
1260 #endif
1261#endif
1262
1263#ifdef BLDOPT_REMOVE_ALIB
1264 #if BLDOPT_REMOVE_ALIB == TRUE
1265 #undef OPTION_ALIB
1266 #define OPTION_ALIB FALSE
1267 #else
1268 #undef OPTION_ALIB
1269 #define OPTION_ALIB TRUE
1270 #endif
1271#endif
1272
1273#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1274 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1275 #undef FCH_SUPPORT
1276 #define FCH_SUPPORT FALSE
1277 #endif
1278#endif
1279
1280#ifdef BLDCFG_IOMMU_SUPPORT
1281 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1282#else
1283 #define CFG_IOMMU_SUPPORT TRUE
1284#endif
1285
1286#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1287 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1288#else
1289 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1290#endif
1291
1292#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1293 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1294#else
1295 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1296#endif
1297
1298#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1299 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1300#else
1301 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1302#endif
1303
1304#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1305 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1306#else
1307 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1308#endif
1309
1310#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1311 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1312#else
1313 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1314#endif
1315
1316#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1317 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1318#else
1319 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1320#endif
1321
1322#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1323 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1324#else
1325 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1326#endif
1327
1328#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1329 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1330#else
1331 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1332#endif
1333
1334#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1335 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1336#else
1337 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1338#endif
1339
1340
1341// BLDCFG_LVDS_24BBP_PANEL_MODE
1342// This specifies the LVDS 24 BBP mode.
1343// 0 - Use LDI mode (default).
1344// 1 - Use FPDI mode.
1345#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1346 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1347#else
1348 #define CFG_LVDS_24BBP_PANEL_MODE 0
1349#endif
1350
1351#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1352 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1353#else
1354 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1355#endif
1356
1357#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1358 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1359#else
1360 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1361#endif
1362
1363#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1364 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1365#else
1366 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1367#endif
1368
1369#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1370 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1371#else
1372 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1373#endif
1374
1375#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1376 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1377#else
1378 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1379#endif
1380
1381#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1382 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1383#else
1384 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
1385#endif
1386
1387#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1388 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1389#else
1390 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
1391#endif
1392
1393#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1394 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1395#else
1396 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
1397#endif
1398
1399#ifdef BLDCFG_DP_FIXED_VOLT_SWING
1400 #define CFG_DP_FIXED_VOLT_SWING BLDCFG_DP_FIXED_VOLT_SWING
1401#else
1402 #define CFG_DP_FIXED_VOLT_SWING 0
1403#endif
1404
1405#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1406 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1407#else
1408 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1409#endif
1410
1411#ifdef BLDCFG_NB_PSTATES_SUPPORTED
1412 #define CFG_NB_PSTATES_SUPPORTED (BLDCFG_NB_PSTATES_SUPPORTED)
1413#else
1414 #define CFG_NB_PSTATES_SUPPORTED (TRUE)
1415#endif
1416
1417#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
1418 #define CFG_HTC_TEMPERATURE_LIMIT (BLDCFG_HTC_TEMPERATURE_LIMIT)
1419#else
1420 #define CFG_HTC_TEMPERATURE_LIMIT (0)
1421#endif
1422
1423#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
1424 #define CFG_LHTC_TEMPERATURE_LIMIT (BLDCFG_LHTC_TEMPERATURE_LIMIT)
1425#else
1426 #define CFG_LHTC_TEMPERATURE_LIMIT (0)
1427#endif
1428
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1429#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1430
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1431#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1432
1433#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1434 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1435#else
1436 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
1437#endif
1438
1439#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
1440 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
1441#else
1442 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
1443#endif
1444
1445#ifdef BLDCFG_HYBRID_BOOST_ENABLE
1446 #define CFG_HYBRID_BOOST_ENABLE BLDCFG_HYBRID_BOOST_ENABLE
1447#else
1448 #define CFG_HYBRID_BOOST_ENABLE TRUE
1449#endif
1450
1451#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
1452 #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
1453#else
1454 #define CFG_GNB_IOAPIC_ADDRESS NULL
1455#endif
1456
1457#ifdef BLDCFG_GNB_IOMMU_ADDRESS
1458 #define CFG_GNB_IOMMU_ADDRESS BLDCFG_GNB_IOMMU_ADDRESS
1459#else
1460 #define CFG_GNB_IOMMU_ADDRESS NULL
1461#endif
1462
1463#ifdef BLDCFG_ENABLE_DATA_EYE
1464 #define CFG_ENABLE_DATA_EYE BLDCFG_ENABLE_DATA_EYE
1465#else
1466 #define CFG_ENABLE_DATA_EYE TRUE
1467#endif
1468
1469#ifdef BLDCFG_ACPI_SET_OEM_ID
1470 #define CFG_ACPI_SET_OEM_ID BLDCFG_ACPI_SET_OEM_ID
1471#else
1472 #define CFG_ACPI_SET_OEM_ID 'A','M','D',' ',' ',' '
1473#endif
1474
1475#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
1476 #define CFG_ACPI_SET_OEM_TABLE_ID BLDCFG_ACPI_SET_OEM_TABLE_ID
1477#else
1478 #define CFG_ACPI_SET_OEM_TABLE_ID 'A','G','E','S','A',' ',' ',' '
1479#endif
1480
1481#ifdef BLDCFG_DOCKED_TDP_HEADROOM
1482 #define CFG_DOCKED_TDP_HEADROOM BLDCFG_DOCKED_TDP_HEADROOM
1483#else
1484 #define CFG_DOCKED_TDP_HEADROOM TRUE
1485#endif
1486
1487#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1488 #define CFG_DRAM_DOUBLE_REFRESH_RATE BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1489#else
1490 #define CFG_DRAM_DOUBLE_REFRESH_RATE FALSE
1491#endif
1492
1493/*---------------------------------------------------------------------------
1494 * Processing the options: Third, perform the option cross checks
1495 *--------------------------------------------------------------------------*/
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1496// Check that deprecated options are not used
1497#ifdef BLDCFG_PCI_MMIO_BASE
1498 #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use!
1499#endif
1500#ifdef BLDCFG_PCI_MMIO_SIZE
1501 #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use!
1502#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1503// Assure that at least one type of memory support is included
1504#if OPTION_UDIMMS == FALSE
1505 #if OPTION_RDIMMS == FALSE
1506 #if OPTION_SODIMMS == FALSE
1507 #if OPTION_LRDIMMS == FALSE
1508 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1509 #endif
1510 #endif
1511 #endif
1512#endif
1513// Ensure at least one dimm type is capable
1514#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1515 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1516 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1517 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1518 #error BLDCFG: No dimm type is capable
1519 #endif
1520 #endif
1521 #endif
1522#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1523// Turn off multi-socket based features if only one node...
1524#if OPTION_MULTISOCKET == FALSE
1525 #undef OPTION_PARALLEL_TRAINING
1526 #define OPTION_PARALLEL_TRAINING FALSE
1527 #undef OPTION_NODE_INTERLEAVE
1528 #define OPTION_NODE_INTERLEAVE FALSE
1529#endif
1530// Ensure the frequency limit is valid
1531#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
1532 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
1533 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
1534 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
1535 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
1536 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
1537 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
1538 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
1539 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
1540 #error BLDCFG: Unsupported memory bus frequency
1541 #endif
1542 #endif
1543 #endif
1544 #endif
1545 #endif
1546 #endif
1547 #endif
1548 #endif
1549#endif
1550// Ensure timing mode is valid
1551#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1552 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1553 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1554 #error BLDCFG: Invalid timing mode is set
1555 #endif
1556 #endif
1557#endif
1558// Ensure the scrub rate is valid
1559#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1560 #error BLDCFG: Unsupported dram scrub rate set
1561#endif
1562#if CFG_SCRUB_L2_RATE > 0x16
1563 #error BLDCFG: Unsupported L2 scrubber rate set
1564#endif
1565#if CFG_SCRUB_L3_RATE > 0x16
1566 #error BLDCFG: unsupported L3 scrubber rate set
1567#endif
1568#if CFG_SCRUB_IC_RATE > 0x16
1569 #error BLDCFG: Unsupported Instruction cache scrub rate set
1570#endif
1571#if CFG_SCRUB_DC_RATE > 0x16
1572 #error BLDCFG: Unsupported Dcache scrub rate set
1573#endif
1574// Ensure Quad rank dimm type is valid
1575#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1576 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1577 #error BLDCFG: Invalid quad rank dimm type set
1578 #endif
1579#endif
1580// Ensure ECC symbol size is valid
1581#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1582 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1583 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1584 #error BLDCFG: Invalid Ecc symbol size set
1585 #endif
1586 #endif
1587#endif
1588// Ensure power down mode is valid
1589#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1590 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1591 #if AGESA_ENTRY_INIT_POST == TRUE
1592 #error BLDCFG: Invalid power down mode set
1593 #endif
1594 #endif
1595#endif
1596
1597// Ensure P-state dependence settings do not conflict
1598#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1599 #error BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
1600#endif
1601
1602#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
1603 #error BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
1604#endif
1605
1606#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
1607 #error BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
1608#endif
1609
1610
1611
1612/*****************************************************************************
1613 *
1614 * Process the option logic, setting local control variables
1615 *
1616 ****************************************************************************/
1617#if OPTION_ACPI_PSTATES == TRUE
1618 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1619 #define OPTFCN_GATHER_DATA PStateGatherData
1620 #if OPTION_MULTISOCKET == TRUE
1621 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1622 #else
1623 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1624 #endif
1625#else
1626 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1627 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1628 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1629#endif
1630
1631// Consolidate P-state dependence setings
1632#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1633 #undef CFG_ACPI_PSTATES_PSD_POLICY
1634 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyIndependent
1635#endif
1636
1637/*****************************************************************************
1638 *
1639 * Include the structure definitions for the defaults table structures
1640 *
1641 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1642#include <CommonReturns.h>
1643#include <agesa-entry-cfg.h>
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1644#include "Options.h"
1645#include "OptionCpuFamiliesInstall.h"
1646#include "OptionsHt.h"
1647#include "OptionHtInstall.h"
1648#include "OptionMemory.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1649#include "OptionMemoryInstall.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1650#include "OptionCpuFeaturesInstall.h"
1651#include "OptionDmi.h"
1652#include "OptionDmiInstall.h"
1653#include "OptionPstate.h"
1654#include "OptionPstateInstall.h"
1655#include "OptionWhea.h"
1656#include "OptionWheaInstall.h"
1657#include "OptionCrat.h"
1658#include "OptionCratInstall.h"
1659#include "OptionCdit.h"
1660#include "OptionCditInstall.h"
1661#include "OptionSrat.h"
1662#include "OptionSratInstall.h"
1663#include "OptionSlit.h"
1664#include "OptionSlitInstall.h"
1665#include "OptionMultiSocket.h"
1666#include "OptionMultiSocketInstall.h"
1667#include "OptionIdsInstall.h"
1668#include "OptionGfxRecovery.h"
1669#include "OptionGfxRecoveryInstall.h"
1670#include "OptionGnb.h"
1671#include "OptionGnbInstall.h"
1672#include "OptionS3ScriptInstall.h"
1673#include "OptionFchInstall.h"
1674#include "OptionMmioMapInstall.h"
1675#include "OptionPrefetchModeInstall.h"
1676
1677
1678/*****************************************************************************
1679 *
1680 * Generate the output structures (defaults tables)
1681 *
1682 ****************************************************************************/
1683
1684FCH_PLATFORM_POLICY FchUserOptions = {
1685 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
1686 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
1687 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
1688 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
1689 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
1690 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
1691 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
1692 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
1693 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
1694 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
1695 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
1696 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
1697 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
1698 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
1699 0x780D1022ul,
1700 CFG_SMBUS_SSID, // CfgSmbusSsid
1701 CFG_IDE_SSID, // CfgIdeSsid
1702 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
1703 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
1704 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
1705 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
1706 CFG_EHCI_SSID, // CfgEhcidSsid
1707 CFG_OHCI_SSID, // CfgOhcidSsid
1708 CFG_LPC_SSID, // CfgLpcSsid
1709 CFG_SD_SSID, // CfgSdSsid
1710 CFG_XHCI_SSID, // CfgXhciSsid
1711 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
1712 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
1713 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
1714 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
1715 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
1716 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
1717 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
1718 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
1719 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
1720 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
1721 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
1722
1723 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
1724 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
1725 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
1726 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
1727 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]1728 CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl
1729 CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1730};
1731
1732BUILD_OPT_CFG UserOptions = {
1733 { // AGESA version string
1734 AGESA_CODE_SIGNATURE, // code header Signature
1735 AGESA_PACKAGE_STRING, // 16 character ID
1736 AGESA_VERSION_STRING, // 12 character version string
1737 0 // null string terminator
1738 },
1739 //Build Option Area
1740 OPTION_UDIMMS, //UDIMMS
1741 OPTION_RDIMMS, //RDIMMS
1742 OPTION_LRDIMMS, //LRDIMMS
1743 OPTION_ECC, //ECC
1744 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1745 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1746 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1747 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1748 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1749 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1750 OPTION_MULTISOCKET, //MULTISOCKET
1751 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1752 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
1753 OPTION_CRAT, //CRAT
1754 OPTION_CDIT, //CDIT
1755 OPTION_SRAT, //SRAT
1756 OPTION_SLIT, //SLIT
1757 OPTION_WHEA, //WHEA
1758 OPTION_DMI, //DMI
1759 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1760 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1761
1762 //Build Configuration Area
1763 CFG_PCI_MMIO_BASE,
1764 CFG_PCI_MMIO_SIZE,
1765 {
1766 // CoreVrm
1767 {
1768 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1769 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1770 CFG_VRM_SLEW_RATE, // VrmSlewRate
1771 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1772 CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmMaximumCurrentLimit
1773 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
1774 },
1775 // NbVrm
1776 {
1777 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1778 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1779 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1780 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1781 CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbMaximumCurrentLimit
1782 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
1783 }
1784 },
1785 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1786 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1787 CFG_C1E_MODE, //C1eMode
1788 CFG_C1E_OPDATA, //C1ePlatformData
1789 CFG_C1E_OPDATA1, //C1ePlatformData1
1790 CFG_C1E_OPDATA2, //C1ePlatformData2
1791 CFG_C1E_OPDATA3, //C1ePlatformData3
1792 CFG_CSTATE_MODE, //CStateMode
1793 CFG_CSTATE_OPDATA, //CStatePlatformData
1794 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1795 CFG_CPB_MODE, //CpbMode
1796 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
1797 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1798 {
1799 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1800 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1801 CFG_USE_ATM_MODE, // CfgUseAtmMode
1802 CFG_USE_NBR_CACHE, // CfgUseNbrCache
1803 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1804 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1805 // ADVANCED_PERFORMANCE_PROFILE
1806 {
1807 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
1808 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
1809 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
1810 },
1811 CFG_PLATFORM_POWER_POLICY_MODE, // The platform's power policy mode.
1812 CFG_NB_PSTATES_SUPPORTED // The Nb-Pstates is supported or not
1813 },
1814 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1815 CFG_AMD_PLATFORM_TYPE, // CfgAmdPlatformType
1816 CFG_AMD_POWER_CEILING, // CfgAmdPowerCeiling
1817 CFG_HTC_TEMPERATURE_LIMIT, // CfgHtcTemperatureLimit
1818 CFG_LHTC_TEMPERATURE_LIMIT, // CfgLhtcTemperatureLimit
1819
1820 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1821 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1822 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1823 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1824 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1825 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1826 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1827 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1828 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
1829 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1830 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1831 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1832 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1833 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1834 CFG_ONLINE_SPARE, // CfgOnlineSpare
1835 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1836 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1837 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1838 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1839 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1840 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1841 CFG_USE_BURST_MODE, // CfgUseBurstMode
1842 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1843 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1844 CFG_ECC_REDIRECTION, // CfgEccRedirection
1845 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1846 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1847 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1848 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1849 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1850 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1851 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1852 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1853 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1854 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1855 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1856 CFG_ACPI_PSTATES_PSD_POLICY, // CfgAcpiPstatesPsdPolicy
1857 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1858 CFG_UMA_MODE, // CfgUmaMode
1859 CFG_UMA_SIZE, // CfgUmaSize
1860 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1861 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1862 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1863 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1864 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1865 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1866 CFG_ABM_SUPPORT, // CfgAbmSupport
1867 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1868 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1869 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1870 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1871 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1872 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1873 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1874 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1875 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1876
1877 &FchUserOptions, // FchBldCfg
1878
1879 CFG_IOMMU_SUPPORT, // CfgIommuSupport
1880 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
1881 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
1882 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
1883 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
1884 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
1885 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
1886 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
1887 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
1888 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
1889 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
1890 {{
1891 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1892 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1893 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1894 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1895 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1896 CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl
1897 }},
1898 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
1899 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
1900 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
1901 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
1902 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
1903 CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi
1904 CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy
1905 CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset
1906 CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment
1907 {{
1908 0, // Reserved
1909 CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
1910 0, // Reserved
1911 }},
1912 CFG_DP_FIXED_VOLT_SWING, // CfgDpFixedVoltSwingType
1913 CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG, // CfgDimmTypeUsedInMixedConfig
1914 CFG_HYBRID_BOOST_ENABLE, // CfgHybridBoostEnable
1915 CFG_GNB_IOAPIC_ADDRESS, // CfgGnbIoapicAddress
1916 CFG_ENABLE_DATA_EYE, // CfgDataEyeEn
1917 CFG_DOCKED_TDP_HEADROOM, // CfgDockedTdpHeadroom
1918 CFG_DRAM_DOUBLE_REFRESH_RATE, // CfgDramDoubleRefreshRateEn
1919 0, //reserved...
1920};
1921
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1922CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1923{
1924 IDS_LATE_RUN_AP_TASK
1925 // Get DMI info
1926 CPU_DMI_AP_GET_TYPE4_TYPE7
1927 // Probe filter enable
1928 L3_FEAT_AP_DISABLE_CACHE
1929 L3_FEAT_AP_ENABLE_CACHE
1930 // Cpu Prefetch Mode
1931 CPU_PREFETCH_MODE_AP_TASK
1932 { 0, NULL }
1933};
1934
1935#if AGESA_ENTRY_INIT_EARLY == TRUE
1936 #if IDSOPT_IDS_ENABLED == TRUE
1937 #if IDSOPT_TRACING_ENABLED == TRUE
1938 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1939 CONST CHAR8 *BldOptDebugOutput[] = {
1940 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1941 //Build Option Area
1942 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1943 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1944 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1945 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1946 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1947 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1948 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1949 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1950 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1951 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1952 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1953 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1954 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1955 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1956 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1957 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1958 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1959 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1960
1961 //Build Configuration Area
1962 // CoreVrm
1963 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1964 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1965 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1966 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1967 MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
1968 MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL)
1969 // NbVrm
1970 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1971 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1972 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1973 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1974 MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
1975 MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL)
1976
1977 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1978 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1979 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
1980 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
1981 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
1982 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
1983 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
1984 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
1985 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
1986 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
1987 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
1988 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
1989
1990 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
1991 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
1992 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
1993 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
1994 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1995 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
1996
1997 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
1998
1999 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2000 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2001 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2002 MAKE_DBG_STR (\nPowerCeiling , CFG_AMD_POWER_CEILING),
2003 MAKE_DBG_STR (\nHtcTempLimit , CFG_HTC_TEMPERATURE_LIMIT)
2004 MAKE_DBG_STR (\nLhtcTempLimit , CFG_LHTC_TEMPERATURE_LIMIT)
2005
2006 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2007 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2008 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2009
2010 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2011 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2012 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2013 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2014 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2015 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2016 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2017 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2018 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2019 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2020 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2021
2022 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2023 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2024 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2025 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2026 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2027 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2028 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2029 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2030 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2031
2032 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2033 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2034 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2035 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2036
2037 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2038 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2039 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2040 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2041 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2042 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2043 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2044 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2045 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2046 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2047 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2048
2049 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2050 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2051 MAKE_DBG_STR (\nAcpiPstatesPsdPolicy , CFG_ACPI_PSTATES_PSD_POLICY)
2052
2053 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2054
2055 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2056 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2057 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2058 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2059 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2060 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2061 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2062 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2063 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2064 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2065 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2066 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2067 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2068 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2069 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2070 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2071 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2072 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2073 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2074 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2075 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2076 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2077 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2078 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2079 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2080 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2081 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2082 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2083 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2084 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2085 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2086 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2087 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2088 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2089 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2090 MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
2091 MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY),
2092 MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION),
2093 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
2094 MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
2095 MAKE_DBG_STR (\nCfgDataEyeEn , CFG_ENABLE_DATA_EYE),
2096 MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn , CFG_DRAM_DOUBLE_REFRESH_RATE),
2097 #endif
2098 NULL
2099 };
2100 #endif
2101 #endif
2102#endif
2103
2104// Needed for floating point support, linker expects this symbol to be defined.
2105#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
2106 CONST INT32 _fltused = 0;
2107#endif
2108