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review.coreboot.org / coreboot / a81be27dc535f5177cf97ddd88458fa3946c125d / . / src / vendorcode / amd / agesa / f16kb / Config / PlatformInstall.h
blob: 686dfb153ab9792a0c175bde9ae1ace85cd9054b [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45/*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
50
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]51VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
52 //ModuleHeaderSignature
53 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
54 Int32FromChar ('0', '0', '0', '0'),
55 //ModuleIdentifier[8]
56 AGESA_ID,
57 //ModuleVersion[12]
58 AGESA_VERSION_STRING,
59 //ModuleDispatcher
60 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
61 //NextBlock
62 NULL
63};
64
Angel Pons64829162020-05-21 15:29:17 +0200[diff] [blame]65/* The default fixed MTRR values to be set after memory initialization */
66static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
67{
68 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
69 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
70 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
71 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
72 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
73 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
74 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
75 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
76 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
77 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
78 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
79 { CPU_LIST_TERMINAL },
80};
81
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]82/* Process solution defined socket / family installations
83 *
84 * As part of the release package for each image, define the options below to select the
85 * AGESA processor support included in that image.
86 */
87
88/* Default sockets to off */
89#define OPTION_FT3_SOCKET_SUPPORT FALSE
90
91/* Default families to off */
92#define OPTION_FAMILY15H_MODEL_1x FALSE
93#define OPTION_FAMILY16H_MODEL_0x FALSE
94
95
96/* Enable the appropriate socket support */
97
98#ifdef INSTALL_FT3_SOCKET_SUPPORT
99 #if INSTALL_FT3_SOCKET_SUPPORT == TRUE
100 #undef OPTION_FT3_SOCKET_SUPPORT
101 #define OPTION_FT3_SOCKET_SUPPORT TRUE
102 #endif
103#endif
104
105
106
107// F16_0x is supported in FT3
108#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
109 #if INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
110 #undef OPTION_FAMILY16H
111 #define OPTION_FAMILY16H TRUE
112 #undef OPTION_FAMILY16H_MODEL_0x
113 #define OPTION_FAMILY16H_MODEL_0x TRUE
114 #endif
115#endif
116
117/* Turn off families not required by socket designations */
118#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
119 #undef OPTION_FAMILY15H
120 #define OPTION_FAMILY15H FALSE
121#endif
122
123#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
124 #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
125 #undef OPTION_FAMILY16H_MODEL_0x
126 #define OPTION_FAMILY16H_MODEL_0x FALSE
127 #endif
128#endif
129
130
131#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
132 #undef OPTION_FAMILY16H
133 #define OPTION_FAMILY16H FALSE
134#endif
135
136
137#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
138 #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
139 #error No FT3 supported families included in the build
140 #endif
141#endif
142
143
144/* Process AGESA private data
145 *
146 * Turn on appropriate CPU models and memory controllers,
147 * as well as some other memory controls.
148 */
149
150/* Default all models to off */
151#define OPTION_FAMILY15H_TN FALSE
152#define OPTION_FAMILY16H_KB FALSE
153#define OPTION_FAMILY15H_UNKNOWN FALSE
154
155/* Default all memory controllers to off */
156#define OPTION_MEMCTLR_TN FALSE
157#define OPTION_MEMCTLR_KB FALSE
158
159/* Default all memory controls to off */
160#define OPTION_HW_WRITE_LEV_TRAINING FALSE
161#define OPTION_SW_WRITE_LEV_TRAINING FALSE
162#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
163#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
164#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
165#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
166#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
167#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
168#define OPTION_MAX_RD_LAT_TRAINING FALSE
169#define OPTION_HW_DRAM_INIT FALSE
170#define OPTION_SW_DRAM_INIT FALSE
171#define OPTION_S3_MEM_SUPPORT FALSE
172#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
173#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
174#define OPTION_RDDQS_2D_TRAINING FALSE
175#define OPTION_PRE_MEM_INIT FALSE
176#define OPTION_POST_MEM_INIT FALSE
177
178/* Defaults for public user options */
179#define OPTION_UDIMMS FALSE
180#define OPTION_RDIMMS FALSE
181#define OPTION_SODIMMS FALSE
182#define OPTION_LRDIMMS FALSE
183#define OPTION_DDR2 FALSE
184#define OPTION_DDR3 FALSE
185#define OPTION_ECC FALSE
186#define OPTION_BANK_INTERLEAVE FALSE
187#define OPTION_DCT_INTERLEAVE FALSE
188#define OPTION_NODE_INTERLEAVE FALSE
189#define OPTION_PARALLEL_TRAINING FALSE
190#define OPTION_ONLINE_SPARE FALSE
191#define OPTION_MEM_RESTORE FALSE
192#define OPTION_DIMM_EXCLUDE FALSE
193#define OPTION_AMP FALSE
194#define OPTION_DATA_EYE FALSE
195#define OPTION_AGGRESSOR FALSE
196
197/* Default all CPU controls to off */
198#define OPTION_MULTISOCKET FALSE
199#define OPTION_CRAT FALSE
200#define OPTION_CDIT FALSE
201#define OPTION_SRAT FALSE
202#define OPTION_SLIT FALSE
203#define OPTION_HT_ASSIST FALSE
204#define OPTION_ATM_MODE FALSE
205#define OPTION_NBR_CACHE FALSE
206#define OPTION_CPU_CORELEVELING FALSE
207#define OPTION_MSG_BASED_C1E FALSE
208#define OPTION_CPU_CFOH FALSE
209#define OPTION_C6_STATE FALSE
210#define OPTION_IO_CSTATE FALSE
211#define OPTION_CPB FALSE
212#define OPTION_CPU_APM FALSE
213#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
214#define OPTION_CPU_PSTATE_HPC_MODE FALSE
215#define OPTION_CPU_TDP_LIMITING FALSE
216#define OPTION_CPU_PSI FALSE
217#define OPTION_CPU_HTC FALSE
218#define OPTION_S3SCRIPT FALSE
219#define OPTION_GFX_RECOVERY FALSE
220#define OPTION_CPU_SCS FALSE
221#define OPTION_PREFETCH_MODE FALSE
222
223/* Default FCH controls to off */
224#define FCH_SUPPORT FALSE
225
226/* Enable all private controls based on socket/family enables */
227
228#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
229 #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
230 #undef FCH_SUPPORT
231 #define FCH_SUPPORT TRUE
232 #undef OPTION_FAMILY16H_KB
233 #define OPTION_FAMILY16H_KB TRUE
234 #undef OPTION_MEMCTLR_KB
235 #define OPTION_MEMCTLR_KB TRUE
236 #undef OPTION_HW_WRITE_LEV_TRAINING
237 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
238 #undef OPTION_CONTINOUS_PATTERN_GENERATION
239 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
240 #undef OPTION_HW_DQS_REC_EN_TRAINING
241 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
242 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
243 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
244 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
245 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
246 #undef OPTION_RDDQS_2D_TRAINING
247 #define OPTION_RDDQS_2D_TRAINING TRUE
248 #undef OPTION_MAX_RD_LAT_TRAINING
249 #define OPTION_MAX_RD_LAT_TRAINING TRUE
250 #undef OPTION_SW_DRAM_INIT
251 #define OPTION_SW_DRAM_INIT TRUE
252 #undef OPTION_S3_MEM_SUPPORT
253 #define OPTION_S3_MEM_SUPPORT TRUE
254 #undef OPTION_GFX_RECOVERY
255 #define OPTION_GFX_RECOVERY TRUE
256 #undef OPTION_CPU_CORELEVELING
257 #define OPTION_CPU_CORELEVELING TRUE
258 #undef OPTION_C6_STATE
259 #define OPTION_C6_STATE TRUE
260 #undef OPTION_IO_CSTATE
261 #define OPTION_IO_CSTATE TRUE
262 #undef OPTION_CPU_CFOH
263 #define OPTION_CPU_CFOH TRUE
264 #undef OPTION_CPU_APM
265 #define OPTION_CPU_APM TRUE
266 #undef OPTION_CPB
267 #define OPTION_CPB TRUE
268 #undef OPTION_CPU_HTC
269 #define OPTION_CPU_HTC TRUE
270 #undef OPTION_CPU_PSI
271 #define OPTION_CPU_PSI TRUE
272 #undef OPTION_CDIT
273 #define OPTION_CDIT TRUE
274 #undef OPTION_CRAT
275 #define OPTION_CRAT TRUE
276 #undef OPTION_CPU_SCS
277 #define OPTION_CPU_SCS TRUE
278 #undef OPTION_S3SCRIPT
279 #define OPTION_S3SCRIPT TRUE
280 ///@todo
281 //#undef OPTION_PREFETCH_MODE
282 //#define OPTION_PREFETCH_MODE TRUE
283 #undef OPTION_UDIMMS
284 #define OPTION_UDIMMS TRUE
285 #undef OPTION_SODIMMS
286 #define OPTION_SODIMMS TRUE
287 #undef OPTION_DDR3
288 #define OPTION_DDR3 TRUE
289 #undef OPTION_ECC
290 #define OPTION_ECC TRUE
291 #undef OPTION_BANK_INTERLEAVE
292 #define OPTION_BANK_INTERLEAVE TRUE
293 #undef OPTION_DCT_INTERLEAVE
294 #define OPTION_DCT_INTERLEAVE TRUE
295 #undef OPTION_MEM_RESTORE
296 #define OPTION_MEM_RESTORE TRUE
297 #undef OPTION_DIMM_EXCLUDE
298 #define OPTION_DIMM_EXCLUDE TRUE
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]299 #ifndef OPTION_MICROSERVER
300 #define OPTION_MICROSERVER FALSE
301 #endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]302 #endif
303#endif
304
305
306#if (OPTION_FAMILY16H_KB == TRUE)
307 #undef GNB_SUPPORT
308 #define GNB_SUPPORT TRUE
309#endif
310
311#define OPTION_ACPI_PSTATES TRUE
312#define OPTION_WHEA TRUE
313#define OPTION_DMI TRUE
314#define OPTION_EARLY_SAMPLES FALSE
315#define CFG_ACPI_PSTATES_PPC TRUE
316#define CFG_ACPI_PSTATES_PCT TRUE
317#define CFG_ACPI_PSTATES_PSD TRUE
318#define CFG_ACPI_PSTATES_PSS TRUE
319#define CFG_ACPI_PSTATES_XPSS TRUE
320#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
321#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
322#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
323#define OPTION_ALIB TRUE
324/*---------------------------------------------------------------------------
325 * Processing the options: Second, process the user's selections
326 *--------------------------------------------------------------------------*/
327#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
328 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
329 #undef OPTION_DDR3
330 #define OPTION_DDR3 FALSE
331 #endif
332#endif
333#if ((OPTION_DDR3 == FALSE))
334 #error BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
335#endif
336#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
337 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
338 #undef OPTION_MULTISOCKET
339 #define OPTION_MULTISOCKET FALSE
340 #endif
341#endif
342#ifdef BLDOPT_REMOVE_ECC_SUPPORT
343 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
344 #undef OPTION_ECC
345 #define OPTION_ECC FALSE
346 #endif
347#endif
348#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
349 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
350 #undef OPTION_UDIMMS
351 #define OPTION_UDIMMS FALSE
352 #endif
353#endif
354#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
355 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
356 #undef OPTION_RDIMMS
357 #define OPTION_RDIMMS FALSE
358 #endif
359#endif
360#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
361 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
362 #undef OPTION_SODIMMS
363 #define OPTION_SODIMMS FALSE
364 #endif
365#endif
366#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
367 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
368 #undef OPTION_LRDIMMS
369 #define OPTION_LRDIMMS FALSE
370 #endif
371#endif
372#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
373 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
374 #undef OPTION_BANK_INTERLEAVE
375 #define OPTION_BANK_INTERLEAVE FALSE
376 #endif
377#endif
378#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
379 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
380 #undef OPTION_DCT_INTERLEAVE
381 #define OPTION_DCT_INTERLEAVE FALSE
382 #endif
383#endif
384#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
385 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
386 #undef OPTION_NODE_INTERLEAVE
387 #define OPTION_NODE_INTERLEAVE FALSE
388 #endif
389#endif
390#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
391 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
392 #undef OPTION_PARALLEL_TRAINING
393 #define OPTION_PARALLEL_TRAINING FALSE
394 #endif
395#endif
396#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
397 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
398 #undef OPTION_ONLINE_SPARE
399 #define OPTION_ONLINE_SPARE FALSE
400 #endif
401#endif
402#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
403 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
404 #undef OPTION_MEM_RESTORE
405 #define OPTION_MEM_RESTORE FALSE
406 #endif
407#endif
408#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
409 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
410 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
411 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
412 #endif
413#endif
414#ifdef BLDOPT_REMOVE_ACPI_PSTATES
415 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
416 #undef OPTION_ACPI_PSTATES
417 #define OPTION_ACPI_PSTATES FALSE
418 #endif
419#endif
420#ifdef BLDOPT_REMOVE_CRAT
421 #if BLDOPT_REMOVE_CRAT == TRUE
422 #undef OPTION_CRAT
423 #define OPTION_CRAT FALSE
424 #endif
425#endif
426#ifdef BLDOPT_REMOVE_CDIT
427 #if BLDOPT_REMOVE_CDIT == TRUE
428 #undef OPTION_CDIT
429 #define OPTION_CDIT FALSE
430 #endif
431#endif
432#ifdef BLDOPT_REMOVE_SRAT
433 #if BLDOPT_REMOVE_SRAT == TRUE
434 #undef OPTION_SRAT
435 #define OPTION_SRAT FALSE
436 #endif
437#endif
438#ifdef BLDOPT_REMOVE_SLIT
439 #if BLDOPT_REMOVE_SLIT == TRUE
440 #undef OPTION_SLIT
441 #define OPTION_SLIT FALSE
442 #endif
443#endif
444#ifdef BLDOPT_REMOVE_WHEA
445 #if BLDOPT_REMOVE_WHEA == TRUE
446 #undef OPTION_WHEA
447 #define OPTION_WHEA FALSE
448 #endif
449#endif
450#ifdef BLDOPT_REMOVE_DMI
451 #if BLDOPT_REMOVE_DMI == TRUE
452 #undef OPTION_DMI
453 #define OPTION_DMI FALSE
454 #endif
455#endif
456#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
457 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
458 #undef OPTION_ADDR_TO_CS_TRANSLATOR
459 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
460 #endif
461#endif
462#ifdef BLDOPT_REMOVE_AMP_SUPPORT
463 #if BLDOPT_REMOVE_AMP_SUPPORT == TRUE
464 #undef OPTION_AMP
465 #define OPTION_AMP FALSE
466 #endif
467#endif
468
469#ifdef OPTION_RDDQS_2D_TRAINING
470 #if OPTION_RDDQS_2D_TRAINING == FALSE
471 #undef OPTION_DATA_EYE
472 #define OPTION_DATA_EYE FALSE
473 #else
474 #ifdef BLDOPT_REMOVE_DATA_EYE
475 #if BLDOPT_REMOVE_DATA_EYE == TRUE
476 #undef OPTION_DATA_EYE
477 #define OPTION_DATA_EYE FALSE
478 #endif
479 #endif
480 #endif
481#else
482 #undef OPTION_DATA_EYE
483 #define OPTION_DATA_EYE FALSE
484#endif
485
486#ifdef BLDOPT_REMOVE_HT_ASSIST
487 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
488 #undef OPTION_HT_ASSIST
489 #define OPTION_HT_ASSIST FALSE
490 #endif
491#endif
492
493#ifdef BLDOPT_REMOVE_ATM_MODE
494 #if BLDOPT_REMOVE_ATM_MODE == TRUE
495 #undef OPTION_ATM_MODE
496 #define OPTION_ATM_MODE FALSE
497 #endif
498#endif
499
500#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
501 #if BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
502 #undef OPTION_NBR_CACHE
503 #define OPTION_NBR_CACHE FALSE
504 #endif
505#endif
506
507#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
508 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
509 #undef OPTION_MSG_BASED_C1E
510 #define OPTION_MSG_BASED_C1E FALSE
511 #endif
512#endif
513
514#ifdef BLDOPT_REMOVE_C6_STATE
515 #if BLDOPT_REMOVE_C6_STATE == TRUE
516 #undef OPTION_C6_STATE
517 #define OPTION_C6_STATE FALSE
518 #endif
519#endif
520
521#ifdef BLDOPT_REMOVE_GFX_RECOVERY
522 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
523 #undef OPTION_GFX_RECOVERY
524 #define OPTION_GFX_RECOVERY FALSE
525 #endif
526#endif
527
528#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
529 #if BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
530 #undef OPTION_RDDQS_2D_TRAINING
531 #define OPTION_RDDQS_2D_TRAINING FALSE
532 #endif
533#endif
534
535#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
536 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
537 #undef CFG_ACPI_PSTATES_PPC
538 #define CFG_ACPI_PSTATES_PPC FALSE
539 #endif
540#endif
541
542#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
543 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
544 #undef CFG_ACPI_PSTATES_PCT
545 #define CFG_ACPI_PSTATES_PCT FALSE
546 #endif
547#endif
548
549#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
550 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
551 #undef CFG_ACPI_PSTATES_PSD
552 #define CFG_ACPI_PSTATES_PSD FALSE
553 #endif
554#endif
555
556#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
557 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
558 #undef CFG_ACPI_PSTATES_PSS
559 #define CFG_ACPI_PSTATES_PSS FALSE
560 #endif
561#endif
562
563#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
564 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
565 #undef CFG_ACPI_PSTATES_XPSS
566 #define CFG_ACPI_PSTATES_XPSS FALSE
567 #endif
568#endif
569
570#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
571 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
572 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
573 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
574 #endif
575#endif
576
577#ifdef BLDOPT_REMOVE_AGGRESSOR
578 #if BLDOPT_REMOVE_AGGRESSOR == TRUE
579 #undef OPTION_AGGRESSOR
580 #define OPTION_AGGRESSOR FALSE
581 #endif
582#endif
583
584#ifdef BLDCFG_PSTATE_HPC_MODE
585 #if BLDCFG_PSTATE_HPC_MODE == TRUE
586 #undef OPTION_CPU_PSTATE_HPC_MODE
587 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
588 #endif
589#endif
590
591#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
592 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
593 #undef CFG_ACPI_PSTATE_PSD_INDPX
594 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
595 #endif
596#endif
597
598#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
599 #define CFG_ACPI_PSTATES_PSD_POLICY (BLDCFG_ACPI_PSTATES_PSD_POLICY)
600#else
601 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
602#endif
603
604#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
605 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
606 #undef CFG_VRM_HIGH_SPEED_ENABLE
607 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
608 #endif
609#endif
610
611#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
612 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
613 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
614 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
615 #endif
616#endif
617
618#ifdef BLDCFG_STARTING_BUSNUM
619 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
620#else
621 #define CFG_STARTING_BUSNUM (0)
622#endif
623
624#ifdef BLDCFG_AMD_PLATFORM_TYPE
625 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
626#else
627 #define CFG_AMD_PLATFORM_TYPE 0
628#endif
629
630CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
631
632#ifdef BLDCFG_MAXIMUM_BUSNUM
633 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
634#else
635 #define CFG_MAXIMUM_BUSNUM (0xF8)
636#endif
637
638#ifdef BLDCFG_ALLOCATED_BUSNUM
639 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
640#else
641 #define CFG_ALLOCATED_BUSNUM (0x20)
642#endif
643
644#ifdef BLDCFG_BUID_SWAP_LIST
645 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
646#else
647 #define CFG_BUID_SWAP_LIST (NULL)
648#endif
649
650#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
651 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
652#else
653 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
654#endif
655
656#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
657 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
658#else
659 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
660#endif
661
662#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
663 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
664#else
665 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
666#endif
667
668#ifdef BLDCFG_BUS_NUMBERS_LIST
669 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
670#else
671 #define CFG_BUS_NUMBERS_LIST (NULL)
672#endif
673
674#ifdef BLDCFG_IGNORE_LINK_LIST
675 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
676#else
677 #define CFG_IGNORE_LINK_LIST (NULL)
678#endif
679
680#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
681 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
682#else
683 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
684#endif
685
686#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
687 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
688#else
689 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
690#endif
691
692#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
693 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
694#else
695 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
696#endif
697
698#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
699 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
700#else
701 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
702#endif
703
704#ifdef BLDCFG_USE_HT_ASSIST
705 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
706#else
707 #define CFG_USE_HT_ASSIST (TRUE)
708#endif
709
710#ifdef BLDCFG_USE_ATM_MODE
711 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
712#else
713 #define CFG_USE_ATM_MODE (TRUE)
714#endif
715
716#ifdef BLDCFG_USE_NEIGHBOR_CACHE
717 #define CFG_USE_NBR_CACHE (BLDCFG_USE_NEIGHBOR_CACHE)
718#else
719 #define CFG_USE_NBR_CACHE (TRUE)
720#endif
721
722#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
723 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
724#else
725 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
726#endif
727
728#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
729 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
730#else
731 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
732#endif
733
734#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
735 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
736#else
737 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
738#endif
739
740#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
741 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
742#else
743 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
744#endif
745
746#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
747 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
748#else
749 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
750#endif
751
752#ifdef BLDCFG_VRM_CURRENT_LIMIT
753 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
754#else
755 #define CFG_VRM_CURRENT_LIMIT 0
756#endif
757
758#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
759 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
760#else
761 #define CFG_VRM_LOW_POWER_THRESHOLD 0
762#endif
763
764#ifdef BLDCFG_VRM_SLEW_RATE
765 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
766#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]767 #define CFG_VRM_SLEW_RATE (5000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]768#endif
769
770#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
771 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
772#else
773 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
774#endif
775
776#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
777 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
778#else
779 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
780#endif
781
782#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
783 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
784#else
785 #define CFG_VRM_SVI_OCP_LEVEL 0
786#endif
787
788#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
789 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
790#else
791 #define CFG_VRM_NB_SVI_OCP_LEVEL 0
792#endif
793
794#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
795 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
796#else
797 #define CFG_VRM_NB_CURRENT_LIMIT (0)
798#endif
799
800#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
801 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
802#else
803 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
804#endif
805
806#ifdef BLDCFG_VRM_NB_SLEW_RATE
807 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
808#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]809 #define CFG_VRM_NB_SLEW_RATE (5000)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]810#endif
811
812#ifdef BLDCFG_PLAT_NUM_IO_APICS
813 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
814#else
815 #define CFG_PLAT_NUM_IO_APICS 0
816#endif
817
818#ifdef BLDCFG_MEM_INIT_PSTATE
819 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
820#else
821 #define CFG_MEM_INIT_PSTATE 0
822#endif
823
824#ifdef BLDCFG_PLATFORM_C1E_MODE
825 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
826#else
827 #define CFG_C1E_MODE C1eModeDisabled
828#endif
829
830#ifdef BLDCFG_PLATFORM_C1E_OPDATA
831 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
832#else
833 #define CFG_C1E_OPDATA 0
834#endif
835
836#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
837 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
838#else
839 #define CFG_C1E_OPDATA1 0
840#endif
841
842#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
843 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
844#else
845 #define CFG_C1E_OPDATA2 0
846#endif
847
848#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
849 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
850#else
851 #define CFG_C1E_OPDATA3 0
852#endif
853
854#ifdef BLDCFG_PLATFORM_CSTATE_MODE
855 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
856#else
857 #define CFG_CSTATE_MODE CStateModeC6
858#endif
859
860#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
861 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
862#else
863 #define CFG_CSTATE_OPDATA 0
864#endif
865
866#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
867 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
868#else
869 #define CFG_CSTATE_IO_BASE_ADDRESS 0
870#endif
871
872#ifdef BLDCFG_PLATFORM_CPB_MODE
873 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
874#else
875 #define CFG_CPB_MODE CpbModeAuto
876#endif
877
878#ifdef BLDCFG_CORE_LEVELING_MODE
879 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
880#else
881 #define CFG_CORE_LEVELING_MODE 0
882#endif
883
884#ifdef BLDCFG_AMD_TDP_LIMIT
885 #define CFG_AMD_POWER_CEILING BLDCFG_AMD_TDP_LIMIT
886#else
887 #define CFG_AMD_POWER_CEILING 0
888#endif
889
890#ifdef BLDCFG_HEAP_DRAM_ADDRESS
891 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
892#else
893 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
894#endif
895
896#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
897 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
898#else
899 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
900#endif
901
902#ifdef BLDCFG_MEMORY_MODE_UNGANGED
903 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
904#else
905 #define CFG_MEMORY_MODE_UNGANGED TRUE
906#endif
907
908#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
909 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
910#else
911 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
912#endif
913
914#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
915 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
916#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]917 #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]918#endif
919
920#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
921 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
922#else
923 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
924#endif
925
926#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
927 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
928#else
929 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
930#endif
931
932#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
933 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
934#else
935 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
936#endif
937
938#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
939 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
940#else
941 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
942#endif
943
944#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
945 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
946#else
947 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
948#endif
949
950#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
951 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
952#else
953 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
954#endif
955
956#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
957 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
958#else
959 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
960#endif
961
962#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
963 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
964#else
965 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
966#endif
967
968#ifdef BLDCFG_MEMORY_POWER_DOWN
969 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
970#else
971 #define CFG_MEMORY_POWER_DOWN FALSE
972#endif
973
974#ifdef BLDCFG_POWER_DOWN_MODE
975 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
976#else
977 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
978#endif
979
980#ifdef BLDCFG_ONLINE_SPARE
981 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
982#else
983 #define CFG_ONLINE_SPARE FALSE
984#endif
985
986#ifdef BLDCFG_MEMORY_PARITY_ENABLE
987 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
988#else
989 #define CFG_MEMORY_PARITY_ENABLE FALSE
990#endif
991
992#ifdef BLDCFG_BANK_SWIZZLE
993 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
994#else
995 #define CFG_BANK_SWIZZLE TRUE
996#endif
997
998#ifdef BLDCFG_TIMING_MODE_SELECT
999 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1000#else
1001 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1002#endif
1003
1004#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1005 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1006#else
1007 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1008#endif
1009
1010#ifdef BLDCFG_DQS_TRAINING_CONTROL
1011 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1012#else
1013 #define CFG_DQS_TRAINING_CONTROL TRUE
1014#endif
1015
1016#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1017 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1018#else
1019 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1020#endif
1021
1022#ifdef BLDCFG_USE_BURST_MODE
1023 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1024#else
1025 #define CFG_USE_BURST_MODE FALSE
1026#endif
1027
1028#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1029 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1030#else
1031 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1032#endif
1033
1034#ifdef BLDCFG_ENABLE_ECC_FEATURE
1035 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1036#else
1037 #define CFG_ENABLE_ECC_FEATURE TRUE
1038#endif
1039
1040#ifdef BLDCFG_ECC_REDIRECTION
1041 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1042#else
1043 #define CFG_ECC_REDIRECTION FALSE
1044#endif
1045
1046#ifdef BLDCFG_SCRUB_DRAM_RATE
1047 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1048#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1049 #define CFG_SCRUB_DRAM_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1050#endif
1051
1052#ifdef BLDCFG_SCRUB_L2_RATE
1053 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1054#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1055 #define CFG_SCRUB_L2_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1056#endif
1057
1058#ifdef BLDCFG_SCRUB_L3_RATE
1059 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1060#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1061 #define CFG_SCRUB_L3_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1062#endif
1063
1064#ifdef BLDCFG_SCRUB_IC_RATE
1065 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1066#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1067 #define CFG_SCRUB_IC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1068#endif
1069
1070#ifdef BLDCFG_SCRUB_DC_RATE
1071 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1072#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]1073 #define CFG_SCRUB_DC_RATE (0)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1074#endif
1075
1076#ifdef BLDCFG_ECC_SYNC_FLOOD
1077 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1078#else
1079 #define CFG_ECC_SYNC_FLOOD TRUE
1080#endif
1081
1082#ifdef BLDCFG_ECC_SYMBOL_SIZE
1083 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1084#else
1085 #define CFG_ECC_SYMBOL_SIZE 0
1086#endif
1087
1088#ifdef BLDCFG_1GB_ALIGN
1089 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1090#else
1091 #define CFG_1GB_ALIGN FALSE
1092#endif
1093
1094#ifdef BLDCFG_UMA_ALLOCATION_MODE
1095 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1096#else
1097 #define CFG_UMA_MODE UMA_AUTO
1098#endif
1099
1100#ifdef BLDCFG_FORCE_TRAINING_MODE
1101 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1102#else
1103 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1104#endif
1105
1106#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1107 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1108#else
1109 #define CFG_UMA_SIZE 0
1110#endif
1111
1112#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1113 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1114#else
1115 #define CFG_UMA_ABOVE4G FALSE
1116#endif
1117
1118#ifdef BLDCFG_UMA_ALIGNMENT
1119 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1120#else
1121 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1122#endif
1123
1124#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1125 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1126#else
1127 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG DDR3_TECHNOLOGY
1128#endif
1129
1130#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1131 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1132#else
1133 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1134#endif
1135
1136#ifdef BLDCFG_S3_LATE_RESTORE
1137 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1138#else
1139 #define CFG_S3_LATE_RESTORE TRUE
1140#endif
1141
1142#ifdef BLDCFG_USE_32_BYTE_REFRESH
1143 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1144#else
1145 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1146#endif
1147
1148#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1149 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1150#else
1151 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1152#endif
1153
1154#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1155 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1156#else
1157 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1158#endif
1159
1160#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1161 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1162#else
1163 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1164#endif
1165
1166#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1167 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1168#else
1169 #define CFG_GNB_HD_AUDIO TRUE
1170#endif
1171
1172#ifdef BLDCFG_CFG_ABM_SUPPORT
1173 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1174#else
1175 #define CFG_ABM_SUPPORT FALSE
1176#endif
1177
1178#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1179 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1180#else
1181 #define CFG_DYNAMIC_REFRESH_RATE 0
1182#endif
1183
1184#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1185 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1186#else
1187 #define CFG_LCD_BACK_LIGHT_CONTROL 200
1188#endif
1189
1190#ifdef BLDCFG_STEREO_3D_PINOUT
1191 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1192#else
1193 #define CFG_GNB_STEREO_3D_PINOUT 0
1194#endif
1195
1196#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1197 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1198#else
1199 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1200#endif
1201
1202// Define pin configuration for SYNCFLOOD
1203// Default to FALSE (Use pin as SYNCFLOOD)
1204#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
1205 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
1206#else
1207 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
1208#endif
1209
1210#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1211 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1212#else
1213 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
1214#endif
1215
1216#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1217 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1218#else
1219 #define CFG_GNB_IGPU_SSID 0
1220#endif
1221
1222#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1223 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1224#else
1225 #define CFG_GNB_HDAUDIO_SSID 0
1226#endif
1227
1228#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1229 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1230#else
1231 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
1232#endif
1233
1234#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1235 #define CFG_GNB_PCIE_SSID BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1236#else
1237 #define CFG_GNB_PCIE_SSID 0x12341022ul
1238#endif
1239
1240#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1241 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1242#else
1243 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1244#endif
1245
1246#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1247 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1248#else
1249 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1250#endif
1251
1252#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1253 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1254#else
1255 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1256#endif
1257
1258#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1259 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1260#else
1261 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
1262#endif
1263
1264#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1265 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1266#else
1267 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1268#endif
1269
1270#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1271 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1272 #undef OPTION_EARLY_SAMPLES
1273 #define OPTION_EARLY_SAMPLES FALSE
1274 #else
1275 #undef OPTION_EARLY_SAMPLES
1276 #define OPTION_EARLY_SAMPLES TRUE
1277 #endif
1278#endif
1279
1280#ifdef BLDOPT_REMOVE_ALIB
1281 #if BLDOPT_REMOVE_ALIB == TRUE
1282 #undef OPTION_ALIB
1283 #define OPTION_ALIB FALSE
1284 #else
1285 #undef OPTION_ALIB
1286 #define OPTION_ALIB TRUE
1287 #endif
1288#endif
1289
1290#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1291 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1292 #undef FCH_SUPPORT
1293 #define FCH_SUPPORT FALSE
1294 #endif
1295#endif
1296
1297#ifdef BLDCFG_IOMMU_SUPPORT
1298 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1299#else
1300 #define CFG_IOMMU_SUPPORT TRUE
1301#endif
1302
1303#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1304 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1305#else
1306 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1307#endif
1308
1309#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1310 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1311#else
1312 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1313#endif
1314
1315#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1316 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1317#else
1318 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1319#endif
1320
1321#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1322 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1323#else
1324 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1325#endif
1326
1327#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1328 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1329#else
1330 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1331#endif
1332
1333#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1334 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1335#else
1336 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1337#endif
1338
1339#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1340 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1341#else
1342 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1343#endif
1344
1345#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1346 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1347#else
1348 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1349#endif
1350
1351#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1352 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1353#else
1354 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1355#endif
1356
1357
1358// BLDCFG_LVDS_24BBP_PANEL_MODE
1359// This specifies the LVDS 24 BBP mode.
1360// 0 - Use LDI mode (default).
1361// 1 - Use FPDI mode.
1362#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1363 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1364#else
1365 #define CFG_LVDS_24BBP_PANEL_MODE 0
1366#endif
1367
1368#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1369 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1370#else
1371 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1372#endif
1373
1374#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1375 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1376#else
1377 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1378#endif
1379
1380#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1381 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1382#else
1383 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1384#endif
1385
1386#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1387 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1388#else
1389 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1390#endif
1391
1392#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1393 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1394#else
1395 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1396#endif
1397
1398#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1399 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1400#else
1401 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
1402#endif
1403
1404#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1405 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1406#else
1407 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
1408#endif
1409
1410#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1411 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1412#else
1413 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
1414#endif
1415
1416#ifdef BLDCFG_DP_FIXED_VOLT_SWING
1417 #define CFG_DP_FIXED_VOLT_SWING BLDCFG_DP_FIXED_VOLT_SWING
1418#else
1419 #define CFG_DP_FIXED_VOLT_SWING 0
1420#endif
1421
1422#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1423 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1424#else
1425 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1426#endif
1427
1428#ifdef BLDCFG_NB_PSTATES_SUPPORTED
1429 #define CFG_NB_PSTATES_SUPPORTED (BLDCFG_NB_PSTATES_SUPPORTED)
1430#else
1431 #define CFG_NB_PSTATES_SUPPORTED (TRUE)
1432#endif
1433
1434#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
1435 #define CFG_HTC_TEMPERATURE_LIMIT (BLDCFG_HTC_TEMPERATURE_LIMIT)
1436#else
1437 #define CFG_HTC_TEMPERATURE_LIMIT (0)
1438#endif
1439
1440#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
1441 #define CFG_LHTC_TEMPERATURE_LIMIT (BLDCFG_LHTC_TEMPERATURE_LIMIT)
1442#else
1443 #define CFG_LHTC_TEMPERATURE_LIMIT (0)
1444#endif
1445
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1446#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1447
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1448#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1449
1450#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1451 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1452#else
Angel Pons64829162020-05-21 15:29:17 +0200[diff] [blame]1453 #define CFG_AP_MTRR_SETTINGS_LIST (KabiniApMtrrSettingsList)
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1454#endif
1455
1456#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
1457 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
1458#else
1459 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
1460#endif
1461
1462#ifdef BLDCFG_HYBRID_BOOST_ENABLE
1463 #define CFG_HYBRID_BOOST_ENABLE BLDCFG_HYBRID_BOOST_ENABLE
1464#else
1465 #define CFG_HYBRID_BOOST_ENABLE TRUE
1466#endif
1467
1468#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
1469 #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
1470#else
1471 #define CFG_GNB_IOAPIC_ADDRESS NULL
1472#endif
1473
1474#ifdef BLDCFG_GNB_IOMMU_ADDRESS
1475 #define CFG_GNB_IOMMU_ADDRESS BLDCFG_GNB_IOMMU_ADDRESS
1476#else
1477 #define CFG_GNB_IOMMU_ADDRESS NULL
1478#endif
1479
1480#ifdef BLDCFG_ENABLE_DATA_EYE
1481 #define CFG_ENABLE_DATA_EYE BLDCFG_ENABLE_DATA_EYE
1482#else
1483 #define CFG_ENABLE_DATA_EYE TRUE
1484#endif
1485
1486#ifdef BLDCFG_ACPI_SET_OEM_ID
1487 #define CFG_ACPI_SET_OEM_ID BLDCFG_ACPI_SET_OEM_ID
1488#else
1489 #define CFG_ACPI_SET_OEM_ID 'A','M','D',' ',' ',' '
1490#endif
1491
1492#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
1493 #define CFG_ACPI_SET_OEM_TABLE_ID BLDCFG_ACPI_SET_OEM_TABLE_ID
1494#else
1495 #define CFG_ACPI_SET_OEM_TABLE_ID 'A','G','E','S','A',' ',' ',' '
1496#endif
1497
1498#ifdef BLDCFG_DOCKED_TDP_HEADROOM
1499 #define CFG_DOCKED_TDP_HEADROOM BLDCFG_DOCKED_TDP_HEADROOM
1500#else
1501 #define CFG_DOCKED_TDP_HEADROOM TRUE
1502#endif
1503
1504#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1505 #define CFG_DRAM_DOUBLE_REFRESH_RATE BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1506#else
1507 #define CFG_DRAM_DOUBLE_REFRESH_RATE FALSE
1508#endif
1509
1510/*---------------------------------------------------------------------------
1511 * Processing the options: Third, perform the option cross checks
1512 *--------------------------------------------------------------------------*/
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1513// Check that deprecated options are not used
1514#ifdef BLDCFG_PCI_MMIO_BASE
1515 #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use!
1516#endif
1517#ifdef BLDCFG_PCI_MMIO_SIZE
1518 #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use!
1519#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1520// Assure that at least one type of memory support is included
1521#if OPTION_UDIMMS == FALSE
1522 #if OPTION_RDIMMS == FALSE
1523 #if OPTION_SODIMMS == FALSE
1524 #if OPTION_LRDIMMS == FALSE
1525 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1526 #endif
1527 #endif
1528 #endif
1529#endif
1530// Ensure at least one dimm type is capable
1531#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1532 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1533 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1534 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1535 #error BLDCFG: No dimm type is capable
1536 #endif
1537 #endif
1538 #endif
1539#endif
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1540// Turn off multi-socket based features if only one node...
1541#if OPTION_MULTISOCKET == FALSE
1542 #undef OPTION_PARALLEL_TRAINING
1543 #define OPTION_PARALLEL_TRAINING FALSE
1544 #undef OPTION_NODE_INTERLEAVE
1545 #define OPTION_NODE_INTERLEAVE FALSE
1546#endif
1547// Ensure the frequency limit is valid
1548#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
1549 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
1550 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
1551 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
1552 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
1553 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
1554 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
1555 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
1556 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
1557 #error BLDCFG: Unsupported memory bus frequency
1558 #endif
1559 #endif
1560 #endif
1561 #endif
1562 #endif
1563 #endif
1564 #endif
1565 #endif
1566#endif
1567// Ensure timing mode is valid
1568#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1569 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1570 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1571 #error BLDCFG: Invalid timing mode is set
1572 #endif
1573 #endif
1574#endif
1575// Ensure the scrub rate is valid
1576#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1577 #error BLDCFG: Unsupported dram scrub rate set
1578#endif
1579#if CFG_SCRUB_L2_RATE > 0x16
1580 #error BLDCFG: Unsupported L2 scrubber rate set
1581#endif
1582#if CFG_SCRUB_L3_RATE > 0x16
1583 #error BLDCFG: unsupported L3 scrubber rate set
1584#endif
1585#if CFG_SCRUB_IC_RATE > 0x16
1586 #error BLDCFG: Unsupported Instruction cache scrub rate set
1587#endif
1588#if CFG_SCRUB_DC_RATE > 0x16
1589 #error BLDCFG: Unsupported Dcache scrub rate set
1590#endif
1591// Ensure Quad rank dimm type is valid
1592#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1593 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1594 #error BLDCFG: Invalid quad rank dimm type set
1595 #endif
1596#endif
1597// Ensure ECC symbol size is valid
1598#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1599 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1600 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1601 #error BLDCFG: Invalid Ecc symbol size set
1602 #endif
1603 #endif
1604#endif
1605// Ensure power down mode is valid
1606#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1607 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1608 #if AGESA_ENTRY_INIT_POST == TRUE
1609 #error BLDCFG: Invalid power down mode set
1610 #endif
1611 #endif
1612#endif
1613
1614// Ensure P-state dependence settings do not conflict
1615#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1616 #error BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
1617#endif
1618
1619#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
1620 #error BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
1621#endif
1622
1623#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
1624 #error BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
1625#endif
1626
1627
1628
1629/*****************************************************************************
1630 *
1631 * Process the option logic, setting local control variables
1632 *
1633 ****************************************************************************/
1634#if OPTION_ACPI_PSTATES == TRUE
1635 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1636 #define OPTFCN_GATHER_DATA PStateGatherData
1637 #if OPTION_MULTISOCKET == TRUE
1638 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1639 #else
1640 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1641 #endif
1642#else
1643 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1644 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1645 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1646#endif
1647
1648// Consolidate P-state dependence setings
1649#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1650 #undef CFG_ACPI_PSTATES_PSD_POLICY
1651 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyIndependent
1652#endif
1653
1654/*****************************************************************************
1655 *
1656 * Include the structure definitions for the defaults table structures
1657 *
1658 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1659#include <CommonReturns.h>
1660#include <agesa-entry-cfg.h>
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1661#include "Options.h"
1662#include "OptionCpuFamiliesInstall.h"
1663#include "OptionsHt.h"
1664#include "OptionHtInstall.h"
1665#include "OptionMemory.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1666#include "OptionMemoryInstall.h"
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1667#include "OptionCpuFeaturesInstall.h"
1668#include "OptionDmi.h"
1669#include "OptionDmiInstall.h"
1670#include "OptionPstate.h"
1671#include "OptionPstateInstall.h"
1672#include "OptionWhea.h"
1673#include "OptionWheaInstall.h"
1674#include "OptionCrat.h"
1675#include "OptionCratInstall.h"
1676#include "OptionCdit.h"
1677#include "OptionCditInstall.h"
1678#include "OptionSrat.h"
1679#include "OptionSratInstall.h"
1680#include "OptionSlit.h"
1681#include "OptionSlitInstall.h"
1682#include "OptionMultiSocket.h"
1683#include "OptionMultiSocketInstall.h"
1684#include "OptionIdsInstall.h"
1685#include "OptionGfxRecovery.h"
1686#include "OptionGfxRecoveryInstall.h"
1687#include "OptionGnb.h"
1688#include "OptionGnbInstall.h"
1689#include "OptionS3ScriptInstall.h"
1690#include "OptionFchInstall.h"
1691#include "OptionMmioMapInstall.h"
1692#include "OptionPrefetchModeInstall.h"
1693
1694
1695/*****************************************************************************
1696 *
1697 * Generate the output structures (defaults tables)
1698 *
1699 ****************************************************************************/
1700
1701FCH_PLATFORM_POLICY FchUserOptions = {
1702 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
1703 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
1704 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
1705 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
1706 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
1707 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
1708 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
1709 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
1710 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
1711 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
1712 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
1713 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
1714 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
1715 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
1716 0x780D1022ul,
1717 CFG_SMBUS_SSID, // CfgSmbusSsid
1718 CFG_IDE_SSID, // CfgIdeSsid
1719 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
1720 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
1721 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
1722 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
1723 CFG_EHCI_SSID, // CfgEhcidSsid
1724 CFG_OHCI_SSID, // CfgOhcidSsid
1725 CFG_LPC_SSID, // CfgLpcSsid
1726 CFG_SD_SSID, // CfgSdSsid
1727 CFG_XHCI_SSID, // CfgXhciSsid
1728 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
1729 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
1730 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
1731 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
1732 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
1733 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
1734 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
1735 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
1736 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
1737 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
1738 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
1739
1740 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
1741 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
1742 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
1743 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
1744 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]1745 CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl
1746 CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1747};
1748
1749BUILD_OPT_CFG UserOptions = {
1750 { // AGESA version string
1751 AGESA_CODE_SIGNATURE, // code header Signature
1752 AGESA_PACKAGE_STRING, // 16 character ID
1753 AGESA_VERSION_STRING, // 12 character version string
1754 0 // null string terminator
1755 },
1756 //Build Option Area
1757 OPTION_UDIMMS, //UDIMMS
1758 OPTION_RDIMMS, //RDIMMS
1759 OPTION_LRDIMMS, //LRDIMMS
1760 OPTION_ECC, //ECC
1761 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1762 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1763 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1764 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1765 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1766 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1767 OPTION_MULTISOCKET, //MULTISOCKET
1768 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1769 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
1770 OPTION_CRAT, //CRAT
1771 OPTION_CDIT, //CDIT
1772 OPTION_SRAT, //SRAT
1773 OPTION_SLIT, //SLIT
1774 OPTION_WHEA, //WHEA
1775 OPTION_DMI, //DMI
1776 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1777 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1778
1779 //Build Configuration Area
1780 CFG_PCI_MMIO_BASE,
1781 CFG_PCI_MMIO_SIZE,
1782 {
1783 // CoreVrm
1784 {
1785 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1786 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1787 CFG_VRM_SLEW_RATE, // VrmSlewRate
1788 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1789 CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmMaximumCurrentLimit
1790 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
1791 },
1792 // NbVrm
1793 {
1794 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1795 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1796 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1797 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1798 CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbMaximumCurrentLimit
1799 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
1800 }
1801 },
1802 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1803 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1804 CFG_C1E_MODE, //C1eMode
1805 CFG_C1E_OPDATA, //C1ePlatformData
1806 CFG_C1E_OPDATA1, //C1ePlatformData1
1807 CFG_C1E_OPDATA2, //C1ePlatformData2
1808 CFG_C1E_OPDATA3, //C1ePlatformData3
1809 CFG_CSTATE_MODE, //CStateMode
1810 CFG_CSTATE_OPDATA, //CStatePlatformData
1811 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1812 CFG_CPB_MODE, //CpbMode
1813 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
1814 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1815 {
1816 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1817 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1818 CFG_USE_ATM_MODE, // CfgUseAtmMode
1819 CFG_USE_NBR_CACHE, // CfgUseNbrCache
1820 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1821 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1822 // ADVANCED_PERFORMANCE_PROFILE
1823 {
1824 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
1825 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
1826 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
1827 },
1828 CFG_PLATFORM_POWER_POLICY_MODE, // The platform's power policy mode.
1829 CFG_NB_PSTATES_SUPPORTED // The Nb-Pstates is supported or not
1830 },
1831 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1832 CFG_AMD_PLATFORM_TYPE, // CfgAmdPlatformType
1833 CFG_AMD_POWER_CEILING, // CfgAmdPowerCeiling
1834 CFG_HTC_TEMPERATURE_LIMIT, // CfgHtcTemperatureLimit
1835 CFG_LHTC_TEMPERATURE_LIMIT, // CfgLhtcTemperatureLimit
1836
1837 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1838 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1839 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1840 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1841 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1842 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1843 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1844 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1845 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
1846 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1847 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1848 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1849 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1850 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1851 CFG_ONLINE_SPARE, // CfgOnlineSpare
1852 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1853 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1854 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1855 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1856 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1857 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1858 CFG_USE_BURST_MODE, // CfgUseBurstMode
1859 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1860 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1861 CFG_ECC_REDIRECTION, // CfgEccRedirection
1862 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1863 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1864 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1865 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1866 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1867 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1868 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1869 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1870 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1871 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1872 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1873 CFG_ACPI_PSTATES_PSD_POLICY, // CfgAcpiPstatesPsdPolicy
1874 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1875 CFG_UMA_MODE, // CfgUmaMode
1876 CFG_UMA_SIZE, // CfgUmaSize
1877 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1878 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1879 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1880 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1881 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1882 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1883 CFG_ABM_SUPPORT, // CfgAbmSupport
1884 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1885 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1886 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1887 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1888 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1889 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1890 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1891 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1892 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1893
1894 &FchUserOptions, // FchBldCfg
1895
1896 CFG_IOMMU_SUPPORT, // CfgIommuSupport
1897 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
1898 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
1899 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
1900 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
1901 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
1902 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
1903 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
1904 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
1905 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
1906 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
1907 {{
1908 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1909 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1910 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1911 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1912 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1913 CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl
1914 }},
1915 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
1916 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
1917 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
1918 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
1919 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
1920 CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi
1921 CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy
1922 CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset
1923 CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment
1924 {{
1925 0, // Reserved
1926 CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
1927 0, // Reserved
1928 }},
1929 CFG_DP_FIXED_VOLT_SWING, // CfgDpFixedVoltSwingType
1930 CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG, // CfgDimmTypeUsedInMixedConfig
1931 CFG_HYBRID_BOOST_ENABLE, // CfgHybridBoostEnable
1932 CFG_GNB_IOAPIC_ADDRESS, // CfgGnbIoapicAddress
1933 CFG_ENABLE_DATA_EYE, // CfgDataEyeEn
1934 CFG_DOCKED_TDP_HEADROOM, // CfgDockedTdpHeadroom
1935 CFG_DRAM_DOUBLE_REFRESH_RATE, // CfgDramDoubleRefreshRateEn
1936 0, //reserved...
1937};
1938
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1939CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1940{
1941 IDS_LATE_RUN_AP_TASK
1942 // Get DMI info
1943 CPU_DMI_AP_GET_TYPE4_TYPE7
1944 // Probe filter enable
1945 L3_FEAT_AP_DISABLE_CACHE
1946 L3_FEAT_AP_ENABLE_CACHE
1947 // Cpu Prefetch Mode
1948 CPU_PREFETCH_MODE_AP_TASK
1949 { 0, NULL }
1950};
1951
1952#if AGESA_ENTRY_INIT_EARLY == TRUE
1953 #if IDSOPT_IDS_ENABLED == TRUE
1954 #if IDSOPT_TRACING_ENABLED == TRUE
1955 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1956 CONST CHAR8 *BldOptDebugOutput[] = {
1957 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1958 //Build Option Area
1959 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1960 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1961 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1962 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1963 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1964 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1965 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1966 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1967 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1968 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1969 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1970 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1971 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1972 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1973 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1974 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1975 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1976 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1977
1978 //Build Configuration Area
1979 // CoreVrm
1980 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1981 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1982 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1983 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1984 MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
1985 MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL)
1986 // NbVrm
1987 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1988 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1989 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1990 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1991 MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
1992 MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL)
1993
1994 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1995 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1996 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
1997 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
1998 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
1999 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2000 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
2001 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2002 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2003 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2004 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2005 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2006
2007 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2008 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2009 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2010 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2011 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2012 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2013
2014 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2015
2016 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2017 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2018 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2019 MAKE_DBG_STR (\nPowerCeiling , CFG_AMD_POWER_CEILING),
2020 MAKE_DBG_STR (\nHtcTempLimit , CFG_HTC_TEMPERATURE_LIMIT)
2021 MAKE_DBG_STR (\nLhtcTempLimit , CFG_LHTC_TEMPERATURE_LIMIT)
2022
2023 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2024 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2025 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2026
2027 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2028 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2029 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2030 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2031 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2032 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2033 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2034 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2035 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2036 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2037 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2038
2039 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2040 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2041 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2042 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2043 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2044 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2045 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2046 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2047 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2048
2049 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2050 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2051 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2052 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2053
2054 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2055 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2056 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2057 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2058 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2059 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2060 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2061 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2062 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2063 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2064 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2065
2066 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2067 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2068 MAKE_DBG_STR (\nAcpiPstatesPsdPolicy , CFG_ACPI_PSTATES_PSD_POLICY)
2069
2070 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2071
2072 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2073 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2074 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2075 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2076 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2077 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2078 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2079 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2080 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2081 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2082 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2083 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2084 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2085 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2086 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2087 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2088 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2089 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2090 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2091 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2092 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2093 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2094 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2095 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2096 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2097 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2098 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2099 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2100 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2101 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2102 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2103 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2104 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2105 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2106 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2107 MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
2108 MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY),
2109 MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION),
2110 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
2111 MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
2112 MAKE_DBG_STR (\nCfgDataEyeEn , CFG_ENABLE_DATA_EYE),
2113 MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn , CFG_DRAM_DOUBLE_REFRESH_RATE),
2114 #endif
2115 NULL
2116 };
2117 #endif
2118 #endif
2119#endif
2120
2121// Needed for floating point support, linker expects this symbol to be defined.
2122#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
2123 CONST INT32 _fltused = 0;
2124#endif
2125