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review.coreboot.org / coreboot / affe85fbc8a13d35960aa92ae87cbb6330ad253f / . / src / vendorcode / amd / agesa / f16kb / Include / PlatformInstall.h
blob: 136b0f4c85b479421278f0800ec05b985b41b94a [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame^]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45/*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
50
51/* Available options for image builds.
52 *
53 * As part of the image build for each image, define the options below to select the
54 * AGESA entry points included in that image. Turn these on in your option c file, not
55 * here.
56 */
57// #define AGESA_ENTRY_INIT_RESET TRUE
58// #define AGESA_ENTRY_INIT_RECOVERY TRUE
59// #define AGESA_ENTRY_INIT_EARLY TRUE
60// #define AGESA_ENTRY_INIT_POST TRUE
61// #define AGESA_ENTRY_INIT_ENV TRUE
62// #define AGESA_ENTRY_INIT_MID TRUE
63// #define AGESA_ENTRY_INIT_LATE TRUE
64// #define AGESA_ENTRY_INIT_S3SAVE TRUE
65// #define AGESA_ENTRY_INIT_RESUME TRUE
66// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
67// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
68
69/* Defaults for private/internal build control settings */
70/* Available options for image builds.
71 *
72 * As part of the image build for each image, define the options below to select the
73 * AGESA entry points included in that image.
74 */
75
76VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
77 //ModuleHeaderSignature
78 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
79 Int32FromChar ('0', '0', '0', '0'),
80 //ModuleIdentifier[8]
81 AGESA_ID,
82 //ModuleVersion[12]
83 AGESA_VERSION_STRING,
84 //ModuleDispatcher
85 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
86 //NextBlock
87 NULL
88};
89
90/* Process user desired AGESA entry points */
91#ifndef AGESA_ENTRY_INIT_RESET
92 #define AGESA_ENTRY_INIT_RESET FALSE
93#endif
94
95#ifndef AGESA_ENTRY_INIT_RECOVERY
96 #define AGESA_ENTRY_INIT_RECOVERY FALSE
97#endif
98
99#ifndef AGESA_ENTRY_INIT_EARLY
100 #define AGESA_ENTRY_INIT_EARLY FALSE
101#endif
102
103#ifndef AGESA_ENTRY_INIT_POST
104 #define AGESA_ENTRY_INIT_POST FALSE
105#endif
106
107#ifndef AGESA_ENTRY_INIT_ENV
108 #define AGESA_ENTRY_INIT_ENV FALSE
109#endif
110
111#ifndef AGESA_ENTRY_INIT_MID
112 #define AGESA_ENTRY_INIT_MID FALSE
113#endif
114
115#ifndef AGESA_ENTRY_INIT_LATE
116 #define AGESA_ENTRY_INIT_LATE FALSE
117#endif
118
119#ifndef AGESA_ENTRY_INIT_S3SAVE
120 #define AGESA_ENTRY_INIT_S3SAVE FALSE
121#endif
122
123#ifndef AGESA_ENTRY_INIT_RESUME
124 #define AGESA_ENTRY_INIT_RESUME FALSE
125#endif
126
127#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
128 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
129#endif
130
131#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
132 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
133#endif
134
135/* Default the late AP entry point to off. It can be enabled
136 by any family that may need the late AP functionality, or
137 by any feature code that may need it. The IBVs no longer
138 have control over this entry point. */
139#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
140 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
141#endif
142#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
143
144
145
146/* Process solution defined socket / family installations
147 *
148 * As part of the release package for each image, define the options below to select the
149 * AGESA processor support included in that image.
150 */
151
152/* Default sockets to off */
153#define OPTION_FT3_SOCKET_SUPPORT FALSE
154
155/* Default families to off */
156#define OPTION_FAMILY15H_MODEL_1x FALSE
157#define OPTION_FAMILY16H_MODEL_0x FALSE
158
159
160/* Enable the appropriate socket support */
161
162#ifdef INSTALL_FT3_SOCKET_SUPPORT
163 #if INSTALL_FT3_SOCKET_SUPPORT == TRUE
164 #undef OPTION_FT3_SOCKET_SUPPORT
165 #define OPTION_FT3_SOCKET_SUPPORT TRUE
166 #endif
167#endif
168
169
170
171// F16_0x is supported in FT3
172#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
173 #if INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
174 #undef OPTION_FAMILY16H
175 #define OPTION_FAMILY16H TRUE
176 #undef OPTION_FAMILY16H_MODEL_0x
177 #define OPTION_FAMILY16H_MODEL_0x TRUE
178 #endif
179#endif
180
181/* Turn off families not required by socket designations */
182#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
183 #undef OPTION_FAMILY15H
184 #define OPTION_FAMILY15H FALSE
185#endif
186
187#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
188 #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
189 #undef OPTION_FAMILY16H_MODEL_0x
190 #define OPTION_FAMILY16H_MODEL_0x FALSE
191 #endif
192#endif
193
194
195#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
196 #undef OPTION_FAMILY16H
197 #define OPTION_FAMILY16H FALSE
198#endif
199
200
201#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
202 #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
203 #error No FT3 supported families included in the build
204 #endif
205#endif
206
207
208/* Process AGESA private data
209 *
210 * Turn on appropriate CPU models and memory controllers,
211 * as well as some other memory controls.
212 */
213
214/* Default all models to off */
215#define OPTION_FAMILY15H_TN FALSE
216#define OPTION_FAMILY16H_KB FALSE
217#define OPTION_FAMILY15H_UNKNOWN FALSE
218
219/* Default all memory controllers to off */
220#define OPTION_MEMCTLR_TN FALSE
221#define OPTION_MEMCTLR_KB FALSE
222
223/* Default all memory controls to off */
224#define OPTION_HW_WRITE_LEV_TRAINING FALSE
225#define OPTION_SW_WRITE_LEV_TRAINING FALSE
226#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
227#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
228#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
229#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
230#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
231#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
232#define OPTION_MAX_RD_LAT_TRAINING FALSE
233#define OPTION_HW_DRAM_INIT FALSE
234#define OPTION_SW_DRAM_INIT FALSE
235#define OPTION_S3_MEM_SUPPORT FALSE
236#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
237#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
238#define OPTION_RDDQS_2D_TRAINING FALSE
239#define OPTION_PRE_MEM_INIT FALSE
240#define OPTION_POST_MEM_INIT FALSE
241
242/* Defaults for public user options */
243#define OPTION_UDIMMS FALSE
244#define OPTION_RDIMMS FALSE
245#define OPTION_SODIMMS FALSE
246#define OPTION_LRDIMMS FALSE
247#define OPTION_DDR2 FALSE
248#define OPTION_DDR3 FALSE
249#define OPTION_ECC FALSE
250#define OPTION_BANK_INTERLEAVE FALSE
251#define OPTION_DCT_INTERLEAVE FALSE
252#define OPTION_NODE_INTERLEAVE FALSE
253#define OPTION_PARALLEL_TRAINING FALSE
254#define OPTION_ONLINE_SPARE FALSE
255#define OPTION_MEM_RESTORE FALSE
256#define OPTION_DIMM_EXCLUDE FALSE
257#define OPTION_AMP FALSE
258#define OPTION_DATA_EYE FALSE
259#define OPTION_AGGRESSOR FALSE
260
261/* Default all CPU controls to off */
262#define OPTION_MULTISOCKET FALSE
263#define OPTION_CRAT FALSE
264#define OPTION_CDIT FALSE
265#define OPTION_SRAT FALSE
266#define OPTION_SLIT FALSE
267#define OPTION_HT_ASSIST FALSE
268#define OPTION_ATM_MODE FALSE
269#define OPTION_NBR_CACHE FALSE
270#define OPTION_CPU_CORELEVELING FALSE
271#define OPTION_MSG_BASED_C1E FALSE
272#define OPTION_CPU_CFOH FALSE
273#define OPTION_C6_STATE FALSE
274#define OPTION_IO_CSTATE FALSE
275#define OPTION_CPB FALSE
276#define OPTION_CPU_APM FALSE
277#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
278#define OPTION_CPU_PSTATE_HPC_MODE FALSE
279#define OPTION_CPU_TDP_LIMITING FALSE
280#define OPTION_CPU_PSI FALSE
281#define OPTION_CPU_HTC FALSE
282#define OPTION_S3SCRIPT FALSE
283#define OPTION_GFX_RECOVERY FALSE
284#define OPTION_CPU_SCS FALSE
285#define OPTION_PREFETCH_MODE FALSE
286
287/* Default FCH controls to off */
288#define FCH_SUPPORT FALSE
289
290/* Enable all private controls based on socket/family enables */
291
292#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
293 #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
294 #undef FCH_SUPPORT
295 #define FCH_SUPPORT TRUE
296 #undef OPTION_FAMILY16H_KB
297 #define OPTION_FAMILY16H_KB TRUE
298 #undef OPTION_MEMCTLR_KB
299 #define OPTION_MEMCTLR_KB TRUE
300 #undef OPTION_HW_WRITE_LEV_TRAINING
301 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
302 #undef OPTION_CONTINOUS_PATTERN_GENERATION
303 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
304 #undef OPTION_HW_DQS_REC_EN_TRAINING
305 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
306 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
307 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
308 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
309 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
310 #undef OPTION_RDDQS_2D_TRAINING
311 #define OPTION_RDDQS_2D_TRAINING TRUE
312 #undef OPTION_MAX_RD_LAT_TRAINING
313 #define OPTION_MAX_RD_LAT_TRAINING TRUE
314 #undef OPTION_SW_DRAM_INIT
315 #define OPTION_SW_DRAM_INIT TRUE
316 #undef OPTION_S3_MEM_SUPPORT
317 #define OPTION_S3_MEM_SUPPORT TRUE
318 #undef OPTION_GFX_RECOVERY
319 #define OPTION_GFX_RECOVERY TRUE
320 #undef OPTION_CPU_CORELEVELING
321 #define OPTION_CPU_CORELEVELING TRUE
322 #undef OPTION_C6_STATE
323 #define OPTION_C6_STATE TRUE
324 #undef OPTION_IO_CSTATE
325 #define OPTION_IO_CSTATE TRUE
326 #undef OPTION_CPU_CFOH
327 #define OPTION_CPU_CFOH TRUE
328 #undef OPTION_CPU_APM
329 #define OPTION_CPU_APM TRUE
330 #undef OPTION_CPB
331 #define OPTION_CPB TRUE
332 #undef OPTION_CPU_HTC
333 #define OPTION_CPU_HTC TRUE
334 #undef OPTION_CPU_PSI
335 #define OPTION_CPU_PSI TRUE
336 #undef OPTION_CDIT
337 #define OPTION_CDIT TRUE
338 #undef OPTION_CRAT
339 #define OPTION_CRAT TRUE
340 #undef OPTION_CPU_SCS
341 #define OPTION_CPU_SCS TRUE
342 #undef OPTION_S3SCRIPT
343 #define OPTION_S3SCRIPT TRUE
344 ///@todo
345 //#undef OPTION_PREFETCH_MODE
346 //#define OPTION_PREFETCH_MODE TRUE
347 #undef OPTION_UDIMMS
348 #define OPTION_UDIMMS TRUE
349 #undef OPTION_SODIMMS
350 #define OPTION_SODIMMS TRUE
351 #undef OPTION_DDR3
352 #define OPTION_DDR3 TRUE
353 #undef OPTION_ECC
354 #define OPTION_ECC TRUE
355 #undef OPTION_BANK_INTERLEAVE
356 #define OPTION_BANK_INTERLEAVE TRUE
357 #undef OPTION_DCT_INTERLEAVE
358 #define OPTION_DCT_INTERLEAVE TRUE
359 #undef OPTION_MEM_RESTORE
360 #define OPTION_MEM_RESTORE TRUE
361 #undef OPTION_DIMM_EXCLUDE
362 #define OPTION_DIMM_EXCLUDE TRUE
363 #endif
364#endif
365
366
367#if (OPTION_FAMILY16H_KB == TRUE)
368 #undef GNB_SUPPORT
369 #define GNB_SUPPORT TRUE
370#endif
371
372#define OPTION_ACPI_PSTATES TRUE
373#define OPTION_WHEA TRUE
374#define OPTION_DMI TRUE
375#define OPTION_EARLY_SAMPLES FALSE
376#define CFG_ACPI_PSTATES_PPC TRUE
377#define CFG_ACPI_PSTATES_PCT TRUE
378#define CFG_ACPI_PSTATES_PSD TRUE
379#define CFG_ACPI_PSTATES_PSS TRUE
380#define CFG_ACPI_PSTATES_XPSS TRUE
381#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
382#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
383#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
384#define OPTION_ALIB TRUE
385/*---------------------------------------------------------------------------
386 * Processing the options: Second, process the user's selections
387 *--------------------------------------------------------------------------*/
388#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
389 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
390 #undef OPTION_DDR3
391 #define OPTION_DDR3 FALSE
392 #endif
393#endif
394#if ((OPTION_DDR3 == FALSE))
395 #error BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
396#endif
397#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
398 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
399 #undef OPTION_MULTISOCKET
400 #define OPTION_MULTISOCKET FALSE
401 #endif
402#endif
403#ifdef BLDOPT_REMOVE_ECC_SUPPORT
404 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
405 #undef OPTION_ECC
406 #define OPTION_ECC FALSE
407 #endif
408#endif
409#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
410 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
411 #undef OPTION_UDIMMS
412 #define OPTION_UDIMMS FALSE
413 #endif
414#endif
415#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
416 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
417 #undef OPTION_RDIMMS
418 #define OPTION_RDIMMS FALSE
419 #endif
420#endif
421#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
422 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
423 #undef OPTION_SODIMMS
424 #define OPTION_SODIMMS FALSE
425 #endif
426#endif
427#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
428 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
429 #undef OPTION_LRDIMMS
430 #define OPTION_LRDIMMS FALSE
431 #endif
432#endif
433#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
434 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
435 #undef OPTION_BANK_INTERLEAVE
436 #define OPTION_BANK_INTERLEAVE FALSE
437 #endif
438#endif
439#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
440 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
441 #undef OPTION_DCT_INTERLEAVE
442 #define OPTION_DCT_INTERLEAVE FALSE
443 #endif
444#endif
445#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
446 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
447 #undef OPTION_NODE_INTERLEAVE
448 #define OPTION_NODE_INTERLEAVE FALSE
449 #endif
450#endif
451#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
452 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
453 #undef OPTION_PARALLEL_TRAINING
454 #define OPTION_PARALLEL_TRAINING FALSE
455 #endif
456#endif
457#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
458 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
459 #undef OPTION_ONLINE_SPARE
460 #define OPTION_ONLINE_SPARE FALSE
461 #endif
462#endif
463#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
464 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
465 #undef OPTION_MEM_RESTORE
466 #define OPTION_MEM_RESTORE FALSE
467 #endif
468#endif
469#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
470 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
471 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
472 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
473 #endif
474#endif
475#ifdef BLDOPT_REMOVE_ACPI_PSTATES
476 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
477 #undef OPTION_ACPI_PSTATES
478 #define OPTION_ACPI_PSTATES FALSE
479 #endif
480#endif
481#ifdef BLDOPT_REMOVE_CRAT
482 #if BLDOPT_REMOVE_CRAT == TRUE
483 #undef OPTION_CRAT
484 #define OPTION_CRAT FALSE
485 #endif
486#endif
487#ifdef BLDOPT_REMOVE_CDIT
488 #if BLDOPT_REMOVE_CDIT == TRUE
489 #undef OPTION_CDIT
490 #define OPTION_CDIT FALSE
491 #endif
492#endif
493#ifdef BLDOPT_REMOVE_SRAT
494 #if BLDOPT_REMOVE_SRAT == TRUE
495 #undef OPTION_SRAT
496 #define OPTION_SRAT FALSE
497 #endif
498#endif
499#ifdef BLDOPT_REMOVE_SLIT
500 #if BLDOPT_REMOVE_SLIT == TRUE
501 #undef OPTION_SLIT
502 #define OPTION_SLIT FALSE
503 #endif
504#endif
505#ifdef BLDOPT_REMOVE_WHEA
506 #if BLDOPT_REMOVE_WHEA == TRUE
507 #undef OPTION_WHEA
508 #define OPTION_WHEA FALSE
509 #endif
510#endif
511#ifdef BLDOPT_REMOVE_DMI
512 #if BLDOPT_REMOVE_DMI == TRUE
513 #undef OPTION_DMI
514 #define OPTION_DMI FALSE
515 #endif
516#endif
517#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
518 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
519 #undef OPTION_ADDR_TO_CS_TRANSLATOR
520 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
521 #endif
522#endif
523#ifdef BLDOPT_REMOVE_AMP_SUPPORT
524 #if BLDOPT_REMOVE_AMP_SUPPORT == TRUE
525 #undef OPTION_AMP
526 #define OPTION_AMP FALSE
527 #endif
528#endif
529
530#ifdef OPTION_RDDQS_2D_TRAINING
531 #if OPTION_RDDQS_2D_TRAINING == FALSE
532 #undef OPTION_DATA_EYE
533 #define OPTION_DATA_EYE FALSE
534 #else
535 #ifdef BLDOPT_REMOVE_DATA_EYE
536 #if BLDOPT_REMOVE_DATA_EYE == TRUE
537 #undef OPTION_DATA_EYE
538 #define OPTION_DATA_EYE FALSE
539 #endif
540 #endif
541 #endif
542#else
543 #undef OPTION_DATA_EYE
544 #define OPTION_DATA_EYE FALSE
545#endif
546
547#ifdef BLDOPT_REMOVE_HT_ASSIST
548 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
549 #undef OPTION_HT_ASSIST
550 #define OPTION_HT_ASSIST FALSE
551 #endif
552#endif
553
554#ifdef BLDOPT_REMOVE_ATM_MODE
555 #if BLDOPT_REMOVE_ATM_MODE == TRUE
556 #undef OPTION_ATM_MODE
557 #define OPTION_ATM_MODE FALSE
558 #endif
559#endif
560
561#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
562 #if BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
563 #undef OPTION_NBR_CACHE
564 #define OPTION_NBR_CACHE FALSE
565 #endif
566#endif
567
568#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
569 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
570 #undef OPTION_MSG_BASED_C1E
571 #define OPTION_MSG_BASED_C1E FALSE
572 #endif
573#endif
574
575#ifdef BLDOPT_REMOVE_C6_STATE
576 #if BLDOPT_REMOVE_C6_STATE == TRUE
577 #undef OPTION_C6_STATE
578 #define OPTION_C6_STATE FALSE
579 #endif
580#endif
581
582#ifdef BLDOPT_REMOVE_GFX_RECOVERY
583 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
584 #undef OPTION_GFX_RECOVERY
585 #define OPTION_GFX_RECOVERY FALSE
586 #endif
587#endif
588
589#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
590 #if BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
591 #undef OPTION_RDDQS_2D_TRAINING
592 #define OPTION_RDDQS_2D_TRAINING FALSE
593 #endif
594#endif
595
596#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
597 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
598 #undef CFG_ACPI_PSTATES_PPC
599 #define CFG_ACPI_PSTATES_PPC FALSE
600 #endif
601#endif
602
603#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
604 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
605 #undef CFG_ACPI_PSTATES_PCT
606 #define CFG_ACPI_PSTATES_PCT FALSE
607 #endif
608#endif
609
610#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
611 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
612 #undef CFG_ACPI_PSTATES_PSD
613 #define CFG_ACPI_PSTATES_PSD FALSE
614 #endif
615#endif
616
617#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
618 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
619 #undef CFG_ACPI_PSTATES_PSS
620 #define CFG_ACPI_PSTATES_PSS FALSE
621 #endif
622#endif
623
624#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
625 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
626 #undef CFG_ACPI_PSTATES_XPSS
627 #define CFG_ACPI_PSTATES_XPSS FALSE
628 #endif
629#endif
630
631#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
632 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
633 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
634 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
635 #endif
636#endif
637
638#ifdef BLDOPT_REMOVE_AGGRESSOR
639 #if BLDOPT_REMOVE_AGGRESSOR == TRUE
640 #undef OPTION_AGGRESSOR
641 #define OPTION_AGGRESSOR FALSE
642 #endif
643#endif
644
645#ifdef BLDCFG_PSTATE_HPC_MODE
646 #if BLDCFG_PSTATE_HPC_MODE == TRUE
647 #undef OPTION_CPU_PSTATE_HPC_MODE
648 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
649 #endif
650#endif
651
652#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
653 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
654 #undef CFG_ACPI_PSTATE_PSD_INDPX
655 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
656 #endif
657#endif
658
659#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
660 #define CFG_ACPI_PSTATES_PSD_POLICY (BLDCFG_ACPI_PSTATES_PSD_POLICY)
661#else
662 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault
663#endif
664
665#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
666 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
667 #undef CFG_VRM_HIGH_SPEED_ENABLE
668 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
669 #endif
670#endif
671
672#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
673 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
674 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
675 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
676 #endif
677#endif
678
679#ifdef BLDCFG_STARTING_BUSNUM
680 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
681#else
682 #define CFG_STARTING_BUSNUM (0)
683#endif
684
685#ifdef BLDCFG_AMD_PLATFORM_TYPE
686 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
687#else
688 #define CFG_AMD_PLATFORM_TYPE 0
689#endif
690
691CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
692
693#ifdef BLDCFG_MAXIMUM_BUSNUM
694 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
695#else
696 #define CFG_MAXIMUM_BUSNUM (0xF8)
697#endif
698
699#ifdef BLDCFG_ALLOCATED_BUSNUM
700 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
701#else
702 #define CFG_ALLOCATED_BUSNUM (0x20)
703#endif
704
705#ifdef BLDCFG_BUID_SWAP_LIST
706 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
707#else
708 #define CFG_BUID_SWAP_LIST (NULL)
709#endif
710
711#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
712 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
713#else
714 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
715#endif
716
717#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
718 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
719#else
720 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
721#endif
722
723#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
724 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
725#else
726 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
727#endif
728
729#ifdef BLDCFG_BUS_NUMBERS_LIST
730 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
731#else
732 #define CFG_BUS_NUMBERS_LIST (NULL)
733#endif
734
735#ifdef BLDCFG_IGNORE_LINK_LIST
736 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
737#else
738 #define CFG_IGNORE_LINK_LIST (NULL)
739#endif
740
741#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
742 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
743#else
744 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
745#endif
746
747#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
748 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
749#else
750 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
751#endif
752
753#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
754 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
755#else
756 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
757#endif
758
759#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
760 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
761#else
762 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
763#endif
764
765#ifdef BLDCFG_USE_HT_ASSIST
766 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
767#else
768 #define CFG_USE_HT_ASSIST (TRUE)
769#endif
770
771#ifdef BLDCFG_USE_ATM_MODE
772 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
773#else
774 #define CFG_USE_ATM_MODE (TRUE)
775#endif
776
777#ifdef BLDCFG_USE_NEIGHBOR_CACHE
778 #define CFG_USE_NBR_CACHE (BLDCFG_USE_NEIGHBOR_CACHE)
779#else
780 #define CFG_USE_NBR_CACHE (TRUE)
781#endif
782
783#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
784 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
785#else
786 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
787#endif
788
789#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
790 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
791#else
792 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
793#endif
794
795#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
796 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
797#else
798 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
799#endif
800
801#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
802 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
803#else
804 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
805#endif
806
807#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
808 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
809#else
810 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
811#endif
812
813#ifdef BLDCFG_VRM_CURRENT_LIMIT
814 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
815#else
816 #define CFG_VRM_CURRENT_LIMIT 0
817#endif
818
819#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
820 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
821#else
822 #define CFG_VRM_LOW_POWER_THRESHOLD 0
823#endif
824
825#ifdef BLDCFG_VRM_SLEW_RATE
826 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
827#else
828 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
829#endif
830
831#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
832 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
833#else
834 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
835#endif
836
837#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
838 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
839#else
840 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
841#endif
842
843#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
844 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
845#else
846 #define CFG_VRM_SVI_OCP_LEVEL 0
847#endif
848
849#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
850 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
851#else
852 #define CFG_VRM_NB_SVI_OCP_LEVEL 0
853#endif
854
855#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
856 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
857#else
858 #define CFG_VRM_NB_CURRENT_LIMIT (0)
859#endif
860
861#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
862 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
863#else
864 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
865#endif
866
867#ifdef BLDCFG_VRM_NB_SLEW_RATE
868 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
869#else
870 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
871#endif
872
873#ifdef BLDCFG_PLAT_NUM_IO_APICS
874 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
875#else
876 #define CFG_PLAT_NUM_IO_APICS 0
877#endif
878
879#ifdef BLDCFG_MEM_INIT_PSTATE
880 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
881#else
882 #define CFG_MEM_INIT_PSTATE 0
883#endif
884
885#ifdef BLDCFG_PLATFORM_C1E_MODE
886 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
887#else
888 #define CFG_C1E_MODE C1eModeDisabled
889#endif
890
891#ifdef BLDCFG_PLATFORM_C1E_OPDATA
892 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
893#else
894 #define CFG_C1E_OPDATA 0
895#endif
896
897#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
898 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
899#else
900 #define CFG_C1E_OPDATA1 0
901#endif
902
903#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
904 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
905#else
906 #define CFG_C1E_OPDATA2 0
907#endif
908
909#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
910 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
911#else
912 #define CFG_C1E_OPDATA3 0
913#endif
914
915#ifdef BLDCFG_PLATFORM_CSTATE_MODE
916 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
917#else
918 #define CFG_CSTATE_MODE CStateModeC6
919#endif
920
921#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
922 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
923#else
924 #define CFG_CSTATE_OPDATA 0
925#endif
926
927#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
928 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
929#else
930 #define CFG_CSTATE_IO_BASE_ADDRESS 0
931#endif
932
933#ifdef BLDCFG_PLATFORM_CPB_MODE
934 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
935#else
936 #define CFG_CPB_MODE CpbModeAuto
937#endif
938
939#ifdef BLDCFG_CORE_LEVELING_MODE
940 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
941#else
942 #define CFG_CORE_LEVELING_MODE 0
943#endif
944
945#ifdef BLDCFG_AMD_TDP_LIMIT
946 #define CFG_AMD_POWER_CEILING BLDCFG_AMD_TDP_LIMIT
947#else
948 #define CFG_AMD_POWER_CEILING 0
949#endif
950
951#ifdef BLDCFG_HEAP_DRAM_ADDRESS
952 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
953#else
954 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
955#endif
956
957#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
958 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
959#else
960 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
961#endif
962
963#ifdef BLDCFG_MEMORY_MODE_UNGANGED
964 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
965#else
966 #define CFG_MEMORY_MODE_UNGANGED TRUE
967#endif
968
969#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
970 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
971#else
972 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
973#endif
974
975#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
976 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
977#else
978 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
979#endif
980
981#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
982 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
983#else
984 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
985#endif
986
987#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
988 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
989#else
990 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
991#endif
992
993#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
994 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
995#else
996 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
997#endif
998
999#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1000 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1001#else
1002 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1003#endif
1004
1005#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1006 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1007#else
1008 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
1009#endif
1010
1011#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1012 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1013#else
1014 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1015#endif
1016
1017#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1018 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1019#else
1020 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1021#endif
1022
1023#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1024 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1025#else
1026 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1027#endif
1028
1029#ifdef BLDCFG_MEMORY_POWER_DOWN
1030 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1031#else
1032 #define CFG_MEMORY_POWER_DOWN FALSE
1033#endif
1034
1035#ifdef BLDCFG_POWER_DOWN_MODE
1036 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1037#else
1038 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1039#endif
1040
1041#ifdef BLDCFG_ONLINE_SPARE
1042 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1043#else
1044 #define CFG_ONLINE_SPARE FALSE
1045#endif
1046
1047#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1048 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1049#else
1050 #define CFG_MEMORY_PARITY_ENABLE FALSE
1051#endif
1052
1053#ifdef BLDCFG_BANK_SWIZZLE
1054 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1055#else
1056 #define CFG_BANK_SWIZZLE TRUE
1057#endif
1058
1059#ifdef BLDCFG_TIMING_MODE_SELECT
1060 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1061#else
1062 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1063#endif
1064
1065#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1066 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1067#else
1068 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1069#endif
1070
1071#ifdef BLDCFG_DQS_TRAINING_CONTROL
1072 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1073#else
1074 #define CFG_DQS_TRAINING_CONTROL TRUE
1075#endif
1076
1077#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1078 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1079#else
1080 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1081#endif
1082
1083#ifdef BLDCFG_USE_BURST_MODE
1084 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1085#else
1086 #define CFG_USE_BURST_MODE FALSE
1087#endif
1088
1089#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1090 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1091#else
1092 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1093#endif
1094
1095#ifdef BLDCFG_ENABLE_ECC_FEATURE
1096 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1097#else
1098 #define CFG_ENABLE_ECC_FEATURE TRUE
1099#endif
1100
1101#ifdef BLDCFG_ECC_REDIRECTION
1102 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1103#else
1104 #define CFG_ECC_REDIRECTION FALSE
1105#endif
1106
1107#ifdef BLDCFG_SCRUB_DRAM_RATE
1108 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1109#else
1110 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1111#endif
1112
1113#ifdef BLDCFG_SCRUB_L2_RATE
1114 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1115#else
1116 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1117#endif
1118
1119#ifdef BLDCFG_SCRUB_L3_RATE
1120 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1121#else
1122 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1123#endif
1124
1125#ifdef BLDCFG_SCRUB_IC_RATE
1126 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1127#else
1128 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1129#endif
1130
1131#ifdef BLDCFG_SCRUB_DC_RATE
1132 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1133#else
1134 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1135#endif
1136
1137#ifdef BLDCFG_ECC_SYNC_FLOOD
1138 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1139#else
1140 #define CFG_ECC_SYNC_FLOOD TRUE
1141#endif
1142
1143#ifdef BLDCFG_ECC_SYMBOL_SIZE
1144 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1145#else
1146 #define CFG_ECC_SYMBOL_SIZE 0
1147#endif
1148
1149#ifdef BLDCFG_1GB_ALIGN
1150 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1151#else
1152 #define CFG_1GB_ALIGN FALSE
1153#endif
1154
1155#ifdef BLDCFG_UMA_ALLOCATION_MODE
1156 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1157#else
1158 #define CFG_UMA_MODE UMA_AUTO
1159#endif
1160
1161#ifdef BLDCFG_FORCE_TRAINING_MODE
1162 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1163#else
1164 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1165#endif
1166
1167#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1168 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1169#else
1170 #define CFG_UMA_SIZE 0
1171#endif
1172
1173#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1174 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1175#else
1176 #define CFG_UMA_ABOVE4G FALSE
1177#endif
1178
1179#ifdef BLDCFG_UMA_ALIGNMENT
1180 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1181#else
1182 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1183#endif
1184
1185#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1186 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
1187#else
1188 #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG DDR3_TECHNOLOGY
1189#endif
1190
1191#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1192 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1193#else
1194 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1195#endif
1196
1197#ifdef BLDCFG_S3_LATE_RESTORE
1198 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1199#else
1200 #define CFG_S3_LATE_RESTORE TRUE
1201#endif
1202
1203#ifdef BLDCFG_USE_32_BYTE_REFRESH
1204 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1205#else
1206 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1207#endif
1208
1209#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1210 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1211#else
1212 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1213#endif
1214
1215#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1216 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1217#else
1218 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1219#endif
1220
1221#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1222 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1223#else
1224 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1225#endif
1226
1227#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1228 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1229#else
1230 #define CFG_GNB_HD_AUDIO TRUE
1231#endif
1232
1233#ifdef BLDCFG_CFG_ABM_SUPPORT
1234 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1235#else
1236 #define CFG_ABM_SUPPORT FALSE
1237#endif
1238
1239#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1240 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1241#else
1242 #define CFG_DYNAMIC_REFRESH_RATE 0
1243#endif
1244
1245#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1246 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1247#else
1248 #define CFG_LCD_BACK_LIGHT_CONTROL 200
1249#endif
1250
1251#ifdef BLDCFG_STEREO_3D_PINOUT
1252 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1253#else
1254 #define CFG_GNB_STEREO_3D_PINOUT 0
1255#endif
1256
1257#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1258 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1259#else
1260 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1261#endif
1262
1263// Define pin configuration for SYNCFLOOD
1264// Default to FALSE (Use pin as SYNCFLOOD)
1265#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
1266 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
1267#else
1268 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
1269#endif
1270
1271#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1272 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
1273#else
1274 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
1275#endif
1276
1277#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1278 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1279#else
1280 #define CFG_GNB_IGPU_SSID 0
1281#endif
1282
1283#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1284 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1285#else
1286 #define CFG_GNB_HDAUDIO_SSID 0
1287#endif
1288
1289#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1290 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
1291#else
1292 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
1293#endif
1294
1295#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1296 #define CFG_GNB_PCIE_SSID BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1297#else
1298 #define CFG_GNB_PCIE_SSID 0x12341022ul
1299#endif
1300
1301#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1302 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1303#else
1304 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1305#endif
1306
1307#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1308 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1309#else
1310 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1311#endif
1312
1313#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1314 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1315#else
1316 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1317#endif
1318
1319#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1320 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1321#else
1322 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
1323#endif
1324
1325#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1326 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1327#else
1328 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1329#endif
1330
1331#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1332 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1333 #undef OPTION_EARLY_SAMPLES
1334 #define OPTION_EARLY_SAMPLES FALSE
1335 #else
1336 #undef OPTION_EARLY_SAMPLES
1337 #define OPTION_EARLY_SAMPLES TRUE
1338 #endif
1339#endif
1340
1341#ifdef BLDOPT_REMOVE_ALIB
1342 #if BLDOPT_REMOVE_ALIB == TRUE
1343 #undef OPTION_ALIB
1344 #define OPTION_ALIB FALSE
1345 #else
1346 #undef OPTION_ALIB
1347 #define OPTION_ALIB TRUE
1348 #endif
1349#endif
1350
1351#ifdef BLDOPT_REMOVE_FCH_COMPONENT
1352 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1353 #undef FCH_SUPPORT
1354 #define FCH_SUPPORT FALSE
1355 #endif
1356#endif
1357
1358#ifdef BLDCFG_IOMMU_SUPPORT
1359 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1360#else
1361 #define CFG_IOMMU_SUPPORT TRUE
1362#endif
1363
1364#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1365 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1366#else
1367 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
1368#endif
1369
1370#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1371 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
1372#else
1373 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
1374#endif
1375
1376#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1377 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
1378#else
1379 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
1380#endif
1381
1382#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1383 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
1384#else
1385 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
1386#endif
1387
1388#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1389 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
1390#else
1391 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
1392#endif
1393
1394#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1395 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
1396#else
1397 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
1398#endif
1399
1400#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1401 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
1402#else
1403 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
1404#endif
1405
1406#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1407 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
1408#else
1409 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
1410#endif
1411
1412#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1413 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
1414#else
1415 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
1416#endif
1417
1418
1419// BLDCFG_LVDS_24BBP_PANEL_MODE
1420// This specifies the LVDS 24 BBP mode.
1421// 0 - Use LDI mode (default).
1422// 1 - Use FPDI mode.
1423#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
1424 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
1425#else
1426 #define CFG_LVDS_24BBP_PANEL_MODE 0
1427#endif
1428
1429#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1430 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1431#else
1432 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1433#endif
1434
1435#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1436 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1437#else
1438 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1439#endif
1440
1441#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1442 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1443#else
1444 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1445#endif
1446
1447#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1448 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1449#else
1450 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1451#endif
1452
1453#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1454 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1455#else
1456 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1457#endif
1458
1459#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1460 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
1461#else
1462 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
1463#endif
1464
1465#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1466 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
1467#else
1468 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
1469#endif
1470
1471#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1472 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
1473#else
1474 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
1475#endif
1476
1477#ifdef BLDCFG_DP_FIXED_VOLT_SWING
1478 #define CFG_DP_FIXED_VOLT_SWING BLDCFG_DP_FIXED_VOLT_SWING
1479#else
1480 #define CFG_DP_FIXED_VOLT_SWING 0
1481#endif
1482
1483#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1484 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1485#else
1486 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1487#endif
1488
1489#ifdef BLDCFG_NB_PSTATES_SUPPORTED
1490 #define CFG_NB_PSTATES_SUPPORTED (BLDCFG_NB_PSTATES_SUPPORTED)
1491#else
1492 #define CFG_NB_PSTATES_SUPPORTED (TRUE)
1493#endif
1494
1495#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
1496 #define CFG_HTC_TEMPERATURE_LIMIT (BLDCFG_HTC_TEMPERATURE_LIMIT)
1497#else
1498 #define CFG_HTC_TEMPERATURE_LIMIT (0)
1499#endif
1500
1501#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
1502 #define CFG_LHTC_TEMPERATURE_LIMIT (BLDCFG_LHTC_TEMPERATURE_LIMIT)
1503#else
1504 #define CFG_LHTC_TEMPERATURE_LIMIT (0)
1505#endif
1506
1507#ifdef BLDCFG_PCI_MMIO_BASE
1508 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
1509#else
1510 #define CFG_PCI_MMIO_BASE (0)
1511#endif
1512
1513#ifdef BLDCFG_PCI_MMIO_SIZE
1514 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
1515#else
1516 #define CFG_PCI_MMIO_SIZE (0)
1517#endif
1518
1519#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1520 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1521#else
1522 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
1523#endif
1524
1525#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
1526 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
1527#else
1528 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
1529#endif
1530
1531#ifdef BLDCFG_HYBRID_BOOST_ENABLE
1532 #define CFG_HYBRID_BOOST_ENABLE BLDCFG_HYBRID_BOOST_ENABLE
1533#else
1534 #define CFG_HYBRID_BOOST_ENABLE TRUE
1535#endif
1536
1537#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
1538 #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS
1539#else
1540 #define CFG_GNB_IOAPIC_ADDRESS NULL
1541#endif
1542
1543#ifdef BLDCFG_GNB_IOMMU_ADDRESS
1544 #define CFG_GNB_IOMMU_ADDRESS BLDCFG_GNB_IOMMU_ADDRESS
1545#else
1546 #define CFG_GNB_IOMMU_ADDRESS NULL
1547#endif
1548
1549#ifdef BLDCFG_ENABLE_DATA_EYE
1550 #define CFG_ENABLE_DATA_EYE BLDCFG_ENABLE_DATA_EYE
1551#else
1552 #define CFG_ENABLE_DATA_EYE TRUE
1553#endif
1554
1555#ifdef BLDCFG_ACPI_SET_OEM_ID
1556 #define CFG_ACPI_SET_OEM_ID BLDCFG_ACPI_SET_OEM_ID
1557#else
1558 #define CFG_ACPI_SET_OEM_ID 'A','M','D',' ',' ',' '
1559#endif
1560
1561#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
1562 #define CFG_ACPI_SET_OEM_TABLE_ID BLDCFG_ACPI_SET_OEM_TABLE_ID
1563#else
1564 #define CFG_ACPI_SET_OEM_TABLE_ID 'A','G','E','S','A',' ',' ',' '
1565#endif
1566
1567#ifdef BLDCFG_DOCKED_TDP_HEADROOM
1568 #define CFG_DOCKED_TDP_HEADROOM BLDCFG_DOCKED_TDP_HEADROOM
1569#else
1570 #define CFG_DOCKED_TDP_HEADROOM TRUE
1571#endif
1572
1573#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1574 #define CFG_DRAM_DOUBLE_REFRESH_RATE BLDCFG_DRAM_DOUBLE_REFRESH_RATE
1575#else
1576 #define CFG_DRAM_DOUBLE_REFRESH_RATE FALSE
1577#endif
1578
1579/*---------------------------------------------------------------------------
1580 * Processing the options: Third, perform the option cross checks
1581 *--------------------------------------------------------------------------*/
1582// Assure that at least one type of memory support is included
1583#if OPTION_UDIMMS == FALSE
1584 #if OPTION_RDIMMS == FALSE
1585 #if OPTION_SODIMMS == FALSE
1586 #if OPTION_LRDIMMS == FALSE
1587 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1588 #endif
1589 #endif
1590 #endif
1591#endif
1592// Ensure at least one dimm type is capable
1593#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1594 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1595 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1596 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1597 #error BLDCFG: No dimm type is capable
1598 #endif
1599 #endif
1600 #endif
1601#endif
1602// Check LRDIMM CODE and LRDIMM CFG item
1603#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1604 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1605 #error Warning: LRDIMM capability is false, but LRIDMM support code included
1606 #endif
1607#endif
1608// Turn off multi-socket based features if only one node...
1609#if OPTION_MULTISOCKET == FALSE
1610 #undef OPTION_PARALLEL_TRAINING
1611 #define OPTION_PARALLEL_TRAINING FALSE
1612 #undef OPTION_NODE_INTERLEAVE
1613 #define OPTION_NODE_INTERLEAVE FALSE
1614#endif
1615// Ensure the frequency limit is valid
1616#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
1617 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
1618 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
1619 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
1620 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
1621 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
1622 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
1623 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
1624 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
1625 #error BLDCFG: Unsupported memory bus frequency
1626 #endif
1627 #endif
1628 #endif
1629 #endif
1630 #endif
1631 #endif
1632 #endif
1633 #endif
1634#endif
1635// Ensure timing mode is valid
1636#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1637 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1638 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1639 #error BLDCFG: Invalid timing mode is set
1640 #endif
1641 #endif
1642#endif
1643// Ensure the scrub rate is valid
1644#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1645 #error BLDCFG: Unsupported dram scrub rate set
1646#endif
1647#if CFG_SCRUB_L2_RATE > 0x16
1648 #error BLDCFG: Unsupported L2 scrubber rate set
1649#endif
1650#if CFG_SCRUB_L3_RATE > 0x16
1651 #error BLDCFG: unsupported L3 scrubber rate set
1652#endif
1653#if CFG_SCRUB_IC_RATE > 0x16
1654 #error BLDCFG: Unsupported Instruction cache scrub rate set
1655#endif
1656#if CFG_SCRUB_DC_RATE > 0x16
1657 #error BLDCFG: Unsupported Dcache scrub rate set
1658#endif
1659// Ensure Quad rank dimm type is valid
1660#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1661 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1662 #error BLDCFG: Invalid quad rank dimm type set
1663 #endif
1664#endif
1665// Ensure ECC symbol size is valid
1666#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1667 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1668 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1669 #error BLDCFG: Invalid Ecc symbol size set
1670 #endif
1671 #endif
1672#endif
1673// Ensure power down mode is valid
1674#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1675 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1676 #if AGESA_ENTRY_INIT_POST == TRUE
1677 #error BLDCFG: Invalid power down mode set
1678 #endif
1679 #endif
1680#endif
1681
1682// Ensure P-state dependence settings do not conflict
1683#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1684 #error BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
1685#endif
1686
1687#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
1688 #error BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
1689#endif
1690
1691#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
1692 #error BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
1693#endif
1694
1695
1696
1697/*****************************************************************************
1698 *
1699 * Process the option logic, setting local control variables
1700 *
1701 ****************************************************************************/
1702#if OPTION_ACPI_PSTATES == TRUE
1703 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1704 #define OPTFCN_GATHER_DATA PStateGatherData
1705 #if OPTION_MULTISOCKET == TRUE
1706 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1707 #else
1708 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1709 #endif
1710#else
1711 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1712 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1713 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1714#endif
1715
1716// Consolidate P-state dependence setings
1717#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
1718 #undef CFG_ACPI_PSTATES_PSD_POLICY
1719 #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyIndependent
1720#endif
1721
1722/*****************************************************************************
1723 *
1724 * Include the structure definitions for the defaults table structures
1725 *
1726 ****************************************************************************/
1727#include "Options.h"
1728#include "OptionCpuFamiliesInstall.h"
1729#include "OptionsHt.h"
1730#include "OptionHtInstall.h"
1731#include "OptionMemory.h"
1732#include "PlatformMemoryConfiguration.h"
1733#include "OptionMemoryInstall.h"
1734#include "OptionMemoryRecovery.h"
1735#include "OptionMemoryRecoveryInstall.h"
1736#include "OptionCpuFeaturesInstall.h"
1737#include "OptionDmi.h"
1738#include "OptionDmiInstall.h"
1739#include "OptionPstate.h"
1740#include "OptionPstateInstall.h"
1741#include "OptionWhea.h"
1742#include "OptionWheaInstall.h"
1743#include "OptionCrat.h"
1744#include "OptionCratInstall.h"
1745#include "OptionCdit.h"
1746#include "OptionCditInstall.h"
1747#include "OptionSrat.h"
1748#include "OptionSratInstall.h"
1749#include "OptionSlit.h"
1750#include "OptionSlitInstall.h"
1751#include "OptionMultiSocket.h"
1752#include "OptionMultiSocketInstall.h"
1753#include "OptionIdsInstall.h"
1754#include "OptionGfxRecovery.h"
1755#include "OptionGfxRecoveryInstall.h"
1756#include "OptionGnb.h"
1757#include "OptionGnbInstall.h"
1758#include "OptionS3ScriptInstall.h"
1759#include "OptionFchInstall.h"
1760#include "OptionMmioMapInstall.h"
1761#include "OptionPrefetchModeInstall.h"
1762
1763
1764/*****************************************************************************
1765 *
1766 * Generate the output structures (defaults tables)
1767 *
1768 ****************************************************************************/
1769
1770FCH_PLATFORM_POLICY FchUserOptions = {
1771 CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress
1772 CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress
1773 CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress
1774 CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr
1775 CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr
1776 CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr
1777 CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr
1778 CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr
1779 CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr
1780 CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr
1781 CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase
1782 CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase
1783 CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress
1784 CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress
1785 0x780D1022ul,
1786 CFG_SMBUS_SSID, // CfgSmbusSsid
1787 CFG_IDE_SSID, // CfgIdeSsid
1788 CFG_SATA_AHCI_SSID, // CfgSataAhciSsid
1789 CFG_SATA_IDE_SSID, // CfgSataIdeSsid
1790 CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid
1791 CFG_SATA_RAID_SSID, // CfgSataRaidSsid
1792 CFG_EHCI_SSID, // CfgEhcidSsid
1793 CFG_OHCI_SSID, // CfgOhcidSsid
1794 CFG_LPC_SSID, // CfgLpcSsid
1795 CFG_SD_SSID, // CfgSdSsid
1796 CFG_XHCI_SSID, // CfgXhciSsid
1797 CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib
1798 CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap
1799 CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig
1800 CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present
1801 CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present
1802 CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present
1803 CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present
1804 CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug
1805 CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug
1806 CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug
1807 CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug
1808
1809 CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap
1810 CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl
1811 CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
1812 CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
1813 CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
1814 CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl
1815};
1816
1817BUILD_OPT_CFG UserOptions = {
1818 { // AGESA version string
1819 AGESA_CODE_SIGNATURE, // code header Signature
1820 AGESA_PACKAGE_STRING, // 16 character ID
1821 AGESA_VERSION_STRING, // 12 character version string
1822 0 // null string terminator
1823 },
1824 //Build Option Area
1825 OPTION_UDIMMS, //UDIMMS
1826 OPTION_RDIMMS, //RDIMMS
1827 OPTION_LRDIMMS, //LRDIMMS
1828 OPTION_ECC, //ECC
1829 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1830 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1831 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1832 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1833 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1834 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1835 OPTION_MULTISOCKET, //MULTISOCKET
1836 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1837 OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode
1838 OPTION_CRAT, //CRAT
1839 OPTION_CDIT, //CDIT
1840 OPTION_SRAT, //SRAT
1841 OPTION_SLIT, //SLIT
1842 OPTION_WHEA, //WHEA
1843 OPTION_DMI, //DMI
1844 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1845 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1846
1847 //Build Configuration Area
1848 CFG_PCI_MMIO_BASE,
1849 CFG_PCI_MMIO_SIZE,
1850 {
1851 // CoreVrm
1852 {
1853 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1854 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1855 CFG_VRM_SLEW_RATE, // VrmSlewRate
1856 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1857 CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmMaximumCurrentLimit
1858 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
1859 },
1860 // NbVrm
1861 {
1862 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1863 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1864 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1865 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1866 CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbMaximumCurrentLimit
1867 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
1868 }
1869 },
1870 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1871 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1872 CFG_C1E_MODE, //C1eMode
1873 CFG_C1E_OPDATA, //C1ePlatformData
1874 CFG_C1E_OPDATA1, //C1ePlatformData1
1875 CFG_C1E_OPDATA2, //C1ePlatformData2
1876 CFG_C1E_OPDATA3, //C1ePlatformData3
1877 CFG_CSTATE_MODE, //CStateMode
1878 CFG_CSTATE_OPDATA, //CStatePlatformData
1879 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1880 CFG_CPB_MODE, //CpbMode
1881 LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO'
1882 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1883 {
1884 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1885 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1886 CFG_USE_ATM_MODE, // CfgUseAtmMode
1887 CFG_USE_NBR_CACHE, // CfgUseNbrCache
1888 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1889 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1890 // ADVANCED_PERFORMANCE_PROFILE
1891 {
1892 CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode
1893 CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode
1894 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
1895 },
1896 CFG_PLATFORM_POWER_POLICY_MODE, // The platform's power policy mode.
1897 CFG_NB_PSTATES_SUPPORTED // The Nb-Pstates is supported or not
1898 },
1899 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1900 CFG_AMD_PLATFORM_TYPE, // CfgAmdPlatformType
1901 CFG_AMD_POWER_CEILING, // CfgAmdPowerCeiling
1902 CFG_HTC_TEMPERATURE_LIMIT, // CfgHtcTemperatureLimit
1903 CFG_LHTC_TEMPERATURE_LIMIT, // CfgLhtcTemperatureLimit
1904
1905 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1906 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1907 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1908 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1909 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1910 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1911 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1912 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1913 CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb
1914 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1915 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1916 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1917 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1918 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1919 CFG_ONLINE_SPARE, // CfgOnlineSpare
1920 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1921 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1922 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1923 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1924 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1925 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1926 CFG_USE_BURST_MODE, // CfgUseBurstMode
1927 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1928 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1929 CFG_ECC_REDIRECTION, // CfgEccRedirection
1930 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1931 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1932 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1933 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1934 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1935 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1936 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1937 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1938 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1939 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1940 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1941 CFG_ACPI_PSTATES_PSD_POLICY, // CfgAcpiPstatesPsdPolicy
1942 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1943 CFG_UMA_MODE, // CfgUmaMode
1944 CFG_UMA_SIZE, // CfgUmaSize
1945 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1946 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1947 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1948 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1949 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1950 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1951 CFG_ABM_SUPPORT, // CfgAbmSupport
1952 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1953 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1954 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1955 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1956 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1957 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1958 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1959 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1960 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1961
1962 &FchUserOptions, // FchBldCfg
1963
1964 CFG_IOMMU_SUPPORT, // CfgIommuSupport
1965 CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe
1966 CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl
1967 CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon
1968 CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
1969 CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
1970 CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
1971 CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
1972 CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq
1973 CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue
1974 CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode
1975 {{
1976 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1977 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1978 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1979 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1980 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1981 CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl
1982 }},
1983 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
1984 CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature
1985 CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode
1986 CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport
1987 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
1988 CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi
1989 CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy
1990 CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset
1991 CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment
1992 {{
1993 0, // Reserved
1994 CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
1995 0, // Reserved
1996 }},
1997 CFG_DP_FIXED_VOLT_SWING, // CfgDpFixedVoltSwingType
1998 CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG, // CfgDimmTypeUsedInMixedConfig
1999 CFG_HYBRID_BOOST_ENABLE, // CfgHybridBoostEnable
2000 CFG_GNB_IOAPIC_ADDRESS, // CfgGnbIoapicAddress
2001 CFG_ENABLE_DATA_EYE, // CfgDataEyeEn
2002 CFG_DOCKED_TDP_HEADROOM, // CfgDockedTdpHeadroom
2003 CFG_DRAM_DOUBLE_REFRESH_RATE, // CfgDramDoubleRefreshRateEn
2004 0, //reserved...
2005};
2006
2007CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2008{
2009 #if AGESA_ENTRY_INIT_RESET == TRUE
2010 { AMD_INIT_RESET,
2011 sizeof (AMD_RESET_PARAMS),
2012 (PF_AGESA_FUNCTION) AmdInitResetConstructor,
2013 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2014 AMD_INIT_RESET_HANDLE
2015 },
2016 #endif
2017
2018 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2019 { AMD_INIT_RECOVERY,
2020 sizeof (AMD_RECOVERY_PARAMS),
2021 (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
2022 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2023 AMD_INIT_POST_HANDLE
2024 },
2025 #endif
2026
2027 #if AGESA_ENTRY_INIT_EARLY == TRUE
2028 { AMD_INIT_EARLY,
2029 sizeof (AMD_EARLY_PARAMS),
2030 (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
2031 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2032 AMD_INIT_EARLY_HANDLE
2033 },
2034 #endif
2035
2036 #if AGESA_ENTRY_INIT_ENV == TRUE
2037 { AMD_INIT_ENV,
2038 sizeof (AMD_ENV_PARAMS),
2039 (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
2040 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2041 AMD_INIT_ENV_HANDLE
2042 },
2043 #endif
2044
2045 #if AGESA_ENTRY_INIT_LATE == TRUE
2046 { AMD_INIT_LATE,
2047 sizeof (AMD_LATE_PARAMS),
2048 (PF_AGESA_FUNCTION) AmdInitLateInitializer,
2049 (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
2050 AMD_INIT_LATE_HANDLE
2051 },
2052 #endif
2053
2054 #if AGESA_ENTRY_INIT_MID == TRUE
2055 { AMD_INIT_MID,
2056 sizeof (AMD_MID_PARAMS),
2057 (PF_AGESA_FUNCTION) AmdInitMidInitializer,
2058 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2059 AMD_INIT_MID_HANDLE
2060 },
2061 #endif
2062
2063 #if AGESA_ENTRY_INIT_POST == TRUE
2064 { AMD_INIT_POST,
2065 sizeof (AMD_POST_PARAMS),
2066 (PF_AGESA_FUNCTION) AmdInitPostInitializer,
2067 (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
2068 AMD_INIT_POST_HANDLE
2069 },
2070 #endif
2071
2072 #if AGESA_ENTRY_INIT_RESUME == TRUE
2073 { AMD_INIT_RESUME,
2074 sizeof (AMD_RESUME_PARAMS),
2075 (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
2076 (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
2077 AMD_INIT_RESUME_HANDLE
2078 },
2079 #endif
2080
2081 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2082 { AMD_S3LATE_RESTORE,
2083 sizeof (AMD_S3LATE_PARAMS),
2084 (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
2085 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2086 AMD_S3_LATE_RESTORE_HANDLE
2087 },
2088 #endif
2089
2090 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2091 { AMD_S3_SAVE,
2092 sizeof (AMD_S3SAVE_PARAMS),
2093 (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
2094 (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
2095 AMD_S3_SAVE_HANDLE
2096 },
2097 #endif
2098
2099 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2100 { AMD_LATE_RUN_AP_TASK,
2101 sizeof (AP_EXE_PARAMS),
2102 (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
2103 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2104 AMD_LATE_RUN_AP_TASK_HANDLE
2105 },
2106 #endif
2107 { 0, 0, NULL, NULL, 0 }
2108};
2109
2110CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
2111
2112CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2113{
2114 { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
2115 { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
2116
2117 #if AGESA_ENTRY_INIT_RESET == TRUE
2118 { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
2119 #endif
2120
2121 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2122 { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
2123 #endif
2124
2125 #if AGESA_ENTRY_INIT_EARLY == TRUE
2126 { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
2127 #endif
2128
2129 #if AGESA_ENTRY_INIT_POST == TRUE
2130 { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
2131 #if OPTION_DATA_EYE == TRUE
2132 { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye },
2133 #endif
2134 #endif
2135
2136 #if AGESA_ENTRY_INIT_ENV == TRUE
2137 { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
2138 #endif
2139
2140 #if AGESA_ENTRY_INIT_MID == TRUE
2141 { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
2142 #endif
2143
2144 #if AGESA_ENTRY_INIT_LATE == TRUE
2145 { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
2146 #endif
2147
2148 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2149 { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
2150 #endif
2151
2152 #if AGESA_ENTRY_INIT_RESUME == TRUE
2153 { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
2154 #endif
2155
2156 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2157 { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
2158 #endif
2159
2160 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2161 { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
2162 { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
2163 { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
2164 { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
2165 { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
2166 { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
2167 #endif
2168
2169 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2170 { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
2171 #endif
2172 { 0, NULL }
2173};
2174
2175CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2176{
2177 IDS_LATE_RUN_AP_TASK
2178 // Get DMI info
2179 CPU_DMI_AP_GET_TYPE4_TYPE7
2180 // Probe filter enable
2181 L3_FEAT_AP_DISABLE_CACHE
2182 L3_FEAT_AP_ENABLE_CACHE
2183 // Cpu Prefetch Mode
2184 CPU_PREFETCH_MODE_AP_TASK
2185 { 0, NULL }
2186};
2187
2188#if AGESA_ENTRY_INIT_EARLY == TRUE
2189 #if IDSOPT_IDS_ENABLED == TRUE
2190 #if IDSOPT_TRACING_ENABLED == TRUE
2191 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2192 CONST CHAR8 *BldOptDebugOutput[] = {
2193 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2194 //Build Option Area
2195 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2196 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2197 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2198 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2199 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2200 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2201 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2202 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2203 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2204 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2205 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2206 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2207 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2208 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2209 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2210 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2211 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2212 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2213
2214 //Build Configuration Area
2215 // CoreVrm
2216 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2217 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2218 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2219 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2220 MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
2221 MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL)
2222 // NbVrm
2223 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2224 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2225 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2226 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2227 MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
2228 MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL)
2229
2230 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2231 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2232 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2233 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2234 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2235 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2236 MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3)
2237 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2238 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2239 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2240 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2241 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2242
2243 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2244 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2245 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2246 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2247 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2248 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2249
2250 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2251
2252 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2253 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2254 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2255 MAKE_DBG_STR (\nPowerCeiling , CFG_AMD_POWER_CEILING),
2256 MAKE_DBG_STR (\nHtcTempLimit , CFG_HTC_TEMPERATURE_LIMIT)
2257 MAKE_DBG_STR (\nLhtcTempLimit , CFG_LHTC_TEMPERATURE_LIMIT)
2258
2259 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2260 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2261 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2262
2263 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2264 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2265 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2266 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2267 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2268 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2269 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2270 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2271 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2272 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2273 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2274
2275 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2276 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2277 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2278 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2279 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2280 MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2281 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2282 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2283 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2284
2285 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2286 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2287 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2288 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2289
2290 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2291 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2292 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2293 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2294 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2295 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2296 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2297 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2298 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2299 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2300 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2301
2302 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2303 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2304 MAKE_DBG_STR (\nAcpiPstatesPsdPolicy , CFG_ACPI_PSTATES_PSD_POLICY)
2305
2306 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2307
2308 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2309 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2310 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2311 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2312 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2313 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2314 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2315 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2316 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2317 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID)
2318 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID)
2319 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID)
2320 MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT)
2321 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2322 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2323 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2324 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2325 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2326 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2327 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2328 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2329 MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2330 MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2331 MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2332 MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE),
2333 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2334 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2335 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2336 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2337 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2338 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2339 MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF),
2340 MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE),
2341 MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG),
2342 MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST),
2343 MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
2344 MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY),
2345 MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION),
2346 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
2347 MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
2348 MAKE_DBG_STR (\nCfgDataEyeEn , CFG_ENABLE_DATA_EYE),
2349 MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn , CFG_DRAM_DOUBLE_REFRESH_RATE),
2350 #endif
2351 NULL
2352 };
2353 #endif
2354 #endif
2355#endif
2356
2357// Needed for floating point support, linker expects this symbol to be defined.
2358#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
2359 CONST INT32 _fltused = 0;
2360#endif
2361