Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2019 - 2020 Intel Corporation |
| 5 | ## Copyright (C) 2019 - 2020 Facebook Inc |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; either version 2 of the License, or |
| 10 | ## (at your option) any later version. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | |
| 18 | config SOC_INTEL_XEON_SP |
| 19 | bool |
| 20 | help |
| 21 | Intel Xeon SP support |
| 22 | |
| 23 | if SOC_INTEL_XEON_SP |
| 24 | |
| 25 | config CPU_SPECIFIC_OPTIONS |
| 26 | def_bool y |
| 27 | select ARCH_BOOTBLOCK_X86_32 |
| 28 | select ARCH_RAMSTAGE_X86_32 |
| 29 | select ARCH_ROMSTAGE_X86_32 |
| 30 | select ARCH_VERSTAGE_X86_32 |
| 31 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 32 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 33 | select POSTCAR_CONSOLE |
| 34 | select SOC_INTEL_COMMON |
| 35 | select SOC_INTEL_COMMON_RESET |
| 36 | select PLATFORM_USES_FSP2_0 |
| 37 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| 38 | select FSP_T_XIP |
| 39 | select FSP_M_XIP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 40 | select POSTCAR_STAGE |
| 41 | select IOAPIC |
| 42 | select PARALLEL_MP |
| 43 | select SMP |
| 44 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 45 | select COMMON_FADT |
| 46 | select SOC_INTEL_COMMON_BLOCK |
| 47 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 48 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 49 | select SOC_INTEL_COMMON_BLOCK_LPC |
| 50 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 51 | select SOC_INTEL_COMMON_BLOCK_SPI |
| 52 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| 53 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 54 | select TSC_MONOTONIC_TIMER |
| 55 | select UDELAY_TSC |
| 56 | select SUPPORT_CPU_UCODE_IN_CBFS |
Nico Huber | 0266be0 | 2020-03-08 18:36:00 +0100 | [diff] [blame^] | 57 | select MICROCODE_BLOB_NOT_HOOKED_UP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 58 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 59 | |
| 60 | config MAINBOARD_USES_FSP2_0 |
| 61 | bool |
| 62 | default y |
| 63 | |
| 64 | config USE_FSP2_0_DRIVER |
| 65 | def_bool y |
| 66 | depends on MAINBOARD_USES_FSP2_0 |
| 67 | select PLATFORM_USES_FSP2_0 |
| 68 | select UDK_2015_BINDING |
| 69 | select POSTCAR_CONSOLE |
| 70 | select POSTCAR_STAGE |
| 71 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 72 | config FSP_HEADER_PATH |
| 73 | string "Location of FSP headers" |
| 74 | depends on MAINBOARD_USES_FSP2_0 |
| 75 | default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" |
| 76 | |
| 77 | config MAX_SOCKET |
| 78 | int |
| 79 | default 2 |
| 80 | |
| 81 | # For 2S config, the number of cpus could be as high as |
| 82 | # 2 threads * 20 cores * 2 sockets |
| 83 | config MAX_CPUS |
| 84 | int |
| 85 | default 80 |
| 86 | |
| 87 | config PCR_BASE_ADDRESS |
| 88 | hex |
| 89 | default 0xfd000000 |
| 90 | help |
| 91 | This option allows you to select MMIO Base Address of sideband bus. |
| 92 | |
| 93 | config DCACHE_RAM_BASE |
| 94 | hex |
| 95 | default 0xfe800000 |
| 96 | |
| 97 | config DCACHE_RAM_SIZE |
| 98 | hex |
| 99 | default 0x200000 |
| 100 | |
| 101 | config DCACHE_BSP_STACK_SIZE |
| 102 | hex |
| 103 | default 0x10000 |
| 104 | |
| 105 | config MMCONF_BASE_ADDRESS |
| 106 | hex |
| 107 | default 0x80000000 |
| 108 | |
| 109 | config CPU_MICROCODE_CBFS_LOC |
| 110 | hex |
| 111 | default 0xfff0fdc0 |
| 112 | |
| 113 | config CPU_MICROCODE_CBFS_LEN |
| 114 | hex |
| 115 | default 0x7C00 |
| 116 | |
| 117 | config C_ENV_BOOTBLOCK_SIZE |
| 118 | hex |
| 119 | default 0xC000 |
| 120 | |
| 121 | config HEAP_SIZE |
| 122 | hex |
| 123 | default 0x80000 |
| 124 | |
| 125 | |
| 126 | endif ## SOC_INTEL_XEON_SP |