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review.coreboot.org / coreboot / d2ebc4d39fa1a99f3582f9e38869ef443cd9d3fb / . / util / inteltool / cpu.c
blob: 74252293de696e804c047a3cb88ed0dad641a5b5 [file] [log] [blame]
Patrick Georgiea063cb2020-05-08 19:28:13 +0200[diff] [blame]1/* inteltool - dump all registers on an Intel CPU + chipset based system */
Patrick Georgi7333a112020-05-08 20:48:04 +0200[diff] [blame]2/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]3
4#include <fcntl.h>
5#include <unistd.h>
6#include <stdio.h>
7#include <stdlib.h>
8#include <string.h>
9#include <errno.h>
Maxim Polyakovd8163ed2019-10-09 18:35:23 +0300[diff] [blame]10#include <limits.h>
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]11
12#include "inteltool.h"
13
Mathias Krause9beb5df2011-06-27 14:35:00 +0200[diff] [blame]14#ifdef __x86_64__
15# define BREG "%%rbx"
16#else
17# define BREG "%%ebx"
18#endif
19
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]20#define IA32_FEATURE_CONTROL 0x3a
21#define SGX_GLOBAL_ENABLED (1 << 18)
22#define FEATURE_CONTROL_LOCKED (1)
23#define MTRR_CAP_MSR 0xfe
24#define PRMRR_SUPPORTED (1 << 12)
25#define SGX_SUPPORTED (1 << 2)
Pratik Prajapati1e678162020-09-03 11:28:19 -0700[diff] [blame]26#define IA32_TME_ACTIVATE 0x982
27#define TME_SUPPORTED (1 << 13)
28#define TME_LOCKED (1)
29#define TME_ENABLED (1 << 1)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]30
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]31int fd_msr;
32
33unsigned int cpuid(unsigned int op)
34{
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]35 uint32_t ret;
36
Mathias Krause5782fee2011-03-09 11:30:55 +0100[diff] [blame]37#if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__)
Stefan Reinauer1c60c882010-05-30 12:35:39 +0000[diff] [blame]38 asm volatile (
Mathias Krause9beb5df2011-06-27 14:35:00 +0200[diff] [blame]39 "push " BREG "\n\t"
40 "cpuid\n\t"
41 "pop " BREG "\n\t"
Stefan Reinauer1c60c882010-05-30 12:35:39 +0000[diff] [blame]42 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
43 );
Stefan Reinauerf1824562009-04-22 23:17:44 +0000[diff] [blame]44#else
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]45 asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
Stefan Reinauerf1824562009-04-22 23:17:44 +0000[diff] [blame]46#endif
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]47
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]48 return ret;
49}
50
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]51inline cpuid_result_t cpuid_ext(int op, unsigned int ecx)
52{
53 cpuid_result_t result;
54
55#ifndef __DARWIN__
56 asm volatile (
57 "mov %%ebx, %%edi;"
58 "cpuid;"
59 "mov %%ebx, %%esi;"
60 "mov %%edi, %%ebx;"
61 : "=a" (result.eax),
62 "=S" (result.ebx),
63 "=c" (result.ecx),
64 "=d" (result.edx)
65 : "0" (op), "2" (ecx)
66 : "edi");
67#endif
68 return result;
69}
70
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]71#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]72int msr_readerror = 0;
73
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]74static msr_t rdmsr(int addr)
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]75{
Stefan Reinauera7b296d2011-11-14 12:40:34 -0800[diff] [blame]76 uint32_t buf[2];
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]77 msr_t msr = { 0xffffffff, 0xffffffff };
78
79 if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
80 perror("Could not lseek() to MSR");
81 close(fd_msr);
82 exit(1);
83 }
84
85 if (read(fd_msr, buf, 8) == 8) {
Stefan Reinauera7b296d2011-11-14 12:40:34 -0800[diff] [blame]86 msr.lo = buf[0];
87 msr.hi = buf[1];
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]88 return msr;
89 }
90
91 if (errno == 5) {
92 printf(" (*)"); // Not all bits of the MSR could be read
93 msr_readerror = 1;
94 } else {
95 // A severe error.
96 perror("Could not read() MSR");
97 close(fd_msr);
98 exit(1);
99 }
100
101 return msr;
102}
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]103
104static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd)
105{
Jacob Garber198c2e62019-07-01 11:04:41 -0600[diff] [blame]106 char dev[32];
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]107 char temp_string[50];
108
109 snprintf(dev, sizeof(dev), "/dev/cpu/%d/msr", cpu);
110 *fd = open(dev, mode);
111
112 if (*fd < 0) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]113 snprintf(temp_string, sizeof(temp_string), "open(\"%s\")", dev);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]114 perror(temp_string);
115 return -1;
116 }
117
118 if (lseek(*fd, msr, SEEK_SET) == (off_t)-1) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]119 snprintf(temp_string, sizeof(temp_string), "lseek(%lu)", msr);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]120 perror(temp_string);
121 close(*fd);
122 return -1;
123 }
124
125 return 0;
126}
127
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]128static msr_t rdmsr_from_cpu(int cpu, unsigned long addr)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]129{
130 int fd;
131 msr_t msr = { 0xffffffff, 0xffffffff };
132 uint32_t buf[2];
133 char temp_string[50];
134
135 if (open_and_seek(cpu, addr, O_RDONLY, &fd) < 0) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]136 snprintf(temp_string, sizeof(temp_string),
137 "Could not read MSR for CPU#%d", cpu);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]138 perror(temp_string);
139 }
140
141 if (read(fd, buf, 8) == 8) {
142 msr.lo = buf[0];
143 msr.hi = buf[1];
144 }
145
146 close(fd);
147
148 return msr;
149}
150
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]151static int get_number_of_cpus(void)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]152{
153 return sysconf(_SC_NPROCESSORS_ONLN);
154}
155
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]156static int get_number_of_cores(void)
157{
158 return sysconf(_SC_NPROCESSORS_CONF);
159}
160
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]161static int is_sgx_supported(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]162{
163 cpuid_result_t cpuid_regs;
164 msr_t msr;
165
166 /* CPUID leaf 0x7 subleaf 0x0 to detect SGX support
167 details are mentioned in Intel SDM Chap.36- section 36.7 */
168 cpuid_regs = cpuid_ext(0x7, 0x0);
169 msr = rdmsr_from_cpu(cpunum, MTRR_CAP_MSR);
170 return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED));
171}
172
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]173static int is_sgx_enabled(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]174{
175 msr_t data;
176 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
177 return (data.lo & SGX_GLOBAL_ENABLED);
178}
179
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]180static int is_sgx_locked(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]181{
182 msr_t data;
183 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
184 return (data.lo & FEATURE_CONTROL_LOCKED);
185}
186
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]187#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]188
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]189int print_sgx(void)
190{
191 int error = -1;
192#ifndef __DARWIN__
193 int ncpus = get_number_of_cpus();
194 int i = 0;
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]195
196 printf("\n============= Dumping INTEL SGX status =============");
197
198 if (ncpus < 1) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]199 perror("Failed to get number of CPUs");
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]200 error = -1;
201 } else {
202 printf("\nNumber of CPUs = %d\n", ncpus);
203 for (i = 0; i < ncpus ; i++) {
204
205 printf("------------- CPU %d ----------------\n", i);
206 printf("SGX supported : %s\n",
207 is_sgx_supported(i) ? "YES" : "NO");
208 printf("SGX enabled : %s\n",
209 is_sgx_enabled(i) ? "YES" : "NO");
210 printf("Feature Control locked : %s\n",
211 is_sgx_locked(i) ? "YES" : "NO");
212 }
213 error = 0;
214 }
215 printf("====================================================\n");
216#endif
217 return error;
218}
219
Pratik Prajapati1e678162020-09-03 11:28:19 -0700[diff] [blame]220static int is_tme_supported()
221{
222 cpuid_result_t cpuid_regs;
223
224 /*
225 * CPUID leaf 0x7 subleaf 0x0 to detect TME support
226 * https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key
227 * -Total-Memory-Encryption-Spec.pdf
228 */
229
230 cpuid_regs = cpuid_ext(0x7, 0x0);
231 return (cpuid_regs.ecx & TME_SUPPORTED);
232}
233
234static msr_t read_tme_activate_msr(){
235 return rdmsr_from_cpu(0, IA32_TME_ACTIVATE);
236}
237
238static int is_tme_locked()
239{
240 msr_t data = read_tme_activate_msr();
241 return (data.lo & TME_LOCKED);
242}
243
244static int is_tme_enabled()
245{
246 msr_t data = read_tme_activate_msr();
247 return (data.lo & TME_ENABLED);
248}
249
250void print_tme(void)
251{
252#ifndef __DARWIN__
253 int tme_supported = is_tme_supported();
254
255 printf("\n============= Dumping INTEL TME status =============\n");
256
257 printf("TME supported : %s\n", tme_supported ? "YES" : "NO");
258
259 if (tme_supported) {
260 printf("TME locked : %s\n", is_tme_locked() ? "YES" : "NO");
261 printf("TME enabled : %s\n", is_tme_enabled() ? "YES" : "NO");
262 }
263 printf("====================================================\n");
264#else
265 printf("Not Implemented\n");
266#endif
267}
268
Maxim Polyakovd8163ed2019-10-09 18:35:23 +0300[diff] [blame]269int print_intel_msrs(unsigned int range_start, unsigned int range_end)
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]270{
Maxim Polyakovd8163ed2019-10-09 18:35:23 +0300[diff] [blame]271 unsigned int i, core, id;
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]272 msr_t msr;
273
274#define IA32_PLATFORM_ID 0x0017
275#define EBL_CR_POWERON 0x002a
276#define FSB_CLK_STS 0x00cd
277#define IA32_TIME_STAMP_COUNTER 0x0010
278#define IA32_APIC_BASE 0x001b
279
280 typedef struct {
281 int number;
282 char *name;
283 } msr_entry_t;
284
Tobias Diedrich3645e612010-11-27 14:44:19 +0000[diff] [blame]285 /* Pentium III */
286 static const msr_entry_t model67x_global_msrs[] = {
287 { 0x0000, "IA32_P5_MC_ADDR" },
288 { 0x0001, "IA32_P5_MC_TYPE" },
289 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
290 { 0x0017, "IA32_PLATFORM_ID" },
291 { 0x001b, "IA32_APIC_BASE" },
292 { 0x002a, "EBL_CR_POWERON" },
293 { 0x0033, "TEST_CTL" },
294 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
295 { 0x0088, "BBL_CR_D0" },
296 { 0x0089, "BBL_CR_D1" },
297 { 0x008a, "BBL_CR_D2" },
298 { 0x008b, "IA32_BIOS_SIGN_ID" },
299 { 0x00c1, "PERFCTR0" },
300 { 0x00c2, "PERFCTR1" },
301 { 0x00fe, "IA32_MTRRCAP" },
302 { 0x0116, "BBL_CR_ADDR" },
303 { 0x0118, "BBL_CR_DECC" },
304 { 0x0119, "BBL_CR_CTL" },
305 //{ 0x011a, "BBL_CR_TRIG" },
306 { 0x011b, "BBL_CR_BUSY" },
307 { 0x011e, "BBL_CR_CTL3" },
308 { 0x0174, "IA32_SYSENTER_CS" },
309 { 0x0175, "IA32_SYSENTER_ESP" },
310 { 0x0176, "IA32_SYSENTER_EIP" },
311 { 0x0179, "IA32_MCG_CAP" },
312 { 0x017a, "IA32_MCG_STATUS" },
313 { 0x017b, "IA32_MCG_CTL" },
314 { 0x0186, "IA32_PERF_EVNTSEL0" },
315 { 0x0187, "IA32_PERF_EVNTSEL1" },
316 { 0x01d9, "IA32_DEBUGCTL" },
317 { 0x01db, "MSR_LASTBRANCHFROMIP" },
318 { 0x01dc, "MSR_LASTBRANCHTOIP" },
319 { 0x01dd, "MSR_LASTINTFROMIP" },
320 { 0x01de, "MSR_LASTINTTOIP" },
321 { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" },
322 { 0x0200, "IA32_MTRR_PHYSBASE0" },
323 { 0x0201, "IA32_MTRR_PHYSMASK0" },
324 { 0x0202, "IA32_MTRR_PHYSBASE1" },
325 { 0x0203, "IA32_MTRR_PHYSMASK1" },
326 { 0x0204, "IA32_MTRR_PHYSBASE2" },
327 { 0x0205, "IA32_MTRR_PHYSMASK2" },
328 { 0x0206, "IA32_MTRR_PHYSBASE3" },
329 { 0x0207, "IA32_MTRR_PHYSMASK3" },
330 { 0x0208, "IA32_MTRR_PHYSBASE4" },
331 { 0x0209, "IA32_MTRR_PHYSMASK4" },
332 { 0x020a, "IA32_MTRR_PHYSBASE5" },
333 { 0x020b, "IA32_MTRR_PHYSMASK5" },
334 { 0x020c, "IA32_MTRR_PHYSBASE6" },
335 { 0x020d, "IA32_MTRR_PHYSMASK6" },
336 { 0x020e, "IA32_MTRR_PHYSBASE7" },
337 { 0x020f, "IA32_MTRR_PHYSMASK7" },
338 { 0x0250, "IA32_MTRR_FIX64K_00000" },
339 { 0x0258, "IA32_MTRR_FIX16K_80000" },
340 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
341 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
342 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
343 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
344 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
345 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
346 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
347 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
348 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
349 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
350 { 0x0400, "IA32_MC0_CTL" },
351 { 0x0401, "IA32_MC0_STATUS" },
352 { 0x0402, "IA32_MC0_ADDR" },
353 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
354 { 0x0404, "IA32_MC1_CTL" },
355 { 0x0405, "IA32_MC1_STATUS" },
356 { 0x0406, "IA32_MC1_ADDR" },
357 //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
358 { 0x0408, "IA32_MC2_CTL" },
359 { 0x0409, "IA32_MC2_STATUS" },
360 { 0x040a, "IA32_MC2_ADDR" },
361 //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
362 { 0x040c, "IA32_MC4_CTL" },
363 { 0x040d, "IA32_MC4_STATUS" },
364 { 0x040e, "IA32_MC4_ADDR" },
365 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
366 { 0x0410, "IA32_MC3_CTL" },
367 { 0x0411, "IA32_MC3_STATUS" },
368 { 0x0412, "IA32_MC3_ADDR" },
369 //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
370 };
371
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]372 static const msr_entry_t model6bx_global_msrs[] = {
373 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
374 { 0x0017, "IA32_PLATFORM_ID" },
375 { 0x001b, "IA32_APIC_BASE" },
376 { 0x002a, "EBL_CR_POWERON" },
377 { 0x0033, "TEST_CTL" },
378 { 0x003f, "THERM_DIODE_OFFSET" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]379 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]380 { 0x008b, "IA32_BIOS_SIGN_ID" },
381 { 0x00c1, "PERFCTR0" },
382 { 0x00c2, "PERFCTR1" },
383 { 0x011e, "BBL_CR_CTL3" },
384 { 0x0179, "IA32_MCG_CAP" },
385 { 0x017a, "IA32_MCG_STATUS" },
386 { 0x0198, "IA32_PERF_STATUS" },
387 { 0x0199, "IA32_PERF_CONTROL" },
388 { 0x019a, "IA32_CLOCK_MODULATION" },
389 { 0x01a0, "IA32_MISC_ENABLES" },
390 { 0x01d9, "IA32_DEBUGCTL" },
391 { 0x0200, "IA32_MTRR_PHYSBASE0" },
392 { 0x0201, "IA32_MTRR_PHYSMASK0" },
393 { 0x0202, "IA32_MTRR_PHYSBASE1" },
394 { 0x0203, "IA32_MTRR_PHYSMASK1" },
395 { 0x0204, "IA32_MTRR_PHYSBASE2" },
396 { 0x0205, "IA32_MTRR_PHYSMASK2" },
397 { 0x0206, "IA32_MTRR_PHYSBASE3" },
398 { 0x0207, "IA32_MTRR_PHYSMASK3" },
399 { 0x0208, "IA32_MTRR_PHYSBASE4" },
400 { 0x0209, "IA32_MTRR_PHYSMASK4" },
401 { 0x020a, "IA32_MTRR_PHYSBASE5" },
402 { 0x020b, "IA32_MTRR_PHYSMASK5" },
403 { 0x020c, "IA32_MTRR_PHYSBASE6" },
404 { 0x020d, "IA32_MTRR_PHYSMASK6" },
405 { 0x020e, "IA32_MTRR_PHYSBASE7" },
406 { 0x020f, "IA32_MTRR_PHYSMASK7" },
407 { 0x0250, "IA32_MTRR_FIX64K_00000" },
408 { 0x0258, "IA32_MTRR_FIX16K_80000" },
409 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
410 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
411 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
412 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
413 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
414 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
415 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
416 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
417 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
418 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
419 { 0x0400, "IA32_MC0_CTL" },
420 { 0x0401, "IA32_MC0_STATUS" },
421 { 0x0402, "IA32_MC0_ADDR" },
422 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
423 { 0x040c, "IA32_MC4_CTL" },
424 { 0x040d, "IA32_MC4_STATUS" },
425 { 0x040e, "IA32_MC4_ADDR" },
426 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
427 };
428
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]429 static const msr_entry_t model6ex_global_msrs[] = {
430 { 0x0017, "IA32_PLATFORM_ID" },
431 { 0x002a, "EBL_CR_POWERON" },
432 { 0x00cd, "FSB_CLOCK_STS" },
433 { 0x00ce, "FSB_CLOCK_VCC" },
434 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
435 { 0x00e3, "PMG_IO_BASE_ADDR" },
436 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
437 { 0x00ee, "EXT_CONFIG" },
438 { 0x011e, "BBL_CR_CTL3" },
439 { 0x0194, "CLOCK_FLEX_MAX" },
440 { 0x0198, "IA32_PERF_STATUS" },
441 { 0x01a0, "IA32_MISC_ENABLES" },
442 { 0x01aa, "PIC_SENS_CFG" },
443 { 0x0400, "IA32_MC0_CTL" },
444 { 0x0401, "IA32_MC0_STATUS" },
445 { 0x0402, "IA32_MC0_ADDR" },
446 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
447 { 0x040c, "IA32_MC4_CTL" },
448 { 0x040d, "IA32_MC4_STATUS" },
449 { 0x040e, "IA32_MC4_ADDR" },
450 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
451 };
452
453 static const msr_entry_t model6ex_per_core_msrs[] = {
454 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
455 { 0x001b, "IA32_APIC_BASE" },
456 { 0x003a, "IA32_FEATURE_CONTROL" },
457 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
458 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
459 { 0x008b, "IA32_BIOS_SIGN_ID" },
460 { 0x00e7, "IA32_MPERF" },
461 { 0x00e8, "IA32_APERF" },
462 { 0x00fe, "IA32_MTRRCAP" },
463 { 0x015f, "DTS_CAL_CTRL" },
464 { 0x0179, "IA32_MCG_CAP" },
465 { 0x017a, "IA32_MCG_STATUS" },
466 { 0x0199, "IA32_PERF_CONTROL" },
467 { 0x019a, "IA32_CLOCK_MODULATION" },
468 { 0x019b, "IA32_THERM_INTERRUPT" },
469 { 0x019c, "IA32_THERM_STATUS" },
470 { 0x019d, "GV_THERM" },
471 { 0x01d9, "IA32_DEBUGCTL" },
472 { 0x0200, "IA32_MTRR_PHYSBASE0" },
473 { 0x0201, "IA32_MTRR_PHYSMASK0" },
474 { 0x0202, "IA32_MTRR_PHYSBASE1" },
475 { 0x0203, "IA32_MTRR_PHYSMASK1" },
476 { 0x0204, "IA32_MTRR_PHYSBASE2" },
477 { 0x0205, "IA32_MTRR_PHYSMASK2" },
478 { 0x0206, "IA32_MTRR_PHYSBASE3" },
479 { 0x0207, "IA32_MTRR_PHYSMASK3" },
480 { 0x0208, "IA32_MTRR_PHYSBASE4" },
481 { 0x0209, "IA32_MTRR_PHYSMASK4" },
482 { 0x020a, "IA32_MTRR_PHYSBASE5" },
483 { 0x020b, "IA32_MTRR_PHYSMASK5" },
484 { 0x020c, "IA32_MTRR_PHYSBASE6" },
485 { 0x020d, "IA32_MTRR_PHYSMASK6" },
486 { 0x020e, "IA32_MTRR_PHYSBASE7" },
487 { 0x020f, "IA32_MTRR_PHYSMASK7" },
488 { 0x0250, "IA32_MTRR_FIX64K_00000" },
489 { 0x0258, "IA32_MTRR_FIX16K_80000" },
490 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
491 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
492 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
493 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
494 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
495 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
496 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
497 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
498 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
499 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
500 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
501 };
502
503 static const msr_entry_t model6fx_global_msrs[] = {
504 { 0x0017, "IA32_PLATFORM_ID" },
505 { 0x002a, "EBL_CR_POWERON" },
506 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
507 { 0x00a8, "EMTTM_CR_TABLE0" },
508 { 0x00a9, "EMTTM_CR_TABLE1" },
509 { 0x00aa, "EMTTM_CR_TABLE2" },
510 { 0x00ab, "EMTTM_CR_TABLE3" },
511 { 0x00ac, "EMTTM_CR_TABLE4" },
512 { 0x00ad, "EMTTM_CR_TABLE5" },
513 { 0x00cd, "FSB_CLOCK_STS" },
514 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
515 { 0x00e3, "PMG_IO_BASE_ADDR" },
516 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
517 { 0x00ee, "EXT_CONFIG" },
518 { 0x011e, "BBL_CR_CTL3" },
519 { 0x0194, "CLOCK_FLEX_MAX" },
520 { 0x0198, "IA32_PERF_STATUS" },
521 { 0x01a0, "IA32_MISC_ENABLES" },
522 { 0x01aa, "PIC_SENS_CFG" },
523 { 0x0400, "IA32_MC0_CTL" },
524 { 0x0401, "IA32_MC0_STATUS" },
525 { 0x0402, "IA32_MC0_ADDR" },
526 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
527 { 0x040c, "IA32_MC4_CTL" },
528 { 0x040d, "IA32_MC4_STATUS" },
529 { 0x040e, "IA32_MC4_ADDR" },
530 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
531 };
532
533 static const msr_entry_t model6fx_per_core_msrs[] = {
534 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
535 { 0x001b, "IA32_APIC_BASE" },
536 { 0x003a, "IA32_FEATURE_CONTROL" },
537 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
538 { 0x008b, "IA32_BIOS_SIGN_ID" },
539 { 0x00e1, "SMM_CST_MISC_INFO" },
540 { 0x00e7, "IA32_MPERF" },
541 { 0x00e8, "IA32_APERF" },
542 { 0x00fe, "IA32_MTRRCAP" },
543 { 0x0179, "IA32_MCG_CAP" },
544 { 0x017a, "IA32_MCG_STATUS" },
545 { 0x0199, "IA32_PERF_CONTROL" },
546 { 0x019a, "IA32_THERM_CTL" },
547 { 0x019b, "IA32_THERM_INTERRUPT" },
548 { 0x019c, "IA32_THERM_STATUS" },
549 { 0x019d, "MSR_THERM2_CTL" },
550 { 0x01d9, "IA32_DEBUGCTL" },
551 { 0x0200, "IA32_MTRR_PHYSBASE0" },
552 { 0x0201, "IA32_MTRR_PHYSMASK0" },
553 { 0x0202, "IA32_MTRR_PHYSBASE1" },
554 { 0x0203, "IA32_MTRR_PHYSMASK1" },
555 { 0x0204, "IA32_MTRR_PHYSBASE2" },
556 { 0x0205, "IA32_MTRR_PHYSMASK2" },
557 { 0x0206, "IA32_MTRR_PHYSBASE3" },
558 { 0x0207, "IA32_MTRR_PHYSMASK3" },
559 { 0x0208, "IA32_MTRR_PHYSBASE4" },
560 { 0x0209, "IA32_MTRR_PHYSMASK4" },
561 { 0x020a, "IA32_MTRR_PHYSBASE5" },
562 { 0x020b, "IA32_MTRR_PHYSMASK5" },
563 { 0x020c, "IA32_MTRR_PHYSBASE6" },
564 { 0x020d, "IA32_MTRR_PHYSMASK6" },
565 { 0x020e, "IA32_MTRR_PHYSBASE7" },
566 { 0x020f, "IA32_MTRR_PHYSMASK7" },
567 { 0x0250, "IA32_MTRR_FIX64K_00000" },
568 { 0x0258, "IA32_MTRR_FIX16K_80000" },
569 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
570 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
571 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
572 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
573 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
574 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
575 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
576 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
577 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
578 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
579 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
580 };
581
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]582 /* Pentium 4 and XEON */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]583 /*
584 * All MSRs per
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]585 *
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]586 * Intel 64 and IA-32 Architectures Software Developer's Manual
587 * Volume 3B: System Programming Guide, Part 2
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]588 *
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]589 * Table B-5, B-7
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]590 */
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]591 static const msr_entry_t modelf2x_global_msrs[] = {
592 { 0x0000, "IA32_P5_MC_ADDR" },
593 { 0x0001, "IA32_P5_MC_TYPE" },
594 /* 0x6: Not available in model 2. */
595 { 0x0017, "IA32_PLATFORM_ID" },
596 { 0x002a, "MSR_EBC_HARD_POWERON" },
Elyes HAOUASe3e2bb02016-07-26 18:34:14 +0200[diff] [blame]597 { 0x002b, "MSR_EBC_SOFT_POWERON" },
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]598 /* 0x2c: Not available in model 2. */
599// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
600 { 0x019c, "IA32_THERM_STATUS" },
601 /* 0x19d: Not available in model 2. */
602 { 0x01a0, "IA32_MISC_ENABLE" },
603 /* 0x1a1: Not available in model 2. */
604 { 0x0200, "IA32_MTRR_PHYSBASE0" },
605 { 0x0201, "IA32_MTRR_PHYSMASK0" },
606 { 0x0202, "IA32_MTRR_PHYSBASE1" },
607 { 0x0203, "IA32_MTRR_PHYSMASK1" },
608 { 0x0204, "IA32_MTRR_PHYSBASE2" },
609 { 0x0205, "IA32_MTRR_PHYSMASK2" },
610 { 0x0206, "IA32_MTRR_PHYSBASE3" },
611 { 0x0207, "IA32_MTRR_PHYSMASK3" },
612 { 0x0208, "IA32_MTRR_PHYSBASE4" },
613 { 0x0209, "IA32_MTRR_PHYSMASK4" },
614 { 0x020a, "IA32_MTRR_PHYSBASE5" },
615 { 0x020b, "IA32_MTRR_PHYSMASK5" },
616 { 0x020c, "IA32_MTRR_PHYSBASE6" },
617 { 0x020d, "IA32_MTRR_PHYSMASK6" },
618 { 0x020e, "IA32_MTRR_PHYSBASE7" },
619 { 0x020f, "IA32_MTRR_PHYSMASK7" },
620 { 0x0250, "IA32_MTRR_FIX64K_00000" },
621 { 0x0258, "IA32_MTRR_FIX16K_80000" },
622 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
623 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
624 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
625 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
626 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
627 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
628 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
629 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
630 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
631 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
632 { 0x0300, "MSR_BPU_COUNTER0" },
633 { 0x0301, "MSR_BPU_COUNTER1" },
634 { 0x0302, "MSR_BPU_COUNTER2" },
635 { 0x0303, "MSR_BPU_COUNTER3" },
636 { 0x0304, "MSR_MS_COUNTER0" },
637 { 0x0305, "MSR_MS_COUNTER1" },
638 { 0x0306, "MSR_MS_COUNTER2" },
639 { 0x0307, "MSR_MS_COUNTER3" },
640 { 0x0308, "MSR_FLAME_COUNTER0" },
641 { 0x0309, "MSR_FLAME_COUNTER1" },
642 { 0x030a, "MSR_FLAME_COUNTER2" },
643 { 0x030b, "MSR_FLAME_COUNTER3" },
644 { 0x030c, "MSR_IQ_COUNTER0" },
645 { 0x030d, "MSR_IQ_COUNTER1" },
646 { 0x030e, "MSR_IQ_COUNTER2" },
647 { 0x030f, "MSR_IQ_COUNTER3" },
648 { 0x0310, "MSR_IQ_COUNTER4" },
649 { 0x0311, "MSR_IQ_COUNTER5" },
650 { 0x0360, "MSR_BPU_CCCR0" },
651 { 0x0361, "MSR_BPU_CCCR1" },
652 { 0x0362, "MSR_BPU_CCCR2" },
653 { 0x0363, "MSR_BPU_CCCR3" },
654 { 0x0364, "MSR_MS_CCCR0" },
655 { 0x0365, "MSR_MS_CCCR1" },
656 { 0x0366, "MSR_MS_CCCR2" },
657 { 0x0367, "MSR_MS_CCCR3" },
658 { 0x0368, "MSR_FLAME_CCCR0" },
659 { 0x0369, "MSR_FLAME_CCCR1" },
660 { 0x036a, "MSR_FLAME_CCCR2" },
661 { 0x036b, "MSR_FLAME_CCCR3" },
662 { 0x036c, "MSR_IQ_CCCR0" },
663 { 0x036d, "MSR_IQ_CCCR1" },
664 { 0x036e, "MSR_IQ_CCCR2" },
665 { 0x036f, "MSR_IQ_CCCR3" },
666 { 0x0370, "MSR_IQ_CCCR4" },
667 { 0x0371, "MSR_IQ_CCCR5" },
668 { 0x03a0, "MSR_BSU_ESCR0" },
669 { 0x03a1, "MSR_BSU_ESCR1" },
670 { 0x03a2, "MSR_FSB_ESCR0" },
671 { 0x03a3, "MSR_FSB_ESCR1" },
672 { 0x03a4, "MSR_FIRM_ESCR0" },
673 { 0x03a5, "MSR_FIRM_ESCR1" },
674 { 0x03a6, "MSR_FLAME_ESCR0" },
675 { 0x03a7, "MSR_FLAME_ESCR1" },
676 { 0x03a8, "MSR_DAC_ESCR0" },
677 { 0x03a9, "MSR_DAC_ESCR1" },
678 { 0x03aa, "MSR_MOB_ESCR0" },
679 { 0x03ab, "MSR_MOB_ESCR1" },
680 { 0x03ac, "MSR_PMH_ESCR0" },
681 { 0x03ad, "MSR_PMH_ESCR1" },
682 { 0x03ae, "MSR_SAAT_ESCR0" },
683 { 0x03af, "MSR_SAAT_ESCR1" },
684 { 0x03b0, "MSR_U2L_ESCR0" },
685 { 0x03b1, "MSR_U2L_ESCR1" },
686 { 0x03b2, "MSR_BPU_ESCR0" },
687 { 0x03b3, "MSR_BPU_ESCR1" },
688 { 0x03b4, "MSR_IS_ESCR0" },
689 { 0x03b5, "MSR_BPU_ESCR1" },
690 { 0x03b6, "MSR_ITLB_ESCR0" },
691 { 0x03b7, "MSR_ITLB_ESCR1" },
692 { 0x03b8, "MSR_CRU_ESCR0" },
693 { 0x03b9, "MSR_CRU_ESCR1" },
694 { 0x03ba, "MSR_IQ_ESCR0" },
695 { 0x03bb, "MSR_IQ_ESCR1" },
696 { 0x03bc, "MSR_RAT_ESCR0" },
697 { 0x03bd, "MSR_RAT_ESCR1" },
698 { 0x03be, "MSR_SSU_ESCR0" },
699 { 0x03c0, "MSR_MS_ESCR0" },
700 { 0x03c1, "MSR_MS_ESCR1" },
701 { 0x03c2, "MSR_TBPU_ESCR0" },
702 { 0x03c3, "MSR_TBPU_ESCR1" },
703 { 0x03c4, "MSR_TC_ESCR0" },
704 { 0x03c5, "MSR_TC_ESCR1" },
705 { 0x03c8, "MSR_IX_ESCR0" },
706 { 0x03c9, "MSR_IX_ESCR1" },
707 { 0x03ca, "MSR_ALF_ESCR0" },
708 { 0x03cb, "MSR_ALF_ESCR1" },
709 { 0x03cc, "MSR_CRU_ESCR2" },
710 { 0x03cd, "MSR_CRU_ESCR3" },
711 { 0x03e0, "MSR_CRU_ESCR4" },
712 { 0x03e1, "MSR_CRU_ESCR5" },
713 { 0x03f0, "MSR_TC_PRECISE_EVENT" },
714 { 0x03f1, "MSR_PEBS_ENABLE" },
715 { 0x03f2, "MSR_PEBS_MATRIX_VERT" },
716
717 /*
718 * All MCX_ADDR and MCX_MISC MSRs depend on a bit being
719 * set in MCX_STATUS.
720 */
721 { 0x400, "IA32_MC0_CTL" },
722 { 0x401, "IA32_MC0_STATUS" },
723 { 0x402, "IA32_MC0_ADDR" },
724 { 0x403, "IA32_MC0_MISC" },
725 { 0x404, "IA32_MC1_CTL" },
726 { 0x405, "IA32_MC1_STATUS" },
727 { 0x406, "IA32_MC1_ADDR" },
728 { 0x407, "IA32_MC1_MISC" },
729 { 0x408, "IA32_MC2_CTL" },
730 { 0x409, "IA32_MC2_STATUS" },
731 { 0x40a, "IA32_MC2_ADDR" },
732 { 0x40b, "IA32_MC2_MISC" },
733 { 0x40c, "IA32_MC3_CTL" },
734 { 0x40d, "IA32_MC3_STATUS" },
735 { 0x40e, "IA32_MC3_ADDR" },
736 { 0x40f, "IA32_MC3_MISC" },
737 { 0x410, "IA32_MC4_CTL" },
738 { 0x411, "IA32_MC4_STATUS" },
739 { 0x412, "IA32_MC4_ADDR" },
740 { 0x413, "IA32_MC4_MISC" },
741 };
742
743 static const msr_entry_t modelf2x_per_core_msrs[] = {
744 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
745 { 0x001b, "IA32_APIC_BASE" },
746 /* 0x3a: Not available in model 2. */
747 { 0x008b, "IA32_BIOS_SIGN_ID" },
748 /* 0x9b: Not available in model 2. */
749 { 0x00fe, "IA32_MTRRCAP" },
750 { 0x0174, "IA32_SYSENTER_CS" },
751 { 0x0175, "IA32_SYSENTER_ESP" },
752 { 0x0176, "IA32_SYSENTER_EIP" },
753 { 0x0179, "IA32_MCG_CAP" },
754 { 0x017a, "IA32_MCG_STATUS" },
755 { 0x017b, "IA32_MCG_CTL" },
756 { 0x0180, "MSR_MCG_RAX" },
757 { 0x0181, "MSR_MCG_RBX" },
758 { 0x0182, "MSR_MCG_RCX" },
759 { 0x0183, "MSR_MCG_RDX" },
760 { 0x0184, "MSR_MCG_RSI" },
761 { 0x0185, "MSR_MCG_RDI" },
762 { 0x0186, "MSR_MCG_RBP" },
763 { 0x0187, "MSR_MCG_RSP" },
764 { 0x0188, "MSR_MCG_RFLAGS" },
765 { 0x0189, "MSR_MCG_RIP" },
766 { 0x018a, "MSR_MCG_MISC" },
767 /* 0x18b-0x18f: Reserved */
768 { 0x0190, "MSR_MCG_R8" },
769 { 0x0191, "MSR_MCG_R9" },
770 { 0x0192, "MSR_MCG_R10" },
771 { 0x0193, "MSR_MCG_R11" },
772 { 0x0194, "MSR_MCG_R12" },
773 { 0x0195, "MSR_MCG_R13" },
774 { 0x0196, "MSR_MCG_R14" },
775 { 0x0197, "MSR_MCG_R15" },
776 /* 0x198: Not available in model 2. */
777 /* 0x199: Not available in model 2. */
778 { 0x019a, "IA32_CLOCK_MODULATION" },
779 { 0x019b, "IA32_THERM_INTERRUPT" },
780 { 0x01a0, "IA32_MISC_ENABLE" },
781 { 0x01d7, "MSR_LER_FROM_LIP" },
782 { 0x01d8, "MSR_LER_TO_LIP" },
783 { 0x01d9, "MSR_DEBUGCTLA" },
784 { 0x01da, "MSR_LASTBRANCH_TOS" },
785 { 0x01db, "MSR_LASTBRANCH_0" },
786 { 0x01dd, "MSR_LASTBRANCH_2" },
787 { 0x01de, "MSR_LASTBRANCH_3" },
788 { 0x0277, "IA32_PAT" },
789 /* 0x480-0x48b : Not available in model 2. */
790 { 0x0600, "IA32_DS_AREA" },
791 /* 0x0680 - 0x06cf Branch Records Skipped */
792 };
793
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]794 static const msr_entry_t modelf4x_global_msrs[] = {
795 { 0x0000, "IA32_P5_MC_ADDR" },
796 { 0x0001, "IA32_P5_MC_TYPE" },
797 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
798 { 0x0017, "IA32_PLATFORM_ID" },
799 { 0x002a, "MSR_EBC_HARD_POWERON" },
Elyes HAOUASe3e2bb02016-07-26 18:34:14 +0200[diff] [blame]800 { 0x002b, "MSR_EBC_SOFT_POWERON" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]801 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]802// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]803 { 0x019c, "IA32_THERM_STATUS" },
804 { 0x019d, "MSR_THERM2_CTL" },
805 { 0x01a0, "IA32_MISC_ENABLE" },
806 { 0x01a1, "MSR_PLATFORM_BRV" },
807 { 0x0200, "IA32_MTRR_PHYSBASE0" },
808 { 0x0201, "IA32_MTRR_PHYSMASK0" },
809 { 0x0202, "IA32_MTRR_PHYSBASE1" },
810 { 0x0203, "IA32_MTRR_PHYSMASK1" },
811 { 0x0204, "IA32_MTRR_PHYSBASE2" },
812 { 0x0205, "IA32_MTRR_PHYSMASK2" },
813 { 0x0206, "IA32_MTRR_PHYSBASE3" },
814 { 0x0207, "IA32_MTRR_PHYSMASK3" },
815 { 0x0208, "IA32_MTRR_PHYSBASE4" },
816 { 0x0209, "IA32_MTRR_PHYSMASK4" },
817 { 0x020a, "IA32_MTRR_PHYSBASE5" },
818 { 0x020b, "IA32_MTRR_PHYSMASK5" },
819 { 0x020c, "IA32_MTRR_PHYSBASE6" },
820 { 0x020d, "IA32_MTRR_PHYSMASK6" },
821 { 0x020e, "IA32_MTRR_PHYSBASE7" },
822 { 0x020f, "IA32_MTRR_PHYSMASK7" },
823 { 0x0250, "IA32_MTRR_FIX64K_00000" },
824 { 0x0258, "IA32_MTRR_FIX16K_80000" },
825 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
826 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
827 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
828 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
829 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
830 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
831 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
832 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
833 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
834 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
835 { 0x0300, "MSR_BPU_COUNTER0" },
836 { 0x0301, "MSR_BPU_COUNTER1" },
837 { 0x0302, "MSR_BPU_COUNTER2" },
838 { 0x0303, "MSR_BPU_COUNTER3" },
839 /* Skipped through 0x3ff for now*/
840
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]841 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]842 * set in MCX_STATUS */
843 { 0x400, "IA32_MC0_CTL" },
844 { 0x401, "IA32_MC0_STATUS" },
845 { 0x402, "IA32_MC0_ADDR" },
846 { 0x403, "IA32_MC0_MISC" },
847 { 0x404, "IA32_MC1_CTL" },
848 { 0x405, "IA32_MC1_STATUS" },
849 { 0x406, "IA32_MC1_ADDR" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]850 { 0x407, "IA32_MC1_MISC" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]851 { 0x408, "IA32_MC2_CTL" },
852 { 0x409, "IA32_MC2_STATUS" },
853 { 0x40a, "IA32_MC2_ADDR" },
854 { 0x40b, "IA32_MC2_MISC" },
855 { 0x40c, "IA32_MC3_CTL" },
856 { 0x40d, "IA32_MC3_STATUS" },
857 { 0x40e, "IA32_MC3_ADDR" },
858 { 0x40f, "IA32_MC3_MISC" },
859 { 0x410, "IA32_MC4_CTL" },
860 { 0x411, "IA32_MC4_STATUS" },
861 { 0x412, "IA32_MC4_ADDR" },
862 { 0x413, "IA32_MC4_MISC" },
863 };
864
865 static const msr_entry_t modelf4x_per_core_msrs[] = {
866 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
867 { 0x001b, "IA32_APIC_BASE" },
868 { 0x003a, "IA32_FEATURE_CONTROL" },
869 { 0x008b, "IA32_BIOS_SIGN_ID" },
870 { 0x009b, "IA32_SMM_MONITOR_CTL" },
871 { 0x00fe, "IA32_MTRRCAP" },
872 { 0x0174, "IA32_SYSENTER_CS" },
873 { 0x0175, "IA32_SYSENTER_ESP" },
874 { 0x0176, "IA32_SYSENTER_EIP" },
875 { 0x0179, "IA32_MCG_CAP" },
876 { 0x017a, "IA32_MCG_STATUS" },
877 { 0x0180, "MSR_MCG_RAX" },
878 { 0x0181, "MSR_MCG_RBX" },
879 { 0x0182, "MSR_MCG_RCX" },
880 { 0x0183, "MSR_MCG_RDX" },
881 { 0x0184, "MSR_MCG_RSI" },
882 { 0x0185, "MSR_MCG_RDI" },
883 { 0x0186, "MSR_MCG_RBP" },
884 { 0x0187, "MSR_MCG_RSP" },
885 { 0x0188, "MSR_MCG_RFLAGS" },
886 { 0x0189, "MSR_MCG_RIP" },
887 { 0x018a, "MSR_MCG_MISC" },
888 // 0x18b-f Reserved
889 { 0x0190, "MSR_MCG_R8" },
890 { 0x0191, "MSR_MCG_R9" },
891 { 0x0192, "MSR_MCG_R10" },
892 { 0x0193, "MSR_MCG_R11" },
893 { 0x0194, "MSR_MCG_R12" },
894 { 0x0195, "MSR_MCG_R13" },
895 { 0x0196, "MSR_MCG_R14" },
896 { 0x0197, "MSR_MCG_R15" },
897 { 0x0198, "IA32_PERF_STATUS" },
898 { 0x0199, "IA32_PERF_CTL" },
899 { 0x019a, "IA32_CLOCK_MODULATION" },
900 { 0x019b, "IA32_THERM_INTERRUPT" },
901 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
902 { 0x01d7, "MSR_LER_FROM_LIP" },
903 { 0x01d8, "MSR_LER_TO_LIP" },
904 { 0x01d9, "MSR_DEBUGCTLA" },
905 { 0x01da, "MSR_LASTBRANCH_TOS" },
906 { 0x0277, "IA32_PAT" },
907 /** Virtualization
908 { 0x480, "IA32_VMX_BASIC" },
909 through
910 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
911 Not implemented in my CPU
912 */
913 { 0x0600, "IA32_DS_AREA" },
914 /* 0x0680 - 0x06cf Branch Records Skipped */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]915
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]916 };
917
Elyes HAOUASdfe8d642018-01-31 21:29:00 +0100[diff] [blame]918 /*
919 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual
920 * September 2016
921 */
922 static const msr_entry_t modelf6x_global_msrs[] = {
923 { 0x0000, "IA32_P5_MC_ADDR" },
924 { 0x0001, "IA32_P5_MC_TYPE" },
925 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
926 { 0x0017, "IA32_PLATFORM_ID" },
927 { 0x002a, "MSR_EBC_HARD_POWERON" },
928 { 0x002b, "MSR_EBC_SOFT_POWERON" },
929 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
930// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
931 { 0x019c, "IA32_THERM_STATUS" },
932 { 0x019d, "MSR_THERM2_CTL" },
933 { 0x01a0, "IA32_MISC_ENABLE" },
934 { 0x01a1, "MSR_PLATFORM_BRV" },
935 { 0x0200, "IA32_MTRR_PHYSBASE0" },
936 { 0x0201, "IA32_MTRR_PHYSMASK0" },
937 { 0x0202, "IA32_MTRR_PHYSBASE1" },
938 { 0x0203, "IA32_MTRR_PHYSMASK1" },
939 { 0x0204, "IA32_MTRR_PHYSBASE2" },
940 { 0x0205, "IA32_MTRR_PHYSMASK2" },
941 { 0x0206, "IA32_MTRR_PHYSBASE3" },
942 { 0x0207, "IA32_MTRR_PHYSMASK3" },
943 { 0x0208, "IA32_MTRR_PHYSBASE4" },
944 { 0x0209, "IA32_MTRR_PHYSMASK4" },
945 { 0x020a, "IA32_MTRR_PHYSBASE5" },
946 { 0x020b, "IA32_MTRR_PHYSMASK5" },
947 { 0x020c, "IA32_MTRR_PHYSBASE6" },
948 { 0x020d, "IA32_MTRR_PHYSMASK6" },
949 { 0x020e, "IA32_MTRR_PHYSBASE7" },
950 { 0x020f, "IA32_MTRR_PHYSMASK7" },
951 { 0x0250, "IA32_MTRR_FIX64K_00000" },
952 { 0x0258, "IA32_MTRR_FIX16K_80000" },
953 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
954 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
955 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
956 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
957 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
958 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
959 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
960 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
961 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
962 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
963 { 0x0300, "MSR_BPU_COUNTER0" },
964 { 0x0301, "MSR_BPU_COUNTER1" },
965 { 0x0302, "MSR_BPU_COUNTER2" },
966 { 0x0303, "MSR_BPU_COUNTER3" },
967 { 0x0304, "MSR_MS_COUNTER0" },
968 { 0x0305, "MSR_MS_COUNTER1" },
969 { 0x0306, "MSR_MS_COUNTER2" },
970 { 0x0307, "MSR_MS_COUNTER3" },
971 { 0x0308, "MSR_FLAME_COUNTER0" },
972 { 0x0309, "MSR_FLAME_COUNTER1" },
973 { 0x030a, "MSR_FLAME_COUNTER2" },
974 { 0x030b, "MSR_FLAME_COUNTER3" },
975 { 0x030c, "MSR_IQ_COUNTER0" },
976 { 0x030d, "MSR_IQ_COUNTER1" },
977 { 0x030e, "MSR_IQ_COUNTER2" },
978 { 0x030f, "MSR_IQ_COUNTER3" },
979 { 0x0310, "MSR_IQ_COUNTER4" },
980 { 0x0311, "MSR_IQ_COUNTER5" },
981 { 0x0360, "MSR_BPU_CCCR0" },
982 { 0x0361, "MSR_BPU_CCCR1" },
983 { 0x0362, "MSR_BPU_CCCR2" },
984 { 0x0363, "MSR_BPU_CCCR3" },
985 { 0x0364, "MSR_MS_CCCR0" },
986 { 0x0365, "MSR_MS_CCCR1" },
987 { 0x0366, "MSR_MS_CCCR2" },
988 { 0x0367, "MSR_MS_CCCR3" },
989 { 0x0368, "MSR_FLAME_CCCR0" },
990 { 0x0369, "MSR_FLAME_CCCR1" },
991 { 0x036A, "MSR_FLAME_CCCR2" },
992 { 0x036B, "MSR_FLAME_CCCR3" },
993 { 0x036C, "MSR_IQ_CCCR0" },
994 { 0x036D, "MSR_IQ_CCCR1" },
995 { 0x036E, "MSR_IQ_CCCR2" },
996 { 0x036F, "MSR_IQ_CCCR3" },
997 { 0x0370, "MSR_IQ_CCCR4" },
998 { 0x0371, "MSR_IQ_CCCR5" },
999 { 0x03A0, "MSR_BSU_ESCR0" },
1000 { 0x03A1, "MSR_BSU_ESCR1" },
1001 { 0x03A2, "MSR_FSB_ESCR0" },
1002 { 0x03A3, "MSR_FSB_ESCR1" },
1003 { 0x03A4, "MSR_FIRM_ESCR0" },
1004 { 0x03A5, "MSR_FIRM_ESCR1" },
1005 { 0x03A6, "MSR_FLAME_ESCR0" },
1006 { 0x03A7, "MSR_FLAME_ESCR1" },
1007 { 0x03A8, "MSR_DAC_ESCR0" },
1008 { 0x03A9, "MSR_DAC_ESCR1" },
1009 { 0x03AA, "MSR_MOB_ESCR0" },
1010 { 0x03AB, "MSR_MOB_ESCR1" },
1011 { 0x03AC, "MSR_PMH_ESCR0" },
1012 { 0x03AD, "MSR_PMH_ESCR1" },
1013 { 0x03AE, "MSR_SAAT_ESCR0" },
1014 { 0x03AF, "MSR_SAAT_ESCR1" },
1015 { 0x03B0, "MSR_U2L_ESCR0" },
1016 { 0x03B1, "MSR_U2L_ESCR1" },
1017 { 0x03B2, "MSR_BPU_ESCR0" },
1018 { 0x03B3, "MSR_BPU_ESCR1" },
1019 { 0x03B4, "MSR_IS_ESCR0" },
1020 { 0x03B5, "MSR_IS_ESCR1" },
1021 { 0x03B6, "MSR_ITLB_ESCR0" },
1022 { 0x03B7, "MSR_ITLB_ESCR1" },
1023 { 0x03B8, "MSR_CRU_ESCR0" },
1024 { 0x03B9, "MSR_CRU_ESCR1" },
1025 { 0x03BA, "MSR_IQ_ESCR0" },
1026 { 0x03BB, "MSR_IQ_ESCR1" },
1027 { 0x03BC, "MSR_RAT_ESCR0" },
1028 { 0x03BD, "MSR_RAT_ESCR1" },
1029 { 0x03BE, "MSR_SSU_ESCR0" },
1030 { 0x03C0, "MSR_MS_ESCR0" },
1031 { 0x03C1, "MSR_MS_ESCR1" },
1032 { 0x03C2, "MSR_TBPU_ESCR0" },
1033 { 0x03C3, "MSR_TBPU_ESCR1" },
1034 { 0x03C4, "MSR_TC_ESCR0" },
1035 { 0x03C5, "MSR_TC_ESCR1" },
1036 { 0x03C8, "MSR_IX_ESCR0" },
1037 { 0x03C9, "MSR_IX_ESCR1" },
1038 { 0x03CA, "MSR_ALF_ESCR0" },
1039 { 0x03CB, "MSR_ALF_ESCR1" },
1040 { 0x03CC, "MSR_CRU_ESCR2" },
1041 { 0x03CD, "MSR_CRU_ESCR3" },
1042 { 0x03E0, "MSR_CRU_ESCR4" },
1043 { 0x03E1, "MSR_CRU_ESCR5" },
1044 { 0x03F0, "MSR_TC_PRECISE_EVENT" },
1045 { 0x03F1, "MSR_PEBS_ENABLE" },
1046 { 0x03F2, "MSR_PEBS_MATRIX_VERT" },
1047 { 0x0400, "IA32_MC0_CTL" },
1048 { 0x0401, "IA32_MC0_STATUS" },
1049 { 0x0402, "IA32_MC0_ADDR" },
1050 { 0x0403, "IA32_MC0_MISC" },
1051 { 0x0404, "IA32_MC1_CTL" },
1052 { 0x0405, "IA32_MC1_STATUS" },
1053 { 0x0406, "IA32_MC1_ADDR" },
1054 { 0x0408, "IA32_MC2_CTL" },
1055 { 0x0409, "IA32_MC2_STATUS" },
1056 { 0x040b, "IA32_MC2_MISC" },
1057 { 0x040c, "IA32_MC3_CTL" },
1058 { 0x040d, "IA32_MC3_STATUS" },
1059 { 0x040e, "IA32_MC3_ADDR" },
1060 { 0x040f, "IA32_MC3_MISC" },
1061 };
1062
1063 static const msr_entry_t modelf6x_per_core_msrs[] = {
1064 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1065 { 0x001b, "IA32_APIC_BASE" },
1066 { 0x008b, "IA32_BIOS_SIGN_ID" },
1067 { 0x00fe, "IA32_MTRRCAP" },
1068 { 0x0174, "IA32_SYSENTER_CS" },
1069 { 0x0175, "IA32_SYSENTER_ESP" },
1070 { 0x0176, "IA32_SYSENTER_EIP" },
1071 { 0x0179, "IA32_MCG_CAP" },
1072 { 0x017a, "IA32_MCG_STATUS" },
1073 { 0x0180, "MSR_MCG_RAX" },
1074 { 0x0181, "MSR_MCG_RBX" },
1075 { 0x0182, "MSR_MCG_RCX" },
1076 { 0x0183, "MSR_MCG_RDX" },
1077 { 0x0184, "MSR_MCG_RSI" },
1078 { 0x0185, "MSR_MCG_RDI" },
1079 { 0x0186, "MSR_MCG_RBP" },
1080 { 0x0187, "MSR_MCG_RSP" },
1081 { 0x0188, "MSR_MCG_RFLAGS" },
1082 { 0x0189, "MSR_MCG_RIP" },
1083 { 0x018a, "MSR_MCG_MISC" },
1084 { 0x0190, "MSR_MCG_R8" },
1085 { 0x0191, "MSR_MCG_R9" },
1086 { 0x0192, "MSR_MCG_R10" },
1087 { 0x0193, "MSR_MCG_R11" },
1088 { 0x0194, "MSR_MCG_R12" },
1089 { 0x0195, "MSR_MCG_R13" },
1090 { 0x0196, "MSR_MCG_R14" },
1091 { 0x0197, "MSR_MCG_R15" },
1092 { 0x0198, "IA32_PERF_STATUS" },
1093 { 0x0199, "IA32_PERF_CTL" },
1094 { 0x019a, "IA32_CLOCK_MODULATION" },
1095 { 0x019b, "IA32_THERM_INTERRUPT" },
1096 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1097 { 0x01d7, "MSR_LER_FROM_LIP" },
1098 { 0x01d8, "MSR_LER_TO_LIP" },
1099 { 0x01d9, "MSR_DEBUGCTLA" },
1100 { 0x01da, "MSR_LASTBRANCH_TOS" },
1101 { 0x0277, "IA32_PAT" },
1102 { 0x0600, "IA32_DS_AREA" },
1103 { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
1104 { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
1105 { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
1106 { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
1107 { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
1108 { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
1109 { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
1110 { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
1111 { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
1112 { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
1113 { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
1114 { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
1115 { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
1116 { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
1117 { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
1118 { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
1119 { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
1120 { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
1121 { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
1122 { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
1123 { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
1124 { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
1125 { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
1126 { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
1127 { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
1128 { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
1129 { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
1130 { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
1131 { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
1132 { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
1133 { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
1134 { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
1135 /* Intel Xeon processor 7100 with L3 */
1136// { 0x107CC, "MSR_EMON_L3_CTR_CTL0" },
1137// { 0x107CD, "MSR_EMON_L3_CTR_CTL1" },
1138// { 0x107CE, "MSR_EMON_L3_CTR_CTL2" },
1139// { 0x107CF, "MSR_EMON_L3_CTR_CTL3" },
1140// { 0x107D0, "MSR_EMON_L3_CTR_CTL4" },
1141// { 0x107D1, "MSR_EMON_L3_CTR_CTL5" },
1142// { 0x107D2, "MSR_EMON_L3_CTR_CTL6" },
1143// { 0x107D3, "MSR_EMON_L3_CTR_CTL7" },
1144 };
1145
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]1146 /* Atom N455
1147 *
1148 * This should apply to the following processors:
1149 * 06_1CH
1150 * 06_26H
1151 * 06_27H
1152 * 06_35
1153 * 06_36
1154 */
1155 /*
1156 * All MSRs per
1157 *
1158 * Intel 64 and IA-32 Architectures Software Developer's Manual
1159 * Volume 3C: System Programming Guide, Part 3
1160 * Order Number 326019
1161 * January 2013
1162 *
1163 * Table 35-4, 35-5
1164 *
1165 * For now it has only been tested with 06_1CH.
1166 */
1167 static const msr_entry_t model6_atom_global_msrs[] = {
1168 { 0x0000, "IA32_P5_MC_ADDR" },
1169 { 0x0001, "IA32_P5_MC_TYPE" },
1170 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1171 { 0x0017, "IA32_PLATFORM_ID" },
1172 { 0x002a, "MSR_EBC_HARD_POWERON" },
1173 { 0x00cd, "MSR_FSB_FREQ" },
1174 { 0x00fe, "IA32_MTRRCAP" },
1175 { 0x011e, "MSR_BBL_CR_CTL3" },
1176 { 0x0198, "IA32_PERF_STATUS" },
1177 { 0x019d, "MSR_THERM2_CTL" },
1178 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1179 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1180 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1181 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1182 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1183 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1184 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1185 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1186 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1187 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1188 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1189 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1190 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1191 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1192 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1193 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1194 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1195 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1196 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1197 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1198 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1199 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1200 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1201 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1202 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1203 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1204 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1205 { 0x0345, "IA32_PERF_CAPABILITIES" },
1206 { 0x400, "IA32_MC0_CTL" },
1207 { 0x401, "IA32_MC0_STATUS" },
1208 { 0x402, "IA32_MC0_ADDR" },
1209 { 0x404, "IA32_MC1_CTL" },
1210 { 0x405, "IA32_MC1_STATUS" },
1211 { 0x408, "IA32_MC2_CTL" },
1212 { 0x409, "IA32_MC2_STATUS" },
1213 { 0x40a, "IA32_MC2_ADDR" },
1214 { 0x40c, "IA32_MC3_CTL" },
1215 { 0x40d, "IA32_MC3_STATUS" },
1216 { 0x40e, "IA32_MC3_ADDR" },
1217 { 0x410, "IA32_MC4_CTL" },
1218 { 0x411, "IA32_MC4_STATUS" },
1219 { 0x412, "IA32_MC4_ADDR" },
1220 /*
1221 * Only 06_27C has the following MSRs
1222 */
1223 /*
1224 { 0x03f8, "MSR_PKG_C2_RESIDENCY" },
1225 { 0x03f9, "MSR_PKG_C4_RESIDENCY" },
1226 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1227 */
1228 };
1229
Elyes HAOUAS94501502016-10-19 17:59:10 +0200[diff] [blame]1230 static const msr_entry_t model6_atom_per_core_msrs[] = {
1231 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
1232 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1233 { 0x001b, "IA32_APIC_BASE" },
1234 { 0x003a, "IA32_FEATURE_CONTROL" },
1235 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1236 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1237 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1238 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1239 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1240 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1241 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1242 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1243 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1244 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1245 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1246 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1247 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1248 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1249 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1250 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1251 /* Write register */
1252 /*
1253 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1254 */
1255 { 0x008b, "IA32_BIOS_SIGN_ID" },
1256 { 0x00c1, "IA32_PMC0" },
1257 { 0x00c2, "IA32_PMC1" },
1258 { 0x00e7, "IA32_MPERF" },
1259 { 0x00e8, "IA32_APERF" },
1260 { 0x0174, "IA32_SYSENTER_CS" },
1261 { 0x0175, "IA32_SYSENTER_ESP" },
1262 { 0x0176, "IA32_SYSENTER_EIP" },
1263 { 0x017a, "IA32_MCG_STATUS" },
1264 { 0x0186, "IA32_PERF_EVNTSEL0" },
1265 { 0x0187, "IA32_PERF_EVNTSEL1" },
1266 { 0x0199, "IA32_PERF_CONTROL" },
1267 { 0x019a, "IA32_CLOCK_MODULATION" },
1268 { 0x019b, "IA32_THERM_INTERRUPT" },
1269 { 0x019c, "IA32_THERM_STATUS" },
1270 { 0x01a0, "IA32_MISC_ENABLES" },
1271 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1272 { 0x01d9, "IA32_DEBUGCTL" },
1273 { 0x01dd, "MSR_LER_FROM_LIP" },
1274 { 0x01de, "MSR_LER_TO_LIP" },
1275 { 0x0277, "IA32_PAT" },
1276 { 0x0309, "IA32_FIXED_CTR0" },
1277 { 0x030a, "IA32_FIXED_CTR1" },
1278 { 0x030b, "IA32_FIXED_CTR2" },
1279 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1280 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1281 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1282 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1283 { 0x03f1, "MSR_PEBS_ENABLE" },
1284 { 0x0480, "IA32_VMX_BASIC" },
1285 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1286 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1287 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1288 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1289 { 0x0485, "IA32_VMX_MISC" },
1290 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1291 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1292 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1293 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1294 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1295 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1296 { 0x0600, "IA32_DS_AREA" },
1297 };
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]1298
Vladimir Serbinenkoe4e8e092013-03-31 13:51:37 +0200[diff] [blame]1299 static const msr_entry_t model20650_global_msrs[] = {
1300 { 0x0000, "IA32_P5_MC_ADDR" },
1301 { 0x0001, "IA32_P5_MC_TYPE" },
1302 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1303 { 0x0017, "IA32_PLATFORM_ID" },
1304 { 0x002a, "MSR_EBC_HARD_POWERON" },
1305// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1306 { 0x00ce, "IA32_MSR_PLATFORM_INFO" },
1307 { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
1308 { 0x019c, "IA32_THERM_STATUS" },
1309 { 0x019d, "MSR_THERM2_CTL" },
1310 { 0x01a0, "IA32_MISC_ENABLE" },
1311 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1312 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1313 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1314 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1315 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1316 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1317 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1318 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1319 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1320 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1321 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1322 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1323 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1324 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1325 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1326 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1327 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1328 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1329 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1330 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1331 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1332 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1333 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1334 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1335 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1336 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1337 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1338 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
1339 { 0x0300, "MSR_BPU_COUNTER0" },
1340 { 0x0301, "MSR_BPU_COUNTER1" },
1341 /* Skipped through 0x3ff for now*/
1342
1343 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
1344 * set in MCX_STATUS */
1345 { 0x400, "IA32_MC0_CTL" },
1346 { 0x401, "IA32_MC0_STATUS" },
1347 { 0x402, "IA32_MC0_ADDR" },
1348 { 0x403, "IA32_MC0_MISC" },
1349 { 0x404, "IA32_MC1_CTL" },
1350 { 0x405, "IA32_MC1_STATUS" },
1351 { 0x406, "IA32_MC1_ADDR" },
1352 { 0x407, "IA32_MC1_MISC" },
1353 { 0x408, "IA32_MC2_CTL" },
1354 { 0x409, "IA32_MC2_STATUS" },
1355 { 0x40a, "IA32_MC2_ADDR" },
1356 { 0x40c, "IA32_MC3_CTL" },
1357 { 0x40d, "IA32_MC3_STATUS" },
1358 { 0x40e, "IA32_MC3_ADDR" },
1359 { 0x410, "IA32_MC4_CTL" },
1360 { 0x411, "IA32_MC4_STATUS" },
1361 };
1362
1363 static const msr_entry_t model20650_per_core_msrs[] = {
1364 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1365 { 0x001b, "IA32_APIC_BASE" },
1366 { 0x003a, "IA32_FEATURE_CONTROL" },
1367 { 0x008b, "IA32_BIOS_SIGN_ID" },
1368 { 0x009b, "IA32_SMM_MONITOR_CTL" },
1369 { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
1370 { 0x00fe, "IA32_MTRRCAP" },
1371 { 0x0174, "IA32_SYSENTER_CS" },
1372 { 0x0175, "IA32_SYSENTER_ESP" },
1373 { 0x0176, "IA32_SYSENTER_EIP" },
1374 { 0x0179, "IA32_MCG_CAP" },
1375 { 0x017a, "IA32_MCG_STATUS" },
1376 { 0x0186, "MSR_MCG_RBP" },
1377 { 0x0187, "MSR_MCG_RSP" },
1378 { 0x0188, "MSR_MCG_RFLAGS" },
1379 { 0x0189, "MSR_MCG_RIP" },
1380 { 0x0194, "MSR_MCG_R12" },
1381 { 0x0198, "IA32_PERF_STATUS" },
1382 { 0x0199, "IA32_PERF_CTL" },
1383 { 0x019a, "IA32_CLOCK_MODULATION" },
1384 { 0x019b, "IA32_THERM_INTERRUPT" },
1385 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
1386 { 0x01aa, "IA32_MISC_PWR_MGMT" },
1387 { 0x01d9, "MSR_DEBUGCTLA" },
1388 { 0x01fc, "MSR_POWER_CTL" },
1389 { 0x0277, "IA32_PAT" },
1390 /** Virtualization
1391 { 0x480, "IA32_VMX_BASIC" },
1392 through
1393 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
1394 Not implemented in my CPU
1395 */
1396 { 0x0600, "IA32_DS_AREA" },
1397 /* 0x0680 - 0x06cf Branch Records Skipped */
1398
1399 { 0x3a, "IA32_FEATURE_CONTROL" },
1400 { 0x13c, "MSR_FEATURE_CONFIG" },
1401 { 0x194, "MSR_FLEX_RATIO" },
1402 { 0x1a0, "IA32_MISC_ENABLE" },
1403 { 0x1a2, "MSR_TEMPERATURE_TARGET" },
1404 { 0x199, "IA32_PERF_CTL" },
1405 { 0x19b, "IA32_THERM_INTERRUPT" },
1406 { 0x401, "IA32_MC0_STATUS" },
1407 { 0x2e, "MSR_PIC_MSG_CONTROL" },
1408 { 0xce, "MSR_PLATFORM_INFO" },
1409 { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
1410 { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
1411 { 0x1aa, "MSR_MISC_PWR_MGMT" },
1412 { 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
1413 { 0x1fc, "MSR_POWER_CTL" },
1414 };
1415
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]1416/*
1417 * The following two tables are the Silvermont registers listed in Table 35-6
Martin Roth0cd338e2016-07-29 14:07:30 -0600[diff] [blame]1418 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]1419 * September 2014
1420 * Vol. 3C 35-59
1421 */
1422 static const msr_entry_t silvermont_per_core_msrs[] = {
1423 /*
1424 * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
1425 * These are MSRs marked as "core"
1426 *
1427 */
1428 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1429 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1430 { 0x001b, "IA32_APIC_BASE" },
1431 { 0x0034, "MSR_SMI_COUNT" },
1432 { 0x003a, "IA32_FEATURE_CONTROL" },
1433 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1434 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1435 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1436 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1437 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1438 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1439 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1440 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1441 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1442 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1443 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1444 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1445 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1446 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1447 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1448 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1449 /* Write register
1450 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1451 */
1452 { 0x008b, "IA32_BIOS_SIGN_ID" },
1453 { 0x00c1, "IA32_PMC0" },
1454 { 0x00c2, "IA32_PMC1" },
1455 { 0x00e7, "IA32_MPERF" },
1456 { 0x00e8, "IA32_APERF" },
1457 { 0x00fe, "IA32_MTRRCAP" },
1458 { 0x0174, "IA32_SYSENTER_CS" },
1459 { 0x0175, "IA32_SYSENTER_ESP" },
1460 { 0x0176, "IA32_SYSENTER_EIP" },
1461 { 0x0179, "IA32_MCG_CAP" },
1462 { 0x017a, "IA32_MCG_STATUS" },
1463 { 0x0186, "IA32_PERF_EVNTSEL0" },
1464 { 0x0187, "IA32_PERF_EVNTSEL1" },
1465 { 0x0199, "IA32_PERF_CONTROL" },
1466 { 0x019a, "IA32_CLOCK_MODULATION" },
1467 { 0x019b, "IA32_THERM_INTERRUPT" },
1468 { 0x019c, "IA32_THERM_STATUS" },
1469 { 0x01a0, "IA32_MISC_ENABLES" },
1470 { 0x01b0, "IA32_ENERGY_PERF_BIAS" },
1471 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1472 { 0x01d9, "IA32_DEBUGCTL" },
1473 { 0x01dd, "MSR_LER_FROM_LIP" },
1474 { 0x01de, "MSR_LER_TO_LIP" },
1475 { 0x01f2, "IA32_SMRR_PHYSBASE" },
1476 { 0x01f3, "IA32_SMRR_PHYSMASK" },
1477 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1478 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1479 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1480 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1481 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1482 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1483 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1484 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1485 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1486 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1487 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1488 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1489 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1490 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1491 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1492 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1493 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1494 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1495 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1496 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1497 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1498 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1499 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1500 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1501 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1502 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1503 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1504 { 0x0277, "IA32_PAT" },
1505 { 0x02FF, "IA32_MTRR_DEF_TYPE" },
1506 { 0x0309, "IA32_FIXED_CTR0" },
1507 { 0x030a, "IA32_FIXED_CTR1" },
1508 { 0x030b, "IA32_FIXED_CTR2" },
1509 { 0x0345, "IA32_PERF_CAPABILITIES" },
1510 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1511 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1512 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1513 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1514 { 0x03f1, "MSR_PEBS_ENABLE" },
1515 { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
1516 { 0x40c, "IA32_MC3_CTL" },
1517 { 0x40d, "IA32_MC3_STATUS" },
1518 { 0x40e, "IA32_MC3_ADDR" },
1519 { 0x410, "IA32_MC4_CTL" },
1520 { 0x411, "IA32_MC4_STATUS" },
1521 { 0x412, "IA32_MC4_ADDR" },
1522 { 0x0480, "IA32_VMX_BASIC" },
1523 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1524 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1525 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1526 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1527 { 0x0485, "IA32_VMX_MISC" },
1528 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1529 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1530 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1531 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1532 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1533 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1534 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1535 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1536 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1537 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1538 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1539 { 0x0491, "IA32_VMX_FMFUNC" },
1540 { 0x04c1, "IA32_A_PMC0" },
1541 { 0x04c2, "IA32_A_PMC1" },
1542 { 0x0600, "IA32_DS_AREA" },
1543 { 0x0660, "MSR_CORE_C1_RESIDENCY" },
1544 { 0x06e0, "IA32_TSC_DEADLINE" },
1545 };
1546
1547 static const msr_entry_t silvermont_global_msrs[] = {
1548 /*
1549 * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
1550 * These are MSRs marked as "shared" or "package"
1551 */
1552 { 0x0000, "IA32_P5_MC_ADDR" },
1553 { 0x0001, "IA32_P5_MC_TYPE" },
1554 { 0x0017, "IA32_PLATFORM_ID" },
1555 { 0x002a, "MSR_EBC_HARD_POWERON" },
1556 { 0x00cd, "MSR_FSB_FREQ" },
1557 { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
1558 { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
1559 { 0x011e, "BBL_CR_CTL3" },
1560 { 0x0198, "IA32_PERF_STATUS" },
1561 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1562 { 0x01A6, "MSR_OFFCORE_RSP_0" },
1563 { 0x01A7, "MSR_OFFCORE_RSP_1" },
1564 { 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
1565 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1566 { 0x400, "IA32_MC0_CTL" },
1567 { 0x401, "IA32_MC0_STATUS" },
1568 { 0x402, "IA32_MC0_ADDR" },
1569 { 0x404, "IA32_MC1_CTL" },
1570 { 0x405, "IA32_MC1_STATUS" },
1571 { 0x408, "IA32_MC2_CTL" },
1572 { 0x409, "IA32_MC2_STATUS" },
1573 { 0x40a, "IA32_MC2_ADDR" },
1574 { 0x414, "MSR_MC5_CTL" },
1575 { 0x415, "MSR_MC5_STATUS" },
1576 { 0x416, "MSR_MC5_ADDR" },
1577 };
1578
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1579/*
1580 * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes
1581 * Page 4668
1582 *
1583 * The following two tables are for the Kaby Lake processors
1584 * 06_9EH.
1585 *
1586 */
1587
1588 static const msr_entry_t model96ex_global_msrs[] = {
Maxim Polyakov3e7ff292019-10-08 12:29:00 +0300[diff] [blame]1589 { 0x0017, "IA32_PLATFORM_ID"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1590 { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"},
1591 { 0x00CE, "MSR_PLATFORM_INFO"},
1592 { 0x0198, "IA32_PERF_STATUS"},
1593 { 0x01A2, "MSR_TEMPERATURE_TARGET"},
1594 { 0x01AD, "MSR_TURBO_RATIO_LIMIT"},
1595 { 0x0284, "IA32_MC4_CTL2"},
1596 { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"},
1597 { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"},
1598 { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"},
1599 { 0x0395, "MSR_UNC_PERF_FIXED_CTR"},
1600 { 0x060A, "MSR_PKGC3_IRTL"},
1601 { 0x060B, "MSR_PKGC6_IRTL"},
1602 { 0x060D, "MSR_PKG_C2_RESIDENCY"},
1603 { 0x0610, "MSR_PKG_POWER_LIMIT"},
1604 { 0x0614, "MSR_PKG_POWER_INFO"},
1605 { 0x0620, "MSR_RING_RATIO_LIMIT"},
1606 { 0x0638, "MSR_PP0_POWER_LIMIT"},
1607 { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"},
1608 { 0x0652, "MSR_PKG_HDC_CONFIG"},
1609 { 0x065C, "MSR_PLATFORM_POWER_LIMIT"},
1610 { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"},
1611 { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"},
1612 { 0x0770, "IA32_PM_ENABLE"},
1613 { 0x0DB0, "IA32_PKG_HDC_CTL"},
1614 { 0x03B0, "MSR_UNC_ARB_PERFCTR0"},
1615 { 0x03B1, "MSR_UNC_ARB_PERFCTR1"},
1616 { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"},
1617 { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"},
1618 { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"},
1619 { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"},
1620 { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"},
1621 { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"},
1622 { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"},
1623 { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"},
1624 { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"},
1625 { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"},
1626 { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"},
1627 { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"},
1628 { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"},
1629 { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"},
1630 { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"},
1631 { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"},
1632 { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"},
1633 { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"},
1634 { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"},
1635 { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"},
1636 };
1637
1638 static const msr_entry_t model96ex_per_core_msrs[] = {
1639 /* Per core MSRs for Sandy Bridge and above */
1640 { 0x0000, "IA32_P5_MC_ADDR"},
1641 { 0x0001, "IA32_P5_MC_TYPE"},
1642 { 0x0006, "IA32_MONITOR_FILTER_SIZE"},
1643 { 0x0010, "IA32_TIME_STAMP_COUNTER"},
1644 { 0x001B, "IA32_APIC_BASE"},
1645 { 0x0034, "MSR_SMI_COUNT"},
1646 { 0x003A, "IA32_FEATURE_CONTROL"},
1647 { 0x008B, "IA32_BIOS_SIGN_ID"},
1648 { 0x00C1, "IA32_PMC0" },
1649 { 0x00C2, "IA32_PMC1" },
1650 { 0x00C3, "IA32_PMC2" },
1651 { 0x00C4, "IA32_PMC3" },
1652 { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" },
1653 { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"},
1654 { 0x00E7, "IA32_MPERF"},
1655 { 0x00E8, "IA32_APERF"},
1656 { 0x00FE, "IA32_MTRRCAP"},
1657 { 0x013C, "MSR_FEATURE_CONFIG"},
1658 { 0x0174, "IA32_SYSENTER_CS"},
1659 { 0x0175, "IA32_SYSENTER_ESP"},
1660 { 0x0176, "IA32_SYSENTER_EIP"},
1661 { 0x0179, "IA32_MCG_CAP"},
1662 { 0x017A, "IA32_MCG_STATUS"},
1663 { 0x0186, "IA32_PERFEVTSEL0"},
1664 { 0x0187, "IA32_PERFEVTSEL1"},
1665 { 0x0188, "IA32_PERFEVTSEL2"},
1666 { 0x0189, "IA32_PERFEVTSEL3"},
1667 { 0x0199, "IA32_PERF_CTL"},
1668 { 0x019A, "IA32_CLOCK_MODULATION"},
1669 { 0x019B, "IA32_THERM_INTERRUPT"},
1670 { 0x019C, "IA32_THERM_STATUS"},
1671 { 0x01A0, "IA32_MISC_ENABLE"},
1672 { 0x01A4, "IA32_MISC_FEATURE_CONTROL"},
1673 { 0x01A6, "MSR_OFFCORE_RSP_0"},
1674 { 0x01A7, "MSR_OFFCORE_RSP_1"},
1675 { 0x01C8, "MSR_LBR_SELECT"},
1676 { 0x01C9, "MSR_LASTBRANCH_TOS"},
1677 { 0x01D9, "IA32_DEBUGCTL"},
1678 { 0x01DD, "MSR_LER_FROM_LIP"},
1679 { 0x01DE, "MSR_LER_TO_LIP"},
1680 { 0x01F2, "IA32_SMRR_PHYSBASE"},
1681 { 0x01F3, "IA32_SMRR_PHYSMASK"},
1682 { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
1683 { 0x01F5, "MSR_PRMRR_PHYS_MASK"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1684 { 0x01FB, "MSR_PRMRR_VALID_CONFIG"},
1685 { 0x01FC, "MSR_POWER_CTL"},
1686 { 0x0200, "IA32_MTRR_PHYSBASE0"},
1687 { 0x0201, "IA32_MTRR_PHYSBASE0"},
1688 { 0x0202, "IA32_MTRR_PHYSBASE1"},
1689 { 0x0203, "IA32_MTRR_PHYSBASE1"},
1690 { 0x0204, "IA32_MTRR_PHYSBASE2"},
1691 { 0x0205, "IA32_MTRR_PHYSBASE2"},
1692 { 0x0206, "IA32_MTRR_PHYSBASE3"},
1693 { 0x0207, "IA32_MTRR_PHYSBASE3"},
1694 { 0x0208, "IA32_MTRR_PHYSBASE4"},
1695 { 0x0209, "IA32_MTRR_PHYSBASE4"},
1696 { 0x020A, "IA32_MTRR_PHYSBASE5"},
1697 { 0x020B, "IA32_MTRR_PHYSBASE5"},
1698 { 0x020C, "IA32_MTRR_PHYSBASE6"},
1699 { 0x020D, "IA32_MTRR_PHYSBASE6"},
1700 { 0x020E, "IA32_MTRR_PHYSBASE7"},
1701 { 0x020F, "IA32_MTRR_PHYSBASE7"},
1702 { 0x0210, "IA32_MTRR_PHYSBASE8"},
1703 { 0x0211, "IA32_MTRR_PHYSBASE8"},
1704 { 0x0212, "IA32_MTRR_PHYSBASE9"},
1705 { 0x0213, "IA32_MTRR_PHYSBASE9"},
1706 { 0x0250, "IA32_MTRR_FIX64K_00000"},
1707 { 0x0258, "IA32_MTRR_FIX16K_80000"},
1708 { 0x0259, "IA32_MTRR_FIX16K_A0000"},
1709 { 0x0268, "IA32_MTRR_FIX4K_C0000"},
1710 { 0x0269, "IA32_MTRR_FIX4K_C8000"},
1711 { 0x026A, "IA32_MTRR_FIX4K_D0000"},
1712 { 0x026B, "IA32_MTRR_FIX4K_D8000"},
1713 { 0x026C, "IA32_MTRR_FIX4K_E0000"},
1714 { 0x026D, "IA32_MTRR_FIX4K_E8000"},
1715 { 0x026E, "IA32_MTRR_FIX4K_F0000"},
1716 { 0x026F, "IA32_MTRR_FIX4K_F8000"},
1717 { 0x0277, "IA32_PAT"},
1718 { 0x0280, "IA32_MC0_CTL2"},
1719 { 0x0281, "IA32_MC1_CTL2"},
1720 { 0x0282, "IA32_MC2_CTL2"},
1721 { 0x0283, "IA32_MC3_CTL2"},
1722 { 0x02FF, "IA32_MTRR_DEF_TYPE"},
1723 { 0x0309, "IA32_FIXED_CTR0"},
1724 { 0x030A, "IA32_FIXED_CTR1"},
1725 { 0x030B, "IA32_FIXED_CTR2"},
1726 { 0x0345, "IA32_PERF_CAPABILITIES"},
1727 { 0x038D, "IA32_FIXED_CTR_CTRL"},
1728 { 0x038E, "IA32_PERF_GLOBAL_STATUS"},
1729 { 0x038F, "IA32_PERF_GLOBAL_CTRL"},
1730 { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"},
1731 { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"},
1732 { 0x03F1, "MSR_PEBS_ENABLE"},
1733 { 0x03F6, "MSR_PEBS_LD_LAT"},
1734 { 0x03F7, "MSR_PEBS_FRONTEND"},
1735 { 0x03FC, "MSR_CORE_C3_RESIDENCY"},
1736 { 0x03FD, "MSR_CORE_C6_RESIDENCY"},
1737 { 0x03FE, "MSR_CORE_C7_RESIDENCY"},
1738 { 0x0400, "IA32_MC0_CTL" },
1739 { 0x0401, "IA32_MC0_STATUS" },
1740 { 0x0402, "IA32_MC0_ADDR" },
1741 { 0x0403, "IA32_MC0_MISC" },
1742 { 0x0404, "IA32_MC1_CTL" },
1743 { 0x0405, "IA32_MC1_STATUS" },
1744 { 0x0406, "IA32_MC1_ADDR" },
1745 { 0x0407, "IA32_MC1_MISC" },
1746 { 0x0408, "IA32_MC2_CTL" },
1747 { 0x0409, "IA32_MC2_STATUS" },
1748 { 0x040a, "IA32_MC2_ADDR" },
1749 { 0x040c, "IA32_MC3_CTL" },
1750 { 0x040d, "IA32_MC3_STATUS" },
1751 { 0x040e, "IA32_MC3_ADDR" },
1752 { 0x0410, "IA32_MC4_CTL" },
1753 { 0x0411, "IA32_MC4_STATUS" },
1754 { 0x0480, "IA32_VMX_BASIC" },
1755 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1756 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1757 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1758 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1759 { 0x0485, "IA32_VMX_MISC" },
1760 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1761 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1762 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1763 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1764 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1765 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1766 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1767 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1768 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1769 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1770 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1771 { 0x04C1, "IA32_A_PMC0"},
1772 { 0x04C2, "IA32_A_PMC1"},
1773 { 0x04C3, "IA32_A_PMC2"},
1774 { 0x04C4, "IA32_A_PMC3"},
1775 { 0x0500, "IA32_SGX_SVN_STATUS"},
1776 { 0x0560, "IA32_RTIT_OUTPUT_BASE"},
1777 { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"},
1778 { 0x0570, "IA32_RTIT_CTL"},
1779 { 0x0571, "IA32_RTIT_STATUS"},
1780 { 0x0572, "IA32_RTIT_CR3_MATCH"},
1781 { 0x0580, "IA32_RTIT_ADDR0_A"},
1782 { 0x0581, "IA32_RTIT_ADDR0_B"},
1783 { 0x0582, "IA32_RTIT_ADDR1_A"},
1784 { 0x0583, "IA32_RTIT_ADDR1_B"},
1785 { 0x0600, "IA32_DS_AREA" },
1786 { 0x064E, "MSR_PPERF"},
1787 { 0x0653, "MSR_CORE_HDC_RESIDENCY"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1788 { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
1789 { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
1790 { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
1791 { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
1792 { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
1793 { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
1794 { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
1795 { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
1796 { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
1797 { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
1798 { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" },
1799 { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" },
1800 { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" },
1801 { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" },
1802 { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" },
1803 { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" },
Maxim Polyakov9ebf5312019-10-09 11:16:07 +0300[diff] [blame]1804 { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" },
1805 { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" },
1806 { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" },
1807 { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" },
1808 { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" },
1809 { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" },
1810 { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" },
1811 { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" },
1812 { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" },
1813 { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" },
1814 { 0x06da, "MSR_LASTBRANCH_26_TO_IP" },
1815 { 0x06db, "MSR_LASTBRANCH_27_TO_IP" },
1816 { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" },
1817 { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" },
1818 { 0x06de, "MSR_LASTBRANCH_30_TO_IP" },
1819 { 0x06df, "MSR_LASTBRANCH_31_TO_IP" },
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1820 { 0x06E0, "IA32_TSC_DEADLINE"},
1821 { 0x0771, "IA32_HWP_CAPABILITIES"},
1822 { 0x0773, "IA32_HWP_INTERRUPT"},
1823 { 0x0774, "IA32_HWP_REQUEST"},
1824 { 0x0777, "IA32_HWP_STATUS"},
1825 { 0x0D90, "IA32_BNDCFGS"},
1826 { 0x0DA0, "IA32_XSS"},
1827 { 0x0DB1, "IA32_PM_CTL1"},
1828 { 0x0DB2, "IA32_THREAD_STALL"},
1829 { 0x0DC0, "IA32_LBR_INFO_0"},
1830 { 0x0DC1, "IA32_LBR_INFO_1"},
1831 { 0x0DC2, "IA32_LBR_INFO_2"},
1832 { 0x0DC3, "IA32_LBR_INFO_3"},
1833 { 0x0DC4, "IA32_LBR_INFO_4"},
1834 { 0x0DC5, "IA32_LBR_INFO_5"},
1835 { 0x0DC6, "IA32_LBR_INFO_6"},
1836 { 0x0DC7, "IA32_LBR_INFO_7"},
1837 { 0x0DC8, "IA32_LBR_INFO_8"},
1838 { 0x0DC9, "IA32_LBR_INFO_9"},
1839 { 0x0DCA, "IA32_LBR_INFO_10"},
1840 { 0x0DCB, "IA32_LBR_INFO_11"},
1841 { 0x0DCC, "IA32_LBR_INFO_12"},
1842 { 0x0DCD, "IA32_LBR_INFO_13"},
1843 { 0x0DCE, "IA32_LBR_INFO_14"},
1844 { 0x0DCF, "IA32_LBR_INFO_15"},
1845 { 0x0DD0, "IA32_LBR_INFO_16"},
1846 { 0x0DD1, "IA32_LBR_INFO_17"},
1847 { 0x0DD2, "IA32_LBR_INFO_18"},
1848 { 0x0DD3, "IA32_LBR_INFO_19"},
1849 { 0x0DD4, "IA32_LBR_INFO_20"},
1850 { 0x0DD5, "IA32_LBR_INFO_21"},
1851 { 0x0DD6, "IA32_LBR_INFO_22"},
1852 { 0x0DD7, "IA32_LBR_INFO_23"},
1853 { 0x0DD8, "IA32_LBR_INFO_24"},
1854 { 0x0DD9, "IA32_LBR_INFO_25"},
1855 { 0x0DDA, "IA32_LBR_INFO_26"},
1856 { 0x0DDB, "IA32_LBR_INFO_27"},
1857 { 0x0DDC, "IA32_LBR_INFO_28"},
1858 { 0x0DDD, "IA32_LBR_INFO_29"},
1859 { 0x0DDE, "IA32_LBR_INFO_30"},
1860 { 0x0DDF, "IA32_LBR_INFO_31"},
1861 };
1862
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]1863/*
1864 * Intel® 64 and IA-32 Architecture Software Developer’s Manual
1865 * Volume 4: Model-Specific Registers
1866 * Order Number: 335592-070US
1867 * page 2-265 ... 2-286
1868 * page 2-297 ... 2-308
1869 *
1870 * The following two tables are for the Intel(R) Xeon(R) Processor Scalable
1871 * Family based on Skylake microarchitecture, 2nd generation Intel(R) Xeon(R)
1872 * Processor Scalable Family based on Cascade Lake product, and future Cooper
1873 * Lake product
1874 * family 6 model 85 (06_55h)
1875 */
1876 static const msr_entry_t model565x_global_msrs[] = {
1877 { 0x004e, "MSR_PPIN_CTL" },
1878 { 0x004f, "MSR_PPIN" },
1879 { 0x00ce, "MSR_PLATFORM_INFO" },
1880 { 0x0198, "IA32_PERF_STATUS" },
1881 { 0x019c, "IA32_THERM_STATUS" },
1882 { 0x01a2, "MSR_TEMPERATURE_TARGET" },
1883 { 0x01ad, "MSR_TURBO_RATIO_LIMIT" },
1884 { 0x01ae, "MSR_TURBO_RATIO_LIMIT_CORES" },
1885 { 0x0284, "IA32_MC4_CTL2" },
1886 { 0x0285, "IA32_MC5_CTL2" },
1887 { 0x0286, "IA32_MC6_CTL2" },
1888 { 0x0287, "IA32_MC7_CTL2" },
1889 { 0x0288, "IA32_MC8_CTL2" },
1890 { 0x0289, "IA32_MC9_CTL2" },
1891 { 0x028a, "IA32_MC10_CTL2" },
1892 { 0x028b, "IA32_MC11_CTL2" },
1893 { 0x028c, "IA32_MC12_CTL2" },
1894 { 0x028d, "IA32_MC13_CTL2" },
1895 { 0x028e, "IA32_MC14_CTL2" },
1896 { 0x028f, "IA32_MC15_CTL2" },
1897 { 0x0290, "IA32_MC16_CTL2" },
1898 { 0x0291, "IA32_MC17_CTL2" },
1899 { 0x0292, "IA32_MC18_CTL2" },
1900 { 0x0293, "IA32_MC19_CTL2" },
1901 { 0x0300, "MSR_SGXOWNEREPOCH0" },
1902 { 0x0301, "MSR_SGXOWNEREPOCH1" },
1903 { 0x0410, "IA32_MC4_CTL" },
1904 { 0x0411, "IA32_MC4_STATUS" },
1905 { 0x0412, "IA32_MC4_ADDR" },
1906 { 0x0413, "IA32_MC4_MISC" },
1907 { 0x0414, "IA32_MC5_CTL" },
1908 { 0x0415, "IA32_MC5_STATUS" },
1909 { 0x0416, "IA32_MC5_ADDR" },
1910 { 0x0417, "IA32_MC5_MISC" },
1911 { 0x0418, "IA32_MC6_CTL" },
1912 { 0x0419, "IA32_MC6_STATUS" },
1913 { 0x041a, "IA32_MC6_ADDR" },
1914 { 0x041b, "IA32_MC6_MISC" },
1915 { 0x041c, "IA32_MC7_CTL" },
1916 { 0x041d, "IA32_MC7_STATUS" },
1917 { 0x041e, "IA32_MC7_ADDR" },
1918 { 0x041f, "IA32_MC7_MISC" },
1919 { 0x0420, "IA32_MC8_CTL" },
1920 { 0x0421, "IA32_MC8_STATUS" },
1921 { 0x0422, "IA32_MC8_ADDR" },
1922 { 0x0423, "IA32_MC8_MISC" },
1923 { 0x0424, "IA32_MC9_CTL" },
1924 { 0x0425, "IA32_MC9_STATUS" },
1925 { 0x0426, "IA32_MC9_ADDR" },
1926 { 0x0427, "IA32_MC9_MISC" },
1927 { 0x0428, "IA32_MC10_CTL" },
1928 { 0x0429, "IA32_MC10_STATUS" },
1929 { 0x042a, "IA32_MC10_ADDR" },
1930 { 0x042b, "IA32_MC10_MISC" },
1931 { 0x042c, "IA32_MC11_CTL" },
1932 { 0x042d, "IA32_MC11_STATUS" },
1933 { 0x042e, "IA32_MC11_ADDR" },
1934 { 0x042f, "IA32_MC11_MISC" },
1935 { 0x0430, "IA32_MC12_CTL" },
1936 { 0x0431, "IA32_MC12_STATUS" },
1937 { 0x0432, "IA32_MC12_ADDR" },
1938 { 0x0433, "IA32_MC12_MISC" },
1939 { 0x0434, "IA32_MC13_CTL" },
1940 { 0x0435, "IA32_MC13_STATUS" },
1941 { 0x0436, "IA32_MC13_ADDR" },
1942 { 0x0437, "IA32_MC13_MISC" },
1943 { 0x0438, "IA32_MC14_CTL" },
1944 { 0x0439, "IA32_MC14_STATUS" },
1945 { 0x043a, "IA32_MC14_ADDR" },
1946 { 0x043b, "IA32_MC14_MISC" },
1947 { 0x043c, "IA32_MC15_CTL" },
1948 { 0x043d, "IA32_MC15_STATUS" },
1949 { 0x043e, "IA32_MC15_ADDR" },
1950 { 0x043f, "IA32_MC15_MISC" },
1951 { 0x0440, "IA32_MC16_CTL" },
1952 { 0x0441, "IA32_MC16_STATUS" },
1953 { 0x0442, "IA32_MC16_ADDR" },
1954 { 0x0443, "IA32_MC16_MISC" },
1955 { 0x0444, "IA32_MC17_CTL" },
1956 { 0x0445, "IA32_MC17_STATUS" },
1957 { 0x0446, "IA32_MC17_ADDR" },
1958 { 0x0447, "IA32_MC17_MISC" },
1959 { 0x0448, "IA32_MC18_CTL" },
1960 { 0x0449, "IA32_MC18_STATUS" },
1961 { 0x044a, "IA32_MC18_ADDR" },
1962 { 0x044b, "IA32_MC18_MISC" },
1963 { 0x044c, "IA32_MC19_CTL" },
1964 { 0x044b, "IA32_MC19_STATUS" },
1965 { 0x044e, "IA32_MC19_ADDR" },
1966 { 0x044f, "IA32_MC19_MISC" },
1967 { 0x0606, "MSR_RAPL_POWER_UNIT" },
1968 { 0x0618, "MSR_DRAM_POWER_LIMIT" },
1969 { 0x0619, "MSR_DRAM_ENERGY_STATUS" },
1970 { 0x061b, "MSR_DRAM_PERF_STATUS" },
1971 { 0x061c, "MSR_DRAM_POWER_INFO" },
1972 { 0x0620, "MSR_UNCORE_RATIO_LIMIT" },
1973 { 0x0639, "MSR_PP0_ENERGY_STATUS" },
1974 { 0x0638, "MSR_PP0_POWER_LIMIT" },
1975 { 0x064d, "MSR_PLATFORM_ENERGY_COUNTER" },
1976 { 0x064f, "MSR_CORE_PERF_LIMIT_REASONS" },
1977 { 0x0652, "MSR_PKG_HDC_CONFIG" },
1978 { 0x0655, "MSR_PKG_HDC_SHALLOW_RESIDENCY" },
1979 { 0x0656, "MSR_PKG_HDC_DEEP_RESIDENCY" },
1980 { 0x0658, "MSR_WEIGHTED_CORE_C0" },
1981 { 0x0659, "MSR_ANY_CORE_C0" },
1982 { 0x065a, "MSR_ANY_GFXE_C0" },
1983 { 0x065b, "MSR_CORE_GFXE_OVERLAP_C0" },
1984 { 0x065c, "MSR_PLATFORM_POWER_LIMIT" },
1985 { 0x06b0, "MSR_GRAPHICS_PERF_LIMIT_REASONS" },
1986 { 0x06b1, "MSR_RING_PERF_LIMIT_REASONS" },
1987 { 0x0770, "IA32_PM_ENABLE" },
1988 { 0x0db0, "IA32_PKG_HDC_CTL" },
1989 { 0x0c90, "IA32_L3_QOS_MASK_0" },
1990 { 0x0c91, "IA32_L3_QOS_MASK_1" },
1991 { 0x0c92, "IA32_L3_QOS_MASK_2" },
1992 { 0x0c93, "IA32_L3_QOS_MASK_3" },
1993 { 0x0c94, "IA32_L3_QOS_MASK_4" },
1994 { 0x0c95, "IA32_L3_QOS_MASK_5" },
1995 { 0x0c96, "IA32_L3_QOS_MASK_6" },
1996 { 0x0c97, "IA32_L3_QOS_MASK_7" },
1997 { 0x0c98, "IA32_L3_QOS_MASK_8" },
1998 { 0x0c99, "IA32_L3_QOS_MASK_9" },
1999 { 0x0c9a, "IA32_L3_QOS_MASK_10" },
2000 { 0x0c9b, "IA32_L3_QOS_MASK_11" },
2001 { 0x0c9c, "IA32_L3_QOS_MASK_12" },
2002 { 0x0c9d, "IA32_L3_QOS_MASK_13" },
2003 { 0x0c9e, "IA32_L3_QOS_MASK_14" },
2004 { 0x0c9f, "IA32_L3_QOS_MASK_15" },
2005 };
2006
2007 static const msr_entry_t model565x_per_core_msrs[] = {
2008 { 0x0000, "IA32_P5_MC_ADDR" },
2009 { 0x0001, "IA32_P5_MC_TYPE" },
2010 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
2011 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
2012 { 0x0017, "IA32_PLATFORM_ID" },
2013 { 0x001b, "IA32_APIC_BASE" },
2014 { 0x0034, "MSR_SMI_COUNT" },
2015 { 0x003a, "IA32_FEATURE_CONTROL" },
2016 { 0x008b, "IA32_BIOS_SIGN_ID" },
2017 { 0x00c1, "IA32_PMC0" },
2018 { 0x00c2, "IA32_PMC1" },
2019 { 0x00c3, "IA32_PMC2" },
2020 { 0x00c4, "IA32_PMC3" },
2021 { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
2022 { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
2023 { 0x00e7, "IA32_MPERF" },
2024 { 0x00e8, "IA32_APERF" },
2025 { 0x00fe, "IA32_MTRRCAP" },
2026 { 0x013c, "MSR_FEATURE_CONFIG" },
2027 { 0x0174, "IA32_SYSENTER_CS" },
2028 { 0x0175, "IA32_SYSENTER_ESP" },
2029 { 0x0176, "IA32_SYSENTER_EIP" },
2030 { 0x0179, "IA32_MCG_CAP" },
2031 { 0x017a, "IA32_MCG_STATUS" },
2032 { 0x017d, "MSR_SMM_MCA_CAP" },
2033 { 0x0186, "IA32_PERFEVTSEL0" },
2034 { 0x0187, "IA32_PERFEVTSEL1" },
2035 { 0x0188, "IA32_PERFEVTSEL2" },
2036 { 0x0189, "IA32_PERFEVTSEL3" },
2037 { 0x019b, "IA32_THERM_INTERRUPT" },
2038 { 0x0199, "IA32_PERF_CTL" },
2039 { 0x019a, "IA32_CLOCK_MODULATION" },
2040 { 0x01a0, "IA32_MISC_ENABLE" },
2041 { 0x01a4, "IA32_MISC_FEATURE_CONTROL" },
2042 { 0x01a6, "MSR_OFFCORE_RSP_0" },
2043 { 0x01a7, "MSR_OFFCORE_RSP_1" },
2044 { 0x01c8, "MSR_LBR_SELECT" },
2045 { 0x01c9, "MSR_LASTBRANCH_TOS" },
2046 { 0x01d9, "IA32_DEBUGCTL" },
2047 { 0x01dd, "MSR_LER_FROM_LIP" },
2048 { 0x01de, "MSR_LER_TO_LIP" },
2049 { 0x01f2, "IA32_SMRR_PHYSBASE" },
2050 { 0x01f3, "IA32_SMRR_PHYSMASK" },
2051 { 0x01fc, "MSR_POWER_CTL" },
2052 { 0x0200, "IA32_MTRR_PHYSBASE0" },
2053 { 0x0201, "IA32_MTRR_PHYSBASE0" },
2054 { 0x0202, "IA32_MTRR_PHYSBASE1" },
2055 { 0x0203, "IA32_MTRR_PHYSBASE1" },
2056 { 0x0204, "IA32_MTRR_PHYSBASE2" },
2057 { 0x0205, "IA32_MTRR_PHYSBASE2" },
2058 { 0x0206, "IA32_MTRR_PHYSBASE3" },
2059 { 0x0207, "IA32_MTRR_PHYSBASE3" },
2060 { 0x0208, "IA32_MTRR_PHYSBASE4" },
2061 { 0x0209, "IA32_MTRR_PHYSBASE4" },
2062 { 0x020a, "IA32_MTRR_PHYSBASE5" },
2063 { 0x020b, "IA32_MTRR_PHYSBASE5" },
2064 { 0x020c, "IA32_MTRR_PHYSBASE6" },
2065 { 0x020d, "IA32_MTRR_PHYSBASE6" },
2066 { 0x020e, "IA32_MTRR_PHYSBASE7" },
2067 { 0x020f, "IA32_MTRR_PHYSBASE7" },
2068 { 0x0210, "IA32_MTRR_PHYSBASE8" },
2069 { 0x0211, "IA32_MTRR_PHYSBASE8" },
2070 { 0x0212, "IA32_MTRR_PHYSBASE9" },
2071 { 0x0213, "IA32_MTRR_PHYSBASE9" },
2072 { 0x0250, "IA32_MTRR_FIX64K_00000" },
2073 { 0x0258, "IA32_MTRR_FIX16K_80000" },
2074 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
2075 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
2076 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
2077 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
2078 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
2079 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
2080 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
2081 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
2082 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
2083 { 0x0277, "IA32_PAT" },
2084 { 0x0280, "IA32_MC0_CTL2" },
2085 { 0x0281, "IA32_MC1_CTL2" },
2086 { 0x0282, "IA32_MC2_CTL2" },
2087 { 0x0283, "IA32_MC3_CTL2" },
2088 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
2089 { 0x0309, "IA32_FIXED_CTR0" },
2090 { 0x030a, "IA32_FIXED_CTR1" },
2091 { 0x030b, "IA32_FIXED_CTR2" },
2092 { 0x0345, "IA32_PERF_CAPABILITIES" },
2093 { 0x038d, "IA32_FIXED_CTR_CTRL" },
2094 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
2095 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
2096 { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET" },
2097 { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET" },
2098 { 0x0392, "IA32_PERF_GLOBAL_INUSE" },
2099 { 0x03f1, "MSR_PEBS_ENABLE" },
2100 { 0x03f6, "MSR_PEBS_LD_LAT" },
2101 { 0x03f7, "MSR_PEBS_FRONTEND" },
2102 { 0x03fc, "MSR_CORE_C3_RESIDENCY" },
2103 { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
2104 { 0x03fe, "MSR_CORE_C7_RESIDENCY" },
2105 { 0x0400, "IA32_MC0_CTL" },
2106 { 0x0401, "IA32_MC0_STATUS" },
2107 { 0x0402, "IA32_MC0_ADDR" },
2108 { 0x0403, "IA32_MC0_MISC" },
2109 { 0x0404, "IA32_MC1_CTL" },
2110 { 0x0405, "IA32_MC1_STATUS" },
2111 { 0x0406, "IA32_MC1_ADDR" },
2112 { 0x0407, "IA32_MC1_MISC" },
2113 { 0x0408, "IA32_MC2_CTL" },
2114 { 0x0409, "IA32_MC2_STATUS" },
2115 { 0x040a, "IA32_MC2_ADDR" },
2116 { 0x040b, "IA32_MC2_MISC" },
2117 { 0x040c, "IA32_MC3_CTL" },
2118 { 0x040d, "IA32_MC3_STATUS" },
2119 { 0x040e, "IA32_MC3_ADDR" },
2120 { 0x040f, "IA32_MC3_MISC" },
2121 { 0x0480, "IA32_VMX_BASIC" },
2122 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
2123 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
2124 { 0x0483, "IA32_VMX_EXIT_CTLS" },
2125 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
2126 { 0x0485, "IA32_VMX_MISC" },
2127 { 0x0486, "IA32_VMX_CR0_FIXED0" },
2128 { 0x0487, "IA32_VMX_CR0_FIXED1" },
2129 { 0x0488, "IA32_VMX_CR4_FIXED0" },
2130 { 0x0489, "IA32_VMX_CR4_FIXED1" },
2131 { 0x048a, "IA32_VMX_VMCS_ENUM" },
2132 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
2133 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
2134 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
2135 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
2136 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
2137 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
2138 { 0x04c1, "IA32_A_PMC0" },
2139 { 0x04c2, "IA32_A_PMC1" },
2140 { 0x04c3, "IA32_A_PMC2" },
2141 { 0x04c4, "IA32_A_PMC3" },
2142 { 0x04c5, "IA32_A_PMC4" },
2143 { 0x04c6, "IA32_A_PMC5" },
2144 { 0x04c7, "IA32_A_PMC6" },
2145 { 0x04c8, "IA32_A_PMC7" },
2146 { 0x0500, "IA32_SGX_SVN_STATUS" },
2147 { 0x0560, "IA32_RTIT_OUTPUT_BASE" },
2148 { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS" },
2149 { 0x0570, "IA32_RTIT_CTL" },
2150 { 0x0571, "IA32_RTIT_STATUS" },
2151 { 0x0572, "IA32_RTIT_CR3_MATCH" },
2152 { 0x0580, "IA32_RTIT_ADDR0_A" },
2153 { 0x0581, "IA32_RTIT_ADDR0_B" },
2154 { 0x0582, "IA32_RTIT_ADDR1_A" },
2155 { 0x0583, "IA32_RTIT_ADDR1_B" },
2156 { 0x0600, "IA32_DS_AREA" },
2157 { 0x064e, "MSR_PPERF" },
2158 { 0x0653, "MSR_CORE_HDC_RESIDENCY" },
2159 { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
2160 { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
2161 { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
2162 { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
2163 { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
2164 { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
2165 { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
2166 { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
2167 { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
2168 { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
2169 { 0x069a, "MSR_LASTBRANCH_26_FROM_IP" },
2170 { 0x069b, "MSR_LASTBRANCH_27_FROM_IP" },
2171 { 0x069c, "MSR_LASTBRANCH_28_FROM_IP" },
2172 { 0x069d, "MSR_LASTBRANCH_29_FROM_IP" },
2173 { 0x069e, "MSR_LASTBRANCH_30_FROM_IP" },
2174 { 0x069f, "MSR_LASTBRANCH_31_FROM_IP" },
2175 { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" },
2176 { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" },
2177 { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" },
2178 { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" },
2179 { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" },
2180 { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" },
2181 { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" },
2182 { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" },
2183 { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" },
2184 { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" },
2185 { 0x06da, "MSR_LASTBRANCH_26_TO_IP" },
2186 { 0x06db, "MSR_LASTBRANCH_27_TO_IP" },
2187 { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" },
2188 { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" },
2189 { 0x06de, "MSR_LASTBRANCH_30_TO_IP" },
2190 { 0x06df, "MSR_LASTBRANCH_31_TO_IP" },
2191 { 0x06e0, "IA32_TSC_DEADLINE" },
2192 { 0x0771, "IA32_HWP_CAPABILITIES" },
2193 { 0x0773, "IA32_HWP_INTERRUPT" },
2194 { 0x0774, "IA32_HWP_REQUEST" },
2195 { 0x0777, "IA32_HWP_STATUS" },
2196 { 0x0c8d, "IA32_QM_EVTSEL" },
2197 { 0x0c8f, "IA32_PQR_ASSOC" },
2198 { 0x0d90, "IA32_BNDCFGS" },
2199 { 0x0da0, "IA32_XSS" },
2200 { 0x0db1, "IA32_PM_CTL1" },
2201 { 0x0db2, "IA32_THREAD_STALL" },
2202 { 0x0dc0, "MSR_LBR_INFO_0" },
2203 { 0x0dc1, "MSR_LBR_INFO_1" },
2204 { 0x0dc2, "MSR_LBR_INFO_2" },
2205 { 0x0dc3, "MSR_LBR_INFO_3" },
2206 { 0x0dc4, "MSR_LBR_INFO_4" },
2207 { 0x0dc5, "MSR_LBR_INFO_5" },
2208 { 0x0dc6, "MSR_LBR_INFO_6" },
2209 { 0x0dc7, "MSR_LBR_INFO_7" },
2210 { 0x0dc8, "MSR_LBR_INFO_8" },
2211 { 0x0dc9, "MSR_LBR_INFO_9" },
2212 { 0x0dca, "MSR_LBR_INFO_10" },
2213 { 0x0dcb, "MSR_LBR_INFO_11" },
2214 { 0x0dcc, "MSR_LBR_INFO_12" },
2215 { 0x0dcd, "MSR_LBR_INFO_13" },
2216 { 0x0dce, "MSR_LBR_INFO_14" },
2217 { 0x0dcf, "MSR_LBR_INFO_15" },
2218 { 0x0dd0, "MSR_LBR_INFO_16" },
2219 { 0x0dd1, "MSR_LBR_INFO_17" },
2220 { 0x0dd2, "MSR_LBR_INFO_18" },
2221 { 0x0dd3, "MSR_LBR_INFO_19" },
2222 { 0x0dd4, "MSR_LBR_INFO_20" },
2223 { 0x0dd5, "MSR_LBR_INFO_21" },
2224 { 0x0dd6, "MSR_LBR_INFO_22" },
2225 { 0x0dd7, "MSR_LBR_INFO_23" },
2226 { 0x0dd8, "MSR_LBR_INFO_24" },
2227 { 0x0dd9, "MSR_LBR_INFO_25" },
2228 { 0x0ddA, "MSR_LBR_INFO_26" },
2229 { 0x0ddB, "MSR_LBR_INFO_27" },
2230 { 0x0ddc, "MSR_LBR_INFO_28" },
2231 { 0x0ddd, "MSR_LBR_INFO_29" },
2232 { 0x0dde, "MSR_LBR_INFO_30" },
2233 { 0x0ddf, "MSR_LBR_INFO_31" },
2234 };
2235
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2236 typedef struct {
2237 unsigned int model;
2238 const msr_entry_t *global_msrs;
2239 unsigned int num_global_msrs;
2240 const msr_entry_t *per_core_msrs;
2241 unsigned int num_per_core_msrs;
2242 } cpu_t;
2243
2244 cpu_t cpulist[] = {
Tobias Diedrich3645e612010-11-27 14:44:19 +0000[diff] [blame]2245 { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]2246 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2247 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
2248 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]2249 { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]2250 { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
Elyes HAOUASdfe8d642018-01-31 21:29:00 +0100[diff] [blame]2251 { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) },
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]2252 { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
Vladimir Serbinenkoe4e8e092013-03-31 13:51:37 +0200[diff] [blame]2253 { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]2254 { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) },
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]2255 { 0x50650, model565x_global_msrs, ARRAY_SIZE(model565x_global_msrs), model565x_per_core_msrs, ARRAY_SIZE(model565x_per_core_msrs) },
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]2256
2257 { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
2258
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2259 };
2260
2261 cpu_t *cpu = NULL;
2262
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]2263 /* Get CPU family and model, not the stepping
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2264 * (TODO: extended family/model)
2265 */
Stefan Reinauer74cd56982010-06-01 10:04:28 +0000[diff] [blame]2266 id = cpuid(1) & 0xfffff0;
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2267 for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
2268 if(cpulist[i].model == id) {
2269 cpu = &cpulist[i];
2270 break;
2271 }
2272 }
2273
2274 if (!cpu) {
2275 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
2276 return -1;
2277 }
2278
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2279#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2280 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
2281 if (fd_msr < 0) {
2282 perror("Error while opening /dev/cpu/0/msr");
2283 printf("Did you run 'modprobe msr'?\n");
2284 return -1;
2285 }
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2286#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2287
2288 printf("\n===================== SHARED MSRs (All Cores) =====================\n");
2289
2290 for (i = 0; i < cpu->num_global_msrs; i++) {
2291 msr = rdmsr(cpu->global_msrs[i].number);
2292 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
2293 cpu->global_msrs[i].number, msr.hi, msr.lo,
2294 cpu->global_msrs[i].name);
2295 }
2296
2297 close(fd_msr);
2298
Maxim Polyakovd8163ed2019-10-09 18:35:23 +0300[diff] [blame]2299 const unsigned int cores_range_max_limit = get_number_of_cores() - 1;
2300 if (range_end > cores_range_max_limit) {
2301 if (range_end != UINT_MAX)
2302 printf("Warning: the range exceeds the maximum core number %d!\n",
2303 cores_range_max_limit);
2304 range_end = cores_range_max_limit;
2305 }
2306
2307 for (core = range_start; core <= range_end; core++) {
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2308#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2309 char msrfilename[64];
2310 memset(msrfilename, 0, 64);
Paul Menzel5f3754e2013-04-05 00:12:21 +0200[diff] [blame]2311 sprintf(msrfilename, "/dev/cpu/%u/msr", core);
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2312
2313 fd_msr = open(msrfilename, O_RDWR);
2314
2315 /* If the file is not there, we're probably through. No error,
2316 * since we successfully opened /dev/cpu/0/msr before.
2317 */
2318 if (fd_msr < 0)
2319 break;
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2320#endif
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]2321 if (cpu->num_per_core_msrs)
Paul Menzel5f3754e2013-04-05 00:12:21 +0200[diff] [blame]2322 printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core);
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2323
2324 for (i = 0; i < cpu->num_per_core_msrs; i++) {
2325 msr = rdmsr(cpu->per_core_msrs[i].number);
2326 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
2327 cpu->per_core_msrs[i].number, msr.hi, msr.lo,
2328 cpu->per_core_msrs[i].name);
2329 }
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2330#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2331 close(fd_msr);
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2332#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2333 }
2334
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2335#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2336 if (msr_readerror)
2337 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2338#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2339 return 0;
2340}