Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
| 4 | * Copyright (C) 2008 by coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <fcntl.h> |
| 21 | #include <unistd.h> |
| 22 | #include <stdio.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
| 25 | #include <errno.h> |
| 26 | |
| 27 | #include "inteltool.h" |
| 28 | |
| 29 | int fd_msr; |
| 30 | |
| 31 | unsigned int cpuid(unsigned int op) |
| 32 | { |
| 33 | unsigned int ret; |
| 34 | unsigned int dummy2, dummy3, dummy4; |
| 35 | asm volatile ( |
| 36 | "cpuid" |
| 37 | : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) |
| 38 | : "a" (op) |
| 39 | ); |
| 40 | return ret; |
| 41 | } |
| 42 | |
| 43 | int msr_readerror = 0; |
| 44 | |
| 45 | msr_t rdmsr(int addr) |
| 46 | { |
| 47 | uint8_t buf[8]; |
| 48 | msr_t msr = { 0xffffffff, 0xffffffff }; |
| 49 | |
| 50 | if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { |
| 51 | perror("Could not lseek() to MSR"); |
| 52 | close(fd_msr); |
| 53 | exit(1); |
| 54 | } |
| 55 | |
| 56 | if (read(fd_msr, buf, 8) == 8) { |
| 57 | msr.lo = *(uint32_t *)buf; |
| 58 | msr.hi = *(uint32_t *)(buf + 4); |
| 59 | |
| 60 | return msr; |
| 61 | } |
| 62 | |
| 63 | if (errno == 5) { |
| 64 | printf(" (*)"); // Not all bits of the MSR could be read |
| 65 | msr_readerror = 1; |
| 66 | } else { |
| 67 | // A severe error. |
| 68 | perror("Could not read() MSR"); |
| 69 | close(fd_msr); |
| 70 | exit(1); |
| 71 | } |
| 72 | |
| 73 | return msr; |
| 74 | } |
| 75 | |
| 76 | int print_intel_core_msrs(void) |
| 77 | { |
| 78 | unsigned int i, core, id; |
| 79 | msr_t msr; |
| 80 | |
| 81 | #define IA32_PLATFORM_ID 0x0017 |
| 82 | #define EBL_CR_POWERON 0x002a |
| 83 | #define FSB_CLK_STS 0x00cd |
| 84 | #define IA32_TIME_STAMP_COUNTER 0x0010 |
| 85 | #define IA32_APIC_BASE 0x001b |
| 86 | |
| 87 | typedef struct { |
| 88 | int number; |
| 89 | char *name; |
| 90 | } msr_entry_t; |
| 91 | |
| 92 | static const msr_entry_t model6ex_global_msrs[] = { |
| 93 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 94 | { 0x002a, "EBL_CR_POWERON" }, |
| 95 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 96 | { 0x00ce, "FSB_CLOCK_VCC" }, |
| 97 | { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, |
| 98 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 99 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 100 | { 0x00ee, "EXT_CONFIG" }, |
| 101 | { 0x011e, "BBL_CR_CTL3" }, |
| 102 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 103 | { 0x0198, "IA32_PERF_STATUS" }, |
| 104 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 105 | { 0x01aa, "PIC_SENS_CFG" }, |
| 106 | { 0x0400, "IA32_MC0_CTL" }, |
| 107 | { 0x0401, "IA32_MC0_STATUS" }, |
| 108 | { 0x0402, "IA32_MC0_ADDR" }, |
| 109 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 110 | { 0x040c, "IA32_MC4_CTL" }, |
| 111 | { 0x040d, "IA32_MC4_STATUS" }, |
| 112 | { 0x040e, "IA32_MC4_ADDR" }, |
| 113 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 114 | }; |
| 115 | |
| 116 | static const msr_entry_t model6ex_per_core_msrs[] = { |
| 117 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 118 | { 0x001b, "IA32_APIC_BASE" }, |
| 119 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 120 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 121 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 122 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 123 | { 0x00e7, "IA32_MPERF" }, |
| 124 | { 0x00e8, "IA32_APERF" }, |
| 125 | { 0x00fe, "IA32_MTRRCAP" }, |
| 126 | { 0x015f, "DTS_CAL_CTRL" }, |
| 127 | { 0x0179, "IA32_MCG_CAP" }, |
| 128 | { 0x017a, "IA32_MCG_STATUS" }, |
| 129 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 130 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 131 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 132 | { 0x019c, "IA32_THERM_STATUS" }, |
| 133 | { 0x019d, "GV_THERM" }, |
| 134 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 135 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 136 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 137 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 138 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 139 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 140 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 141 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 142 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 143 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 144 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 145 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 146 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 147 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 148 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 149 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 150 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 151 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 152 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 153 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 154 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 155 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 156 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 157 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 158 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 159 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 160 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 161 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 162 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 163 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 164 | }; |
| 165 | |
| 166 | static const msr_entry_t model6fx_global_msrs[] = { |
| 167 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 168 | { 0x002a, "EBL_CR_POWERON" }, |
| 169 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 170 | { 0x00a8, "EMTTM_CR_TABLE0" }, |
| 171 | { 0x00a9, "EMTTM_CR_TABLE1" }, |
| 172 | { 0x00aa, "EMTTM_CR_TABLE2" }, |
| 173 | { 0x00ab, "EMTTM_CR_TABLE3" }, |
| 174 | { 0x00ac, "EMTTM_CR_TABLE4" }, |
| 175 | { 0x00ad, "EMTTM_CR_TABLE5" }, |
| 176 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 177 | { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, |
| 178 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 179 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 180 | { 0x00ee, "EXT_CONFIG" }, |
| 181 | { 0x011e, "BBL_CR_CTL3" }, |
| 182 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 183 | { 0x0198, "IA32_PERF_STATUS" }, |
| 184 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 185 | { 0x01aa, "PIC_SENS_CFG" }, |
| 186 | { 0x0400, "IA32_MC0_CTL" }, |
| 187 | { 0x0401, "IA32_MC0_STATUS" }, |
| 188 | { 0x0402, "IA32_MC0_ADDR" }, |
| 189 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 190 | { 0x040c, "IA32_MC4_CTL" }, |
| 191 | { 0x040d, "IA32_MC4_STATUS" }, |
| 192 | { 0x040e, "IA32_MC4_ADDR" }, |
| 193 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 194 | }; |
| 195 | |
| 196 | static const msr_entry_t model6fx_per_core_msrs[] = { |
| 197 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 198 | { 0x001b, "IA32_APIC_BASE" }, |
| 199 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 200 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 201 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 202 | { 0x00e1, "SMM_CST_MISC_INFO" }, |
| 203 | { 0x00e7, "IA32_MPERF" }, |
| 204 | { 0x00e8, "IA32_APERF" }, |
| 205 | { 0x00fe, "IA32_MTRRCAP" }, |
| 206 | { 0x0179, "IA32_MCG_CAP" }, |
| 207 | { 0x017a, "IA32_MCG_STATUS" }, |
| 208 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 209 | { 0x019a, "IA32_THERM_CTL" }, |
| 210 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 211 | { 0x019c, "IA32_THERM_STATUS" }, |
| 212 | { 0x019d, "MSR_THERM2_CTL" }, |
| 213 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 214 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 215 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 216 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 217 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 218 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 219 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 220 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 221 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 222 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 223 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 224 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 225 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 226 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 227 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 228 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 229 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 230 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 231 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 232 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 233 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 234 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 235 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 236 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 237 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 238 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 239 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 240 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 241 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 242 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 243 | }; |
| 244 | |
| 245 | typedef struct { |
| 246 | unsigned int model; |
| 247 | const msr_entry_t *global_msrs; |
| 248 | unsigned int num_global_msrs; |
| 249 | const msr_entry_t *per_core_msrs; |
| 250 | unsigned int num_per_core_msrs; |
| 251 | } cpu_t; |
| 252 | |
| 253 | cpu_t cpulist[] = { |
| 254 | { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, |
| 255 | { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, |
| 256 | }; |
| 257 | |
| 258 | cpu_t *cpu = NULL; |
| 259 | |
| 260 | /* Get CPU family and model, not the stepping |
| 261 | * (TODO: extended family/model) |
| 262 | */ |
| 263 | id = cpuid(1) & 0xff0; |
| 264 | for (i = 0; i < ARRAY_SIZE(cpulist); i++) { |
| 265 | if(cpulist[i].model == id) { |
| 266 | cpu = &cpulist[i]; |
| 267 | break; |
| 268 | } |
| 269 | } |
| 270 | |
| 271 | if (!cpu) { |
| 272 | printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); |
| 273 | return -1; |
| 274 | } |
| 275 | |
| 276 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
| 277 | if (fd_msr < 0) { |
| 278 | perror("Error while opening /dev/cpu/0/msr"); |
| 279 | printf("Did you run 'modprobe msr'?\n"); |
| 280 | return -1; |
| 281 | } |
| 282 | |
| 283 | printf("\n===================== SHARED MSRs (All Cores) =====================\n"); |
| 284 | |
| 285 | for (i = 0; i < cpu->num_global_msrs; i++) { |
| 286 | msr = rdmsr(cpu->global_msrs[i].number); |
| 287 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 288 | cpu->global_msrs[i].number, msr.hi, msr.lo, |
| 289 | cpu->global_msrs[i].name); |
| 290 | } |
| 291 | |
| 292 | close(fd_msr); |
| 293 | |
| 294 | for (core = 0; core < 8; core++) { |
| 295 | char msrfilename[64]; |
| 296 | memset(msrfilename, 0, 64); |
| 297 | sprintf(msrfilename, "/dev/cpu/%d/msr", core); |
| 298 | |
| 299 | fd_msr = open(msrfilename, O_RDWR); |
| 300 | |
| 301 | /* If the file is not there, we're probably through. No error, |
| 302 | * since we successfully opened /dev/cpu/0/msr before. |
| 303 | */ |
| 304 | if (fd_msr < 0) |
| 305 | break; |
| 306 | |
| 307 | printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); |
| 308 | |
| 309 | for (i = 0; i < cpu->num_per_core_msrs; i++) { |
| 310 | msr = rdmsr(cpu->per_core_msrs[i].number); |
| 311 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 312 | cpu->per_core_msrs[i].number, msr.hi, msr.lo, |
| 313 | cpu->per_core_msrs[i].name); |
| 314 | } |
| 315 | |
| 316 | close(fd_msr); |
| 317 | } |
| 318 | |
| 319 | if (msr_readerror) |
| 320 | printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | |