util/inteltool: Use tabs for indents
Change-Id: I9d27c276053c51021166f4b22d150060e415d08f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17025
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 9bdc1eb..afafc63 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -815,74 +815,74 @@
*/
};
- static const msr_entry_t model6_atom_per_core_msrs[] = {
- { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
- { 0x0010, "IA32_TIME_STAMP_COUNTER" },
- { 0x001b, "IA32_APIC_BASE" },
- { 0x003a, "IA32_FEATURE_CONTROL" },
- { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
- { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
- { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
- { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
- { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
- { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
- { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
- { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
- { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
- { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
- { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
- { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
- { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
- { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
- { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
- { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
- /* Write register */
- /*
- { 0x0079, "IA32_BIOS_UPDT_TRIG" },
- */
- { 0x008b, "IA32_BIOS_SIGN_ID" },
- { 0x00c1, "IA32_PMC0" },
- { 0x00c2, "IA32_PMC1" },
- { 0x00e7, "IA32_MPERF" },
- { 0x00e8, "IA32_APERF" },
- { 0x0174, "IA32_SYSENTER_CS" },
- { 0x0175, "IA32_SYSENTER_ESP" },
- { 0x0176, "IA32_SYSENTER_EIP" },
- { 0x017a, "IA32_MCG_STATUS" },
- { 0x0186, "IA32_PERF_EVNTSEL0" },
- { 0x0187, "IA32_PERF_EVNTSEL1" },
- { 0x0199, "IA32_PERF_CONTROL" },
- { 0x019a, "IA32_CLOCK_MODULATION" },
- { 0x019b, "IA32_THERM_INTERRUPT" },
- { 0x019c, "IA32_THERM_STATUS" },
- { 0x01a0, "IA32_MISC_ENABLES" },
- { 0x01c9, "MSR_LASTBRANCH_TOS" },
- { 0x01d9, "IA32_DEBUGCTL" },
- { 0x01dd, "MSR_LER_FROM_LIP" },
- { 0x01de, "MSR_LER_TO_LIP" },
- { 0x0277, "IA32_PAT" },
- { 0x0309, "IA32_FIXED_CTR0" },
- { 0x030a, "IA32_FIXED_CTR1" },
- { 0x030b, "IA32_FIXED_CTR2" },
- { 0x038d, "IA32_FIXED_CTR_CTRL" },
- { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
- { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
- { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
- { 0x03f1, "MSR_PEBS_ENABLE" },
- { 0x0480, "IA32_VMX_BASIC" },
- { 0x0481, "IA32_VMX_PINBASED_CTLS" },
- { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
- { 0x0483, "IA32_VMX_EXIT_CTLS" },
- { 0x0484, "IA32_VMX_ENTRY_CTLS" },
- { 0x0485, "IA32_VMX_MISC" },
- { 0x0486, "IA32_VMX_CR0_FIXED0" },
- { 0x0487, "IA32_VMX_CR0_FIXED1" },
- { 0x0488, "IA32_VMX_CR4_FIXED0" },
- { 0x0489, "IA32_VMX_CR4_FIXED1" },
- { 0x048a, "IA32_VMX_VMCS_ENUM" },
- { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
- { 0x0600, "IA32_DS_AREA" },
- };
+ static const msr_entry_t model6_atom_per_core_msrs[] = {
+ { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
+ { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
+ { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
+ { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
+ { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
+ { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
+ { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
+ { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
+ { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
+ { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
+ { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
+ { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
+ { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
+ { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
+ { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
+ { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
+ /* Write register */
+ /*
+ { 0x0079, "IA32_BIOS_UPDT_TRIG" },
+ */
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x00c1, "IA32_PMC0" },
+ { 0x00c2, "IA32_PMC1" },
+ { 0x00e7, "IA32_MPERF" },
+ { 0x00e8, "IA32_APERF" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0186, "IA32_PERF_EVNTSEL0" },
+ { 0x0187, "IA32_PERF_EVNTSEL1" },
+ { 0x0199, "IA32_PERF_CONTROL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x01a0, "IA32_MISC_ENABLES" },
+ { 0x01c9, "MSR_LASTBRANCH_TOS" },
+ { 0x01d9, "IA32_DEBUGCTL" },
+ { 0x01dd, "MSR_LER_FROM_LIP" },
+ { 0x01de, "MSR_LER_TO_LIP" },
+ { 0x0277, "IA32_PAT" },
+ { 0x0309, "IA32_FIXED_CTR0" },
+ { 0x030a, "IA32_FIXED_CTR1" },
+ { 0x030b, "IA32_FIXED_CTR2" },
+ { 0x038d, "IA32_FIXED_CTR_CTRL" },
+ { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
+ { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
+ { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
+ { 0x03f1, "MSR_PEBS_ENABLE" },
+ { 0x0480, "IA32_VMX_BASIC" },
+ { 0x0481, "IA32_VMX_PINBASED_CTLS" },
+ { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+ { 0x0483, "IA32_VMX_EXIT_CTLS" },
+ { 0x0484, "IA32_VMX_ENTRY_CTLS" },
+ { 0x0485, "IA32_VMX_MISC" },
+ { 0x0486, "IA32_VMX_CR0_FIXED0" },
+ { 0x0487, "IA32_VMX_CR0_FIXED1" },
+ { 0x0488, "IA32_VMX_CR4_FIXED0" },
+ { 0x0489, "IA32_VMX_CR4_FIXED1" },
+ { 0x048a, "IA32_VMX_VMCS_ENUM" },
+ { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+ { 0x0600, "IA32_DS_AREA" },
+ };
static const msr_entry_t model20650_global_msrs[] = {
{ 0x0000, "IA32_P5_MC_ADDR" },