Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
| 5 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <fcntl.h> |
| 21 | #include <unistd.h> |
| 22 | #include <stdio.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
| 25 | #include <errno.h> |
| 26 | |
| 27 | #include "inteltool.h" |
| 28 | |
| 29 | int fd_msr; |
| 30 | |
| 31 | unsigned int cpuid(unsigned int op) |
| 32 | { |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 33 | uint32_t ret; |
| 34 | |
| 35 | #if defined(__DARWIN__) && !defined(__LP64__) |
Stefan Reinauer | 1c60c88 | 2010-05-30 12:35:39 +0000 | [diff] [blame] | 36 | asm volatile ( |
| 37 | "pushl %%ebx\n" |
| 38 | "cpuid\n" |
| 39 | "popl %%ebx\n" |
| 40 | : "=a" (ret) : "a" (op) : "%ecx", "%edx" |
| 41 | ); |
Stefan Reinauer | f182456 | 2009-04-22 23:17:44 +0000 | [diff] [blame] | 42 | #else |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 43 | asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx"); |
Stefan Reinauer | f182456 | 2009-04-22 23:17:44 +0000 | [diff] [blame] | 44 | #endif |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 45 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 46 | return ret; |
| 47 | } |
| 48 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 49 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 50 | int msr_readerror = 0; |
| 51 | |
| 52 | msr_t rdmsr(int addr) |
| 53 | { |
| 54 | uint8_t buf[8]; |
| 55 | msr_t msr = { 0xffffffff, 0xffffffff }; |
| 56 | |
| 57 | if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { |
| 58 | perror("Could not lseek() to MSR"); |
| 59 | close(fd_msr); |
| 60 | exit(1); |
| 61 | } |
| 62 | |
| 63 | if (read(fd_msr, buf, 8) == 8) { |
| 64 | msr.lo = *(uint32_t *)buf; |
| 65 | msr.hi = *(uint32_t *)(buf + 4); |
| 66 | |
| 67 | return msr; |
| 68 | } |
| 69 | |
| 70 | if (errno == 5) { |
| 71 | printf(" (*)"); // Not all bits of the MSR could be read |
| 72 | msr_readerror = 1; |
| 73 | } else { |
| 74 | // A severe error. |
| 75 | perror("Could not read() MSR"); |
| 76 | close(fd_msr); |
| 77 | exit(1); |
| 78 | } |
| 79 | |
| 80 | return msr; |
| 81 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 82 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 83 | |
| 84 | int print_intel_core_msrs(void) |
| 85 | { |
| 86 | unsigned int i, core, id; |
| 87 | msr_t msr; |
| 88 | |
| 89 | #define IA32_PLATFORM_ID 0x0017 |
| 90 | #define EBL_CR_POWERON 0x002a |
| 91 | #define FSB_CLK_STS 0x00cd |
| 92 | #define IA32_TIME_STAMP_COUNTER 0x0010 |
| 93 | #define IA32_APIC_BASE 0x001b |
| 94 | |
| 95 | typedef struct { |
| 96 | int number; |
| 97 | char *name; |
| 98 | } msr_entry_t; |
| 99 | |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame^] | 100 | /* Pentium III */ |
| 101 | static const msr_entry_t model67x_global_msrs[] = { |
| 102 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 103 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 104 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 105 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 106 | { 0x001b, "IA32_APIC_BASE" }, |
| 107 | { 0x002a, "EBL_CR_POWERON" }, |
| 108 | { 0x0033, "TEST_CTL" }, |
| 109 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 110 | { 0x0088, "BBL_CR_D0" }, |
| 111 | { 0x0089, "BBL_CR_D1" }, |
| 112 | { 0x008a, "BBL_CR_D2" }, |
| 113 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 114 | { 0x00c1, "PERFCTR0" }, |
| 115 | { 0x00c2, "PERFCTR1" }, |
| 116 | { 0x00fe, "IA32_MTRRCAP" }, |
| 117 | { 0x0116, "BBL_CR_ADDR" }, |
| 118 | { 0x0118, "BBL_CR_DECC" }, |
| 119 | { 0x0119, "BBL_CR_CTL" }, |
| 120 | //{ 0x011a, "BBL_CR_TRIG" }, |
| 121 | { 0x011b, "BBL_CR_BUSY" }, |
| 122 | { 0x011e, "BBL_CR_CTL3" }, |
| 123 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 124 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 125 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 126 | { 0x0179, "IA32_MCG_CAP" }, |
| 127 | { 0x017a, "IA32_MCG_STATUS" }, |
| 128 | { 0x017b, "IA32_MCG_CTL" }, |
| 129 | { 0x0186, "IA32_PERF_EVNTSEL0" }, |
| 130 | { 0x0187, "IA32_PERF_EVNTSEL1" }, |
| 131 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 132 | { 0x01db, "MSR_LASTBRANCHFROMIP" }, |
| 133 | { 0x01dc, "MSR_LASTBRANCHTOIP" }, |
| 134 | { 0x01dd, "MSR_LASTINTFROMIP" }, |
| 135 | { 0x01de, "MSR_LASTINTTOIP" }, |
| 136 | { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, |
| 137 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 138 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 139 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 140 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 141 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 142 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 143 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 144 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 145 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 146 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 147 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 148 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 149 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 150 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 151 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 152 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 153 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 154 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 155 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 156 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 157 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 158 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 159 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 160 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 161 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 162 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 163 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 164 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 165 | { 0x0400, "IA32_MC0_CTL" }, |
| 166 | { 0x0401, "IA32_MC0_STATUS" }, |
| 167 | { 0x0402, "IA32_MC0_ADDR" }, |
| 168 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 169 | { 0x0404, "IA32_MC1_CTL" }, |
| 170 | { 0x0405, "IA32_MC1_STATUS" }, |
| 171 | { 0x0406, "IA32_MC1_ADDR" }, |
| 172 | //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO |
| 173 | { 0x0408, "IA32_MC2_CTL" }, |
| 174 | { 0x0409, "IA32_MC2_STATUS" }, |
| 175 | { 0x040a, "IA32_MC2_ADDR" }, |
| 176 | //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO |
| 177 | { 0x040c, "IA32_MC4_CTL" }, |
| 178 | { 0x040d, "IA32_MC4_STATUS" }, |
| 179 | { 0x040e, "IA32_MC4_ADDR" }, |
| 180 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 181 | { 0x0410, "IA32_MC3_CTL" }, |
| 182 | { 0x0411, "IA32_MC3_STATUS" }, |
| 183 | { 0x0412, "IA32_MC3_ADDR" }, |
| 184 | //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO |
| 185 | }; |
| 186 | |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 187 | static const msr_entry_t model6bx_global_msrs[] = { |
| 188 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 189 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 190 | { 0x001b, "IA32_APIC_BASE" }, |
| 191 | { 0x002a, "EBL_CR_POWERON" }, |
| 192 | { 0x0033, "TEST_CTL" }, |
| 193 | { 0x003f, "THERM_DIODE_OFFSET" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 194 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 195 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 196 | { 0x00c1, "PERFCTR0" }, |
| 197 | { 0x00c2, "PERFCTR1" }, |
| 198 | { 0x011e, "BBL_CR_CTL3" }, |
| 199 | { 0x0179, "IA32_MCG_CAP" }, |
| 200 | { 0x017a, "IA32_MCG_STATUS" }, |
| 201 | { 0x0198, "IA32_PERF_STATUS" }, |
| 202 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 203 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 204 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 205 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 206 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 207 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 208 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 209 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 210 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 211 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 212 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 213 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 214 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 215 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 216 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 217 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 218 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 219 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 220 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 221 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 222 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 223 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 224 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 225 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 226 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 227 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 228 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 229 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 230 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 231 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 232 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 233 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 234 | { 0x0400, "IA32_MC0_CTL" }, |
| 235 | { 0x0401, "IA32_MC0_STATUS" }, |
| 236 | { 0x0402, "IA32_MC0_ADDR" }, |
| 237 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 238 | { 0x040c, "IA32_MC4_CTL" }, |
| 239 | { 0x040d, "IA32_MC4_STATUS" }, |
| 240 | { 0x040e, "IA32_MC4_ADDR" }, |
| 241 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 242 | }; |
| 243 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 244 | static const msr_entry_t model6ex_global_msrs[] = { |
| 245 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 246 | { 0x002a, "EBL_CR_POWERON" }, |
| 247 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 248 | { 0x00ce, "FSB_CLOCK_VCC" }, |
| 249 | { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, |
| 250 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 251 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 252 | { 0x00ee, "EXT_CONFIG" }, |
| 253 | { 0x011e, "BBL_CR_CTL3" }, |
| 254 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 255 | { 0x0198, "IA32_PERF_STATUS" }, |
| 256 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 257 | { 0x01aa, "PIC_SENS_CFG" }, |
| 258 | { 0x0400, "IA32_MC0_CTL" }, |
| 259 | { 0x0401, "IA32_MC0_STATUS" }, |
| 260 | { 0x0402, "IA32_MC0_ADDR" }, |
| 261 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 262 | { 0x040c, "IA32_MC4_CTL" }, |
| 263 | { 0x040d, "IA32_MC4_STATUS" }, |
| 264 | { 0x040e, "IA32_MC4_ADDR" }, |
| 265 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 266 | }; |
| 267 | |
| 268 | static const msr_entry_t model6ex_per_core_msrs[] = { |
| 269 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 270 | { 0x001b, "IA32_APIC_BASE" }, |
| 271 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 272 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 273 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 274 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 275 | { 0x00e7, "IA32_MPERF" }, |
| 276 | { 0x00e8, "IA32_APERF" }, |
| 277 | { 0x00fe, "IA32_MTRRCAP" }, |
| 278 | { 0x015f, "DTS_CAL_CTRL" }, |
| 279 | { 0x0179, "IA32_MCG_CAP" }, |
| 280 | { 0x017a, "IA32_MCG_STATUS" }, |
| 281 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 282 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 283 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 284 | { 0x019c, "IA32_THERM_STATUS" }, |
| 285 | { 0x019d, "GV_THERM" }, |
| 286 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 287 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 288 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 289 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 290 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 291 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 292 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 293 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 294 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 295 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 296 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 297 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 298 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 299 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 300 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 301 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 302 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 303 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 304 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 305 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 306 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 307 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 308 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 309 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 310 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 311 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 312 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 313 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 314 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 315 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 316 | }; |
| 317 | |
| 318 | static const msr_entry_t model6fx_global_msrs[] = { |
| 319 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 320 | { 0x002a, "EBL_CR_POWERON" }, |
| 321 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 322 | { 0x00a8, "EMTTM_CR_TABLE0" }, |
| 323 | { 0x00a9, "EMTTM_CR_TABLE1" }, |
| 324 | { 0x00aa, "EMTTM_CR_TABLE2" }, |
| 325 | { 0x00ab, "EMTTM_CR_TABLE3" }, |
| 326 | { 0x00ac, "EMTTM_CR_TABLE4" }, |
| 327 | { 0x00ad, "EMTTM_CR_TABLE5" }, |
| 328 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 329 | { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, |
| 330 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 331 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 332 | { 0x00ee, "EXT_CONFIG" }, |
| 333 | { 0x011e, "BBL_CR_CTL3" }, |
| 334 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 335 | { 0x0198, "IA32_PERF_STATUS" }, |
| 336 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 337 | { 0x01aa, "PIC_SENS_CFG" }, |
| 338 | { 0x0400, "IA32_MC0_CTL" }, |
| 339 | { 0x0401, "IA32_MC0_STATUS" }, |
| 340 | { 0x0402, "IA32_MC0_ADDR" }, |
| 341 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 342 | { 0x040c, "IA32_MC4_CTL" }, |
| 343 | { 0x040d, "IA32_MC4_STATUS" }, |
| 344 | { 0x040e, "IA32_MC4_ADDR" }, |
| 345 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 346 | }; |
| 347 | |
| 348 | static const msr_entry_t model6fx_per_core_msrs[] = { |
| 349 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 350 | { 0x001b, "IA32_APIC_BASE" }, |
| 351 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 352 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 353 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 354 | { 0x00e1, "SMM_CST_MISC_INFO" }, |
| 355 | { 0x00e7, "IA32_MPERF" }, |
| 356 | { 0x00e8, "IA32_APERF" }, |
| 357 | { 0x00fe, "IA32_MTRRCAP" }, |
| 358 | { 0x0179, "IA32_MCG_CAP" }, |
| 359 | { 0x017a, "IA32_MCG_STATUS" }, |
| 360 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 361 | { 0x019a, "IA32_THERM_CTL" }, |
| 362 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 363 | { 0x019c, "IA32_THERM_STATUS" }, |
| 364 | { 0x019d, "MSR_THERM2_CTL" }, |
| 365 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 366 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 367 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 368 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 369 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 370 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 371 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 372 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 373 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 374 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 375 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 376 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 377 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 378 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 379 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 380 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 381 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 382 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 383 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 384 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 385 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 386 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 387 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 388 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 389 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 390 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 391 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 392 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 393 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 394 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 395 | }; |
| 396 | |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 397 | /* Pentium 4 and XEON */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 398 | /* |
| 399 | * All MSRs per |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 400 | * |
| 401 | * Intel® 64 and IA-32 Architectures |
| 402 | * Software Developer.s Manual |
| 403 | * Volume 3B: |
| 404 | * System Programming Guide, Part 2 |
| 405 | * |
| 406 | * Table B-5 |
| 407 | */ |
| 408 | static const msr_entry_t modelf4x_global_msrs[] = { |
| 409 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 410 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 411 | { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, |
| 412 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 413 | { 0x002a, "MSR_EBC_HARD_POWERON" }, |
| 414 | { 0x002b, "MSR_EBC_SOFT_POWRON" }, |
| 415 | { 0x002c, "MSR_EBC_FREQUENCY_ID" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 416 | // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 417 | { 0x019c, "IA32_THERM_STATUS" }, |
| 418 | { 0x019d, "MSR_THERM2_CTL" }, |
| 419 | { 0x01a0, "IA32_MISC_ENABLE" }, |
| 420 | { 0x01a1, "MSR_PLATFORM_BRV" }, |
| 421 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 422 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 423 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 424 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 425 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 426 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 427 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 428 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 429 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 430 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 431 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 432 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 433 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 434 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 435 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 436 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 437 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 438 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 439 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 440 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 441 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 442 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 443 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 444 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 445 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 446 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 447 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 448 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 449 | { 0x0300, "MSR_BPU_COUNTER0" }, |
| 450 | { 0x0301, "MSR_BPU_COUNTER1" }, |
| 451 | { 0x0302, "MSR_BPU_COUNTER2" }, |
| 452 | { 0x0303, "MSR_BPU_COUNTER3" }, |
| 453 | /* Skipped through 0x3ff for now*/ |
| 454 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 455 | /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 456 | * set in MCX_STATUS */ |
| 457 | { 0x400, "IA32_MC0_CTL" }, |
| 458 | { 0x401, "IA32_MC0_STATUS" }, |
| 459 | { 0x402, "IA32_MC0_ADDR" }, |
| 460 | { 0x403, "IA32_MC0_MISC" }, |
| 461 | { 0x404, "IA32_MC1_CTL" }, |
| 462 | { 0x405, "IA32_MC1_STATUS" }, |
| 463 | { 0x406, "IA32_MC1_ADDR" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 464 | { 0x407, "IA32_MC1_MISC" }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 465 | { 0x408, "IA32_MC2_CTL" }, |
| 466 | { 0x409, "IA32_MC2_STATUS" }, |
| 467 | { 0x40a, "IA32_MC2_ADDR" }, |
| 468 | { 0x40b, "IA32_MC2_MISC" }, |
| 469 | { 0x40c, "IA32_MC3_CTL" }, |
| 470 | { 0x40d, "IA32_MC3_STATUS" }, |
| 471 | { 0x40e, "IA32_MC3_ADDR" }, |
| 472 | { 0x40f, "IA32_MC3_MISC" }, |
| 473 | { 0x410, "IA32_MC4_CTL" }, |
| 474 | { 0x411, "IA32_MC4_STATUS" }, |
| 475 | { 0x412, "IA32_MC4_ADDR" }, |
| 476 | { 0x413, "IA32_MC4_MISC" }, |
| 477 | }; |
| 478 | |
| 479 | static const msr_entry_t modelf4x_per_core_msrs[] = { |
| 480 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 481 | { 0x001b, "IA32_APIC_BASE" }, |
| 482 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 483 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 484 | { 0x009b, "IA32_SMM_MONITOR_CTL" }, |
| 485 | { 0x00fe, "IA32_MTRRCAP" }, |
| 486 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 487 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 488 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 489 | { 0x0179, "IA32_MCG_CAP" }, |
| 490 | { 0x017a, "IA32_MCG_STATUS" }, |
| 491 | { 0x0180, "MSR_MCG_RAX" }, |
| 492 | { 0x0181, "MSR_MCG_RBX" }, |
| 493 | { 0x0182, "MSR_MCG_RCX" }, |
| 494 | { 0x0183, "MSR_MCG_RDX" }, |
| 495 | { 0x0184, "MSR_MCG_RSI" }, |
| 496 | { 0x0185, "MSR_MCG_RDI" }, |
| 497 | { 0x0186, "MSR_MCG_RBP" }, |
| 498 | { 0x0187, "MSR_MCG_RSP" }, |
| 499 | { 0x0188, "MSR_MCG_RFLAGS" }, |
| 500 | { 0x0189, "MSR_MCG_RIP" }, |
| 501 | { 0x018a, "MSR_MCG_MISC" }, |
| 502 | // 0x18b-f Reserved |
| 503 | { 0x0190, "MSR_MCG_R8" }, |
| 504 | { 0x0191, "MSR_MCG_R9" }, |
| 505 | { 0x0192, "MSR_MCG_R10" }, |
| 506 | { 0x0193, "MSR_MCG_R11" }, |
| 507 | { 0x0194, "MSR_MCG_R12" }, |
| 508 | { 0x0195, "MSR_MCG_R13" }, |
| 509 | { 0x0196, "MSR_MCG_R14" }, |
| 510 | { 0x0197, "MSR_MCG_R15" }, |
| 511 | { 0x0198, "IA32_PERF_STATUS" }, |
| 512 | { 0x0199, "IA32_PERF_CTL" }, |
| 513 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 514 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 515 | { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific |
| 516 | { 0x01d7, "MSR_LER_FROM_LIP" }, |
| 517 | { 0x01d8, "MSR_LER_TO_LIP" }, |
| 518 | { 0x01d9, "MSR_DEBUGCTLA" }, |
| 519 | { 0x01da, "MSR_LASTBRANCH_TOS" }, |
| 520 | { 0x0277, "IA32_PAT" }, |
| 521 | /** Virtualization |
| 522 | { 0x480, "IA32_VMX_BASIC" }, |
| 523 | through |
| 524 | { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, |
| 525 | Not implemented in my CPU |
| 526 | */ |
| 527 | { 0x0600, "IA32_DS_AREA" }, |
| 528 | /* 0x0680 - 0x06cf Branch Records Skipped */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 529 | |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 530 | }; |
| 531 | |
| 532 | |
| 533 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 534 | typedef struct { |
| 535 | unsigned int model; |
| 536 | const msr_entry_t *global_msrs; |
| 537 | unsigned int num_global_msrs; |
| 538 | const msr_entry_t *per_core_msrs; |
| 539 | unsigned int num_per_core_msrs; |
| 540 | } cpu_t; |
| 541 | |
| 542 | cpu_t cpulist[] = { |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame^] | 543 | { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 544 | { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 545 | { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, |
| 546 | { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 547 | { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 548 | }; |
| 549 | |
| 550 | cpu_t *cpu = NULL; |
| 551 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 552 | /* Get CPU family and model, not the stepping |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 553 | * (TODO: extended family/model) |
| 554 | */ |
Stefan Reinauer | 74cd5698 | 2010-06-01 10:04:28 +0000 | [diff] [blame] | 555 | id = cpuid(1) & 0xfffff0; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 556 | for (i = 0; i < ARRAY_SIZE(cpulist); i++) { |
| 557 | if(cpulist[i].model == id) { |
| 558 | cpu = &cpulist[i]; |
| 559 | break; |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | if (!cpu) { |
| 564 | printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); |
| 565 | return -1; |
| 566 | } |
| 567 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 568 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 569 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
| 570 | if (fd_msr < 0) { |
| 571 | perror("Error while opening /dev/cpu/0/msr"); |
| 572 | printf("Did you run 'modprobe msr'?\n"); |
| 573 | return -1; |
| 574 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 575 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 576 | |
| 577 | printf("\n===================== SHARED MSRs (All Cores) =====================\n"); |
| 578 | |
| 579 | for (i = 0; i < cpu->num_global_msrs; i++) { |
| 580 | msr = rdmsr(cpu->global_msrs[i].number); |
| 581 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 582 | cpu->global_msrs[i].number, msr.hi, msr.lo, |
| 583 | cpu->global_msrs[i].name); |
| 584 | } |
| 585 | |
| 586 | close(fd_msr); |
| 587 | |
| 588 | for (core = 0; core < 8; core++) { |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 589 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 590 | char msrfilename[64]; |
| 591 | memset(msrfilename, 0, 64); |
| 592 | sprintf(msrfilename, "/dev/cpu/%d/msr", core); |
| 593 | |
| 594 | fd_msr = open(msrfilename, O_RDWR); |
| 595 | |
| 596 | /* If the file is not there, we're probably through. No error, |
| 597 | * since we successfully opened /dev/cpu/0/msr before. |
| 598 | */ |
| 599 | if (fd_msr < 0) |
| 600 | break; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 601 | #endif |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 602 | if (cpu->num_per_core_msrs) |
| 603 | printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 604 | |
| 605 | for (i = 0; i < cpu->num_per_core_msrs; i++) { |
| 606 | msr = rdmsr(cpu->per_core_msrs[i].number); |
| 607 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 608 | cpu->per_core_msrs[i].number, msr.hi, msr.lo, |
| 609 | cpu->per_core_msrs[i].name); |
| 610 | } |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 611 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 612 | close(fd_msr); |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 613 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 614 | } |
| 615 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 616 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 617 | if (msr_readerror) |
| 618 | printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 619 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 620 | return 0; |
| 621 | } |
| 622 | |
| 623 | |