Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 7 | #include <option.h> |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 8 | #include <pc80/mc146818rtc.h> |
| 9 | #include <pc80/isa-dma.h> |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 10 | #include <pc80/i8259.h> |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 11 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 13 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 14 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 15 | #include <acpi/acpi_gnvs.h> |
Sven Schnelle | f4dc1a7 | 2011-06-05 11:33:41 +0200 | [diff] [blame] | 16 | #include <cpu/x86/smm.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 17 | #include <acpi/acpigen.h> |
Vladimir Serbinenko | d5d94ea | 2014-10-18 02:13:11 +0200 | [diff] [blame] | 18 | #include <arch/smp/mpspec.h> |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 19 | #include <cbmem.h> |
| 20 | #include <string.h> |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 21 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 22 | #include <southbridge/intel/common/pmbase.h> |
Arthur Heymans | b429c5b | 2019-05-28 13:24:15 +0200 | [diff] [blame] | 23 | #include <southbridge/intel/common/spi.h> |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 24 | |
Arthur Heymans | 742df5a | 2019-06-03 16:24:41 +0200 | [diff] [blame] | 25 | #include "chip.h" |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 26 | #include "i82801gx.h" |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 27 | #include "nvs.h" |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 28 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 29 | #define NMI_OFF 0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 30 | |
Paul Menzel | ddddf15 | 2013-04-23 14:40:23 +0200 | [diff] [blame] | 31 | /** |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 32 | * Set miscellaneous static southbridge features. |
Paul Menzel | ddddf15 | 2013-04-23 14:40:23 +0200 | [diff] [blame] | 33 | * |
| 34 | * @param dev PCI device with I/O APIC control registers |
| 35 | */ |
| 36 | static void i82801gx_enable_ioapic(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 37 | { |
Paul Menzel | ddddf15 | 2013-04-23 14:40:23 +0200 | [diff] [blame] | 38 | /* Enable ACPI I/O range decode */ |
Kyösti Mälkki | 1cca340 | 2013-02-26 19:21:39 +0200 | [diff] [blame] | 39 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 40 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 41 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 42 | |
Paul Menzel | ddddf15 | 2013-04-23 14:40:23 +0200 | [diff] [blame] | 43 | /* |
| 44 | * Select Boot Configuration register (0x03) and |
| 45 | * use Processor System Bus (0x01) to deliver interrupts. |
| 46 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static void i82801gx_enable_serial_irqs(struct device *dev) |
| 51 | { |
| 52 | /* Set packet length and toggle silent mode bit for one frame. */ |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 53 | pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 56 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 57 | * 0x00 - 0000 = Reserved |
| 58 | * 0x01 - 0001 = Reserved |
| 59 | * 0x02 - 0010 = Reserved |
| 60 | * 0x03 - 0011 = IRQ3 |
| 61 | * 0x04 - 0100 = IRQ4 |
| 62 | * 0x05 - 0101 = IRQ5 |
| 63 | * 0x06 - 0110 = IRQ6 |
| 64 | * 0x07 - 0111 = IRQ7 |
| 65 | * 0x08 - 1000 = Reserved |
| 66 | * 0x09 - 1001 = IRQ9 |
| 67 | * 0x0A - 1010 = IRQ10 |
| 68 | * 0x0B - 1011 = IRQ11 |
| 69 | * 0x0C - 1100 = IRQ12 |
| 70 | * 0x0D - 1101 = Reserved |
| 71 | * 0x0E - 1110 = IRQ14 |
| 72 | * 0x0F - 1111 = IRQ15 |
| 73 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 74 | * 0x80 - The PIRQ is not routed. |
| 75 | */ |
| 76 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 77 | static void i82801gx_pirq_init(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 78 | { |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 79 | struct device *irq_dev; |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 80 | /* Get the chip configuration */ |
Elyes HAOUAS | 8d9a6f1 | 2020-04-28 04:57:27 +0200 | [diff] [blame] | 81 | const struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 82 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 83 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 84 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 85 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 86 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 87 | |
| 88 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 89 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 90 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 91 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 92 | |
| 93 | /* Eric Biederman once said we should let the OS do this. |
| 94 | * I am not so sure anymore he was right. |
| 95 | */ |
| 96 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 97 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 98 | u8 int_pin = 0, int_line = 0; |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 99 | |
| 100 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 101 | continue; |
| 102 | |
| 103 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 104 | |
| 105 | switch (int_pin) { |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 106 | case 1: |
| 107 | /* INTA# */ int_line = config->pirqa_routing; break; |
| 108 | case 2: |
| 109 | /* INTB# */ int_line = config->pirqb_routing; break; |
| 110 | case 3: |
| 111 | /* INTC# */ int_line = config->pirqc_routing; break; |
| 112 | case 4: |
| 113 | /* INTD# */ int_line = config->pirqd_routing; break; |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | if (!int_line) |
| 117 | continue; |
| 118 | |
| 119 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 120 | } |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 121 | } |
| 122 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 123 | static void i82801gx_gpi_routing(struct device *dev) |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 124 | { |
| 125 | /* Get the chip configuration */ |
Elyes HAOUAS | 8d9a6f1 | 2020-04-28 04:57:27 +0200 | [diff] [blame] | 126 | const struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 127 | u32 reg32 = 0; |
| 128 | |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 129 | /* An array would be much nicer here, or some other method of doing this. */ |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 130 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 131 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 132 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 133 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 134 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 135 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 136 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 137 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 138 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 139 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 140 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 141 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 142 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 143 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 144 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 145 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 146 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 147 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 148 | } |
| 149 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 150 | static void i82801gx_power_options(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 151 | { |
| 152 | u8 reg8; |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 153 | u16 reg16; |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 154 | u32 reg32; |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 155 | const char *state; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 156 | /* Get the chip configuration */ |
Elyes HAOUAS | 8d9a6f1 | 2020-04-28 04:57:27 +0200 | [diff] [blame] | 157 | const struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 158 | |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 159 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 160 | int nmi_option; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 161 | |
| 162 | /* Which state do we want to goto after g3 (power restored)? |
| 163 | * 0 == S0 Full On |
| 164 | * 1 == S5 Soft Off |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 165 | * |
| 166 | * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 167 | */ |
Varad Gautam | 06ef046 | 2015-03-11 09:54:41 +0530 | [diff] [blame] | 168 | pwr_on = MAINBOARD_POWER_ON; |
| 169 | get_option(&pwr_on, "power_on_after_fail"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 170 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 171 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 172 | reg8 &= 0xfe; |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 173 | switch (pwr_on) { |
| 174 | case MAINBOARD_POWER_OFF: |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 175 | reg8 |= 1; |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 176 | state = "off"; |
| 177 | break; |
| 178 | case MAINBOARD_POWER_ON: |
| 179 | reg8 &= ~1; |
| 180 | state = "on"; |
| 181 | break; |
| 182 | case MAINBOARD_POWER_KEEP: |
| 183 | reg8 &= ~1; |
| 184 | state = "state keep"; |
| 185 | break; |
| 186 | default: |
| 187 | state = "undefined"; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 188 | } |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 189 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 190 | reg8 |= (3 << 4); /* avoid #S4 assertions */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 191 | reg8 &= ~(1 << 3); /* minimum assertion is 1 to 2 RTCCLK */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 192 | |
| 193 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 194 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 195 | |
| 196 | /* Set up NMI on errors. */ |
| 197 | reg8 = inb(0x61); |
| 198 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 199 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 200 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 201 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 202 | outb(reg8, 0x61); |
| 203 | |
| 204 | reg8 = inb(0x70); |
| 205 | nmi_option = NMI_OFF; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 206 | get_option(&nmi_option, "nmi"); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 207 | if (nmi_option) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 208 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 209 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 210 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 211 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 212 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 213 | } |
| 214 | outb(reg8, 0x70); |
| 215 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 216 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 217 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 218 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 219 | reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only |
| 220 | reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only |
| 221 | reg16 |= (1 << 5); // CPUSLP_EN Desktop only |
Sven Schnelle | 906f9ae | 2011-10-23 16:35:01 +0200 | [diff] [blame] | 222 | |
| 223 | if (config->c4onc3_enable) |
| 224 | reg16 |= (1 << 7); |
| 225 | |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 226 | // another laptop wants this? |
| 227 | // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only |
| 228 | reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only |
Kyösti Mälkki | 9446447 | 2020-06-13 13:45:42 +0300 | [diff] [blame] | 229 | if (CONFIG(DEBUG_PERIODIC_SMI)) |
| 230 | reg16 |= (3 << 0); // Periodic SMI every 8s |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 231 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 232 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 233 | // Set the board's GPI routing. |
| 234 | i82801gx_gpi_routing(dev); |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 235 | |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 236 | write_pmbase32(GPE0_EN, config->gpe0_en); |
| 237 | write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 238 | |
| 239 | /* Set up power management block and determine sleep mode */ |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 240 | reg32 = read_pmbase32(PM1_CNT); |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 241 | |
| 242 | reg32 &= ~(7 << 10); // SLP_TYP |
| 243 | reg32 |= (1 << 1); // enable C3->C0 transition on bus master |
| 244 | reg32 |= (1 << 0); // SCI_EN |
Elyes HAOUAS | 7118701 | 2019-02-10 14:58:13 +0100 | [diff] [blame] | 245 | write_pmbase32(PM1_CNT, reg32); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 246 | } |
| 247 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 248 | static void i82801gx_configure_cstates(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 249 | { |
| 250 | u8 reg8; |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 251 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 252 | reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration |
| 253 | reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown |
| 254 | pci_write_config8(dev, 0xa9, reg8); |
| 255 | |
| 256 | // Set Deeper Sleep configuration to recommended values |
| 257 | reg8 = pci_read_config8(dev, 0xaa); |
| 258 | reg8 &= 0xf0; |
| 259 | reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us |
| 260 | reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us |
| 261 | pci_write_config8(dev, 0xaa, reg8); |
| 262 | } |
| 263 | |
| 264 | static void i82801gx_rtc_init(struct device *dev) |
| 265 | { |
| 266 | u8 reg8; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 267 | int rtc_failed; |
| 268 | |
| 269 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 270 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 271 | if (rtc_failed) { |
| 272 | reg8 &= ~RTC_BATTERY_DEAD; |
| 273 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 274 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 275 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 276 | |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 277 | cmos_init(rtc_failed); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 278 | } |
| 279 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 280 | static void enable_hpet(void) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 281 | { |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 282 | u32 reg32; |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 283 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 284 | /* Move HPET to default address 0xfed00000 and enable it */ |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 285 | reg32 = RCBA32(HPTC); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 286 | reg32 |= (1 << 7); // HPET Address Enable |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 287 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 288 | RCBA32(HPTC) = reg32; |
Arthur Heymans | c73c923 | 2019-10-02 14:57:50 +0200 | [diff] [blame] | 289 | /* On NM10 this only works if read back */ |
| 290 | RCBA32(HPTC); |
| 291 | |
| 292 | write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 293 | } |
| 294 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 295 | static void enable_clock_gating(void) |
| 296 | { |
| 297 | u32 reg32; |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 298 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 299 | /* Enable Clock Gating for most devices */ |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 300 | reg32 = RCBA32(CG); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 301 | reg32 |= (1 << 31); // LPC clock gating |
| 302 | reg32 |= (1 << 30); // PATA clock gating |
| 303 | // SATA clock gating |
| 304 | reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); |
| 305 | reg32 |= (1 << 23); // AC97 clock gating |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 306 | reg32 |= (1 << 19); // USB EHCI clock gating |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 307 | reg32 |= (1 << 3) | (1 << 1); // DMI clock gating |
| 308 | reg32 |= (1 << 2); // PCIe clock gating; |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 309 | reg32 &= ~(1 << 20); // No static clock gating for USB |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 310 | reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 311 | RCBA32(CG) = reg32; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 312 | } |
Stefan Reinauer | 269563a | 2009-01-19 21:20:22 +0000 | [diff] [blame] | 313 | |
Kyösti Mälkki | 83d6a8a | 2019-07-12 08:16:53 +0300 | [diff] [blame] | 314 | static void i82801gx_set_acpi_mode(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 315 | { |
Kyösti Mälkki | ad882c3 | 2020-06-02 05:05:30 +0300 | [diff] [blame] | 316 | if (!acpi_is_wakeup_s3()) { |
| 317 | apm_control(APM_CNT_ACPI_DISABLE); |
| 318 | } else { |
| 319 | apm_control(APM_CNT_ACPI_ENABLE); |
Sven Schnelle | e261807 | 2011-06-05 11:39:12 +0200 | [diff] [blame] | 320 | } |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 323 | #define SPIBASE 0x3020 |
| 324 | static void i82801gx_spi_init(void) |
| 325 | { |
| 326 | u16 spicontrol; |
| 327 | |
| 328 | spicontrol = RCBA16(SPIBASE + 2); |
| 329 | spicontrol &= ~(1 << 0); // SPI Access Request |
| 330 | RCBA16(SPIBASE + 2) = spicontrol; |
| 331 | } |
| 332 | |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 333 | static void i82801gx_fixups(struct device *dev) |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 334 | { |
| 335 | /* This needs to happen after PCI enumeration */ |
| 336 | RCBA32(0x1d40) |= 1; |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 337 | |
| 338 | /* USB Transient Disconnect Detect: |
| 339 | * Prevent a SE0 condition on the USB ports from being |
| 340 | * interpreted by the UHCI controller as a disconnect |
| 341 | */ |
| 342 | pci_write_config8(dev, 0xad, 0x3); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 343 | } |
| 344 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 345 | static void lpc_init(struct device *dev) |
| 346 | { |
Elyes HAOUAS | bfc255a | 2020-03-07 13:05:14 +0100 | [diff] [blame] | 347 | printk(BIOS_DEBUG, "i82801gx: %s\n", __func__); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 348 | |
| 349 | /* Set the value for PCI command register. */ |
Angel Pons | 89739ba | 2020-07-25 02:46:39 +0200 | [diff] [blame] | 350 | pci_write_config16(dev, PCI_COMMAND, |
| 351 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | |
| 352 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 353 | |
| 354 | /* IO APIC initialization. */ |
Paul Menzel | ddddf15 | 2013-04-23 14:40:23 +0200 | [diff] [blame] | 355 | i82801gx_enable_ioapic(dev); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 356 | |
| 357 | i82801gx_enable_serial_irqs(dev); |
| 358 | |
| 359 | /* Setup the PIRQ. */ |
| 360 | i82801gx_pirq_init(dev); |
| 361 | |
| 362 | /* Setup power options. */ |
| 363 | i82801gx_power_options(dev); |
| 364 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 365 | /* Configure Cx state registers */ |
| 366 | i82801gx_configure_cstates(dev); |
| 367 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 368 | /* Set the state of the GPIO lines. */ |
| 369 | //gpio_init(dev); |
| 370 | |
| 371 | /* Initialize the real time clock. */ |
| 372 | i82801gx_rtc_init(dev); |
| 373 | |
| 374 | /* Initialize ISA DMA. */ |
| 375 | isa_dma_init(); |
| 376 | |
| 377 | /* Initialize the High Precision Event Timers, if present. */ |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 378 | enable_hpet(); |
| 379 | |
| 380 | /* Initialize Clock Gating */ |
| 381 | enable_clock_gating(); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 382 | |
| 383 | setup_i8259(); |
| 384 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 385 | /* The OS should do this? */ |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 386 | /* Interrupt 9 should be level triggered (SCI) */ |
| 387 | i8259_configure_irq_trigger(9, 1); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 388 | |
Kyösti Mälkki | 44da9e7 | 2019-10-09 12:32:16 +0300 | [diff] [blame] | 389 | i82801gx_set_acpi_mode(dev); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 390 | |
| 391 | i82801gx_spi_init(); |
| 392 | |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 393 | i82801gx_fixups(dev); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Vladimir Serbinenko | d5d94ea | 2014-10-18 02:13:11 +0200 | [diff] [blame] | 396 | unsigned long acpi_fill_madt(unsigned long current) |
| 397 | { |
| 398 | /* Local APICs */ |
| 399 | current = acpi_create_madt_lapics(current); |
| 400 | |
| 401 | /* IOAPIC */ |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 402 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); |
Vladimir Serbinenko | d5d94ea | 2014-10-18 02:13:11 +0200 | [diff] [blame] | 403 | |
| 404 | /* LAPIC_NMI */ |
| 405 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) |
| 406 | current, 0, |
| 407 | MP_IRQ_POLARITY_HIGH | |
| 408 | MP_IRQ_TRIGGER_EDGE, 0x01); |
| 409 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) |
| 410 | current, 1, MP_IRQ_POLARITY_HIGH | |
| 411 | MP_IRQ_TRIGGER_EDGE, 0x01); |
| 412 | |
| 413 | /* INT_SRC_OVR */ |
| 414 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 415 | current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); |
| 416 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 417 | current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); |
| 418 | |
| 419 | |
| 420 | return current; |
| 421 | } |
| 422 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 423 | static void i82801gx_lpc_read_resources(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 424 | { |
| 425 | struct resource *res; |
Vladimir Serbinenko | f119f08 | 2014-11-24 21:05:56 +0100 | [diff] [blame] | 426 | u8 io_index = 0; |
| 427 | int i; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 428 | |
| 429 | /* Get the normal PCI resources of this device. */ |
| 430 | pci_dev_read_resources(dev); |
| 431 | |
| 432 | /* Add an extra subtractive resource for both memory and I/O. */ |
Vladimir Serbinenko | f119f08 | 2014-11-24 21:05:56 +0100 | [diff] [blame] | 433 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 434 | res->base = 0; |
| 435 | res->size = 0x1000; |
| 436 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 437 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 438 | |
Vladimir Serbinenko | f119f08 | 2014-11-24 21:05:56 +0100 | [diff] [blame] | 439 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 440 | res->base = 0xff800000; |
| 441 | res->size = 0x00800000; /* 8 MB for flash */ |
| 442 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 443 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 444 | |
| 445 | res = new_resource(dev, 3); /* IOAPIC */ |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 446 | res->base = IO_APIC_ADDR; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 447 | res->size = 0x00001000; |
| 448 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Vladimir Serbinenko | f119f08 | 2014-11-24 21:05:56 +0100 | [diff] [blame] | 449 | |
| 450 | /* Set IO decode ranges if required.*/ |
| 451 | for (i = 0; i < 4; i++) { |
| 452 | u32 gen_dec; |
| 453 | gen_dec = pci_read_config32(dev, 0x84 + 4 * i); |
| 454 | |
| 455 | if ((gen_dec & 0xFFFC) > 0x1000) { |
| 456 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 457 | res->base = gen_dec & 0xFFFC; |
| 458 | res->size = (gen_dec >> 16) & 0xFC; |
| 459 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 460 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 461 | } |
| 462 | } |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 463 | } |
| 464 | |
Arthur Heymans | 3664647 | 2018-01-22 14:42:18 +0100 | [diff] [blame] | 465 | #define SPIBAR16(x) RCBA16(0x3020 + x) |
| 466 | #define SPIBAR32(x) RCBA32(0x3020 + x) |
| 467 | |
| 468 | static void lpc_final(struct device *dev) |
| 469 | { |
| 470 | u16 tco1_cnt; |
| 471 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 472 | if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) |
Arthur Heymans | 3664647 | 2018-01-22 14:42:18 +0100 | [diff] [blame] | 473 | return; |
| 474 | |
Arthur Heymans | 767de0a | 2019-11-15 19:19:53 +0100 | [diff] [blame] | 475 | if (CONFIG(BOOT_DEVICE_SPI_FLASH)) |
| 476 | spi_finalize_ops(); |
Arthur Heymans | 3664647 | 2018-01-22 14:42:18 +0100 | [diff] [blame] | 477 | |
| 478 | /* Lock SPIBAR */ |
| 479 | SPIBAR16(0) = SPIBAR16(0) | (1 << 15); |
| 480 | |
| 481 | /* BIOS Interface Lockdown */ |
| 482 | RCBA32(0x3410) |= 1 << 0; |
| 483 | |
| 484 | /* Global SMI Lock */ |
| 485 | pci_or_config16(dev, GEN_PMCON_1, 1 << 4); |
| 486 | |
| 487 | /* TCO_Lock */ |
| 488 | tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); |
| 489 | tco1_cnt |= (1 << 12); /* TCO lock */ |
| 490 | outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); |
| 491 | |
| 492 | /* Indicate finalize step with post code */ |
| 493 | outb(POST_OS_BOOT, 0x80); |
| 494 | } |
| 495 | |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 496 | void southbridge_inject_dsdt(const struct device *dev) |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 497 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 498 | struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 499 | |
| 500 | if (gnvs) { |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 501 | memset(gnvs, 0, sizeof(*gnvs)); |
Vladimir Serbinenko | 385743a | 2014-10-18 02:26:21 +0200 | [diff] [blame] | 502 | |
| 503 | gnvs->apic = 1; |
| 504 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 505 | |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 506 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 507 | |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 508 | /* And tell SMI about it */ |
Kyösti Mälkki | c3c5521 | 2020-06-17 10:34:26 +0300 | [diff] [blame] | 509 | apm_control(APM_CNT_GNVS_UPDATE); |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 510 | |
| 511 | /* Add it to SSDT. */ |
Vladimir Serbinenko | 1bad88e | 2014-11-04 21:20:56 +0100 | [diff] [blame] | 512 | acpigen_write_scope("\\"); |
| 513 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 514 | acpigen_pop_len(); |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 518 | static const char *lpc_acpi_name(const struct device *dev) |
| 519 | { |
| 520 | return "LPCB"; |
| 521 | } |
| 522 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 523 | static void southbridge_fill_ssdt(const struct device *device) |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 524 | { |
| 525 | intel_acpi_gen_def_acpi_pirq(device); |
| 526 | } |
| 527 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 528 | static struct device_operations device_ops = { |
| 529 | .read_resources = i82801gx_lpc_read_resources, |
| 530 | .set_resources = pci_dev_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 531 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 532 | .acpi_inject_dsdt = southbridge_inject_dsdt, |
Vladimir Serbinenko | 0e64617 | 2014-08-31 00:27:05 +0200 | [diff] [blame] | 533 | .write_acpi_tables = acpi_write_hpet, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 534 | .acpi_fill_ssdt = southbridge_fill_ssdt, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 535 | .acpi_name = lpc_acpi_name, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 536 | .init = lpc_init, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 537 | .scan_bus = scan_static_bus, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 538 | .enable = i82801gx_enable, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 539 | .ops_pci = &pci_dev_ops_pci, |
Arthur Heymans | 3664647 | 2018-01-22 14:42:18 +0100 | [diff] [blame] | 540 | .final = lpc_final, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 541 | }; |
| 542 | |
Damien Zammit | ef33e03 | 2015-11-14 01:03:39 +1100 | [diff] [blame] | 543 | static const unsigned short pci_device_ids[] = { |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 544 | 0x27b0, /* 82801GH (ICH7 DH) */ |
| 545 | 0x27b8, /* 82801GB/GR (ICH7/ICH7R) */ |
| 546 | 0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */ |
| 547 | 0x27bc, /* 82NM10 (NM10) */ |
| 548 | 0x27bd, /* 82801GHM (ICH7-M DH) */ |
| 549 | 0 |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 550 | }; |
| 551 | |
Damien Zammit | ef33e03 | 2015-11-14 01:03:39 +1100 | [diff] [blame] | 552 | static const struct pci_driver ich7_lpc __pci_driver = { |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 553 | .ops = &device_ops, |
| 554 | .vendor = PCI_VENDOR_ID_INTEL, |
Damien Zammit | ef33e03 | 2015-11-14 01:03:39 +1100 | [diff] [blame] | 555 | .devices = pci_device_ids, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 556 | }; |