Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <string.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | #include <cbmem.h> |
| 19 | #include <arch/cbfs.h> |
| 20 | #include <cbfs.h> |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 21 | #include <cf9_reset.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | #include <ip_checksum.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 23 | #include <memory_info.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 24 | #include <mrc_cache.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | #include <device/pci_def.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 26 | #include <device/dram/ddr3.h> |
| 27 | #include <smbios.h> |
| 28 | #include <spd.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 29 | #include <security/vboot/vboot_common.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 30 | #include <commonlib/region.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | #include "raminit.h" |
| 32 | #include "pei_data.h" |
| 33 | #include "haswell.h" |
| 34 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 35 | #define MRC_CACHE_VERSION 1 |
| 36 | |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 37 | void save_mrc_data(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 40 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 41 | pei_data->mrc_output, pei_data->mrc_output_len); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 45 | { |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 46 | struct region_device rdev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | |
| 48 | // preset just in case there is an error |
| 49 | pei_data->mrc_input = NULL; |
| 50 | pei_data->mrc_input_len = 0; |
| 51 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 52 | if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | /* error message printed in find_current_mrc_cache */ |
| 54 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 56 | pei_data->mrc_input = rdev_mmap_full(&rdev); |
| 57 | pei_data->mrc_input_len = region_device_sz(&rdev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 59 | printk(BIOS_DEBUG, "%s: at %p, size %x\n", |
| 60 | __func__, pei_data->mrc_input, pei_data->mrc_input_len); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | } |
| 62 | |
Elyes HAOUAS | 448d9fb | 2018-05-22 12:51:27 +0200 | [diff] [blame] | 63 | static const char *ecc_decoder[] = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | "inactive", |
| 65 | "active on IO", |
| 66 | "disabled on IO", |
| 67 | "active" |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Dump in the log memory controller configuration as read from the memory |
| 72 | * controller registers. |
| 73 | */ |
| 74 | static void report_memory_config(void) |
| 75 | { |
| 76 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 77 | int i; |
| 78 | |
| 79 | addr_decoder_common = MCHBAR32(0x5000); |
| 80 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 81 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 82 | |
| 83 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 84 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 85 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 86 | addr_decoder_common & 3, |
| 87 | (addr_decoder_common >> 2) & 3, |
| 88 | (addr_decoder_common >> 4) & 3); |
| 89 | |
| 90 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 91 | u32 ch_conf = addr_decode_ch[i]; |
| 92 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 93 | i, ch_conf); |
| 94 | printk(BIOS_DEBUG, " ECC %s\n", |
| 95 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 96 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 97 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 98 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 99 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 100 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | ((ch_conf >> 0) & 0xff) * 256, |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 102 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 104 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 105 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | ((ch_conf >> 8) & 0xff) * 256, |
Ryan Salsamendi | dab81a4 | 2017-06-30 17:36:41 -0700 | [diff] [blame] | 107 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 109 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | /** |
| 114 | * Find PEI executable in coreboot filesystem and execute it. |
| 115 | * |
| 116 | * @param pei_data: configuration data for UEFI PEI reference code |
| 117 | */ |
| 118 | void sdram_initialize(struct pei_data *pei_data) |
| 119 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | unsigned long entry; |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 121 | uint32_t type = CBFS_TYPE_MRC; |
| 122 | struct cbfsf f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 123 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 125 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | /* |
| 127 | * Do not pass MRC data in for recovery mode boot, |
| 128 | * Always pass it in for S3 resume. |
| 129 | */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 130 | if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 131 | prepare_mrc_cache(pei_data); |
| 132 | |
| 133 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 134 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 135 | post_code(POST_RESUME_FAILURE); |
| 136 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: " |
| 137 | "No MRC data\n"); |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 138 | system_reset(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /* Pass console handler in pei_data */ |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 142 | pei_data->tx_byte = do_putchar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 143 | |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 144 | /* |
| 145 | * Locate and call UEFI System Agent binary. The binary needs to be at |
| 146 | * a fixed offset in the flash and can therefore only reside in the |
| 147 | * COREBOOT fmap region |
| 148 | */ |
| 149 | if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) |
| 150 | die("mrc.bin not found!"); |
| 151 | /* We don't care about leaking the mapping */ |
| 152 | entry = (unsigned long)rdev_mmap_full(&f.data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | if (entry) { |
| 154 | int rv; |
| 155 | asm volatile ( |
| 156 | "call *%%ecx\n\t" |
| 157 | :"=a" (rv) : "c" (entry), "a" (pei_data)); |
| 158 | if (rv) { |
| 159 | switch (rv) { |
| 160 | case -1: |
| 161 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 162 | break; |
| 163 | case -2: |
| 164 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 165 | break; |
| 166 | default: |
| 167 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 168 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 169 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 170 | "Nonzero MRC return value.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 171 | } |
| 172 | } else { |
| 173 | die("UEFI PEI System Agent not found.\n"); |
| 174 | } |
| 175 | |
| 176 | /* For reference print the System Agent version |
| 177 | * after executing the UEFI PEI stage. |
| 178 | */ |
| 179 | u32 version = MCHBAR32(0x5034); |
| 180 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 181 | version >> 24, (version >> 16) & 0xff, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 182 | (version >> 8) & 0xff, version & 0xff); |
| 183 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | report_memory_config(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | } |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 186 | |
| 187 | void setup_sdram_meminfo(struct pei_data *pei_data) |
| 188 | { |
Elyes HAOUAS | ce83f31 | 2019-05-20 18:31:38 +0200 | [diff] [blame^] | 189 | u32 addr_decode_ch[2]; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 190 | struct memory_info* mem_info; |
| 191 | struct dimm_info *dimm; |
| 192 | int ddr_frequency; |
| 193 | int dimm_size; |
| 194 | int ch, d_num; |
| 195 | int dimm_cnt = 0; |
| 196 | |
| 197 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
Nico Huber | acac02d | 2017-06-20 14:49:04 +0200 | [diff] [blame] | 198 | if (!mem_info) |
| 199 | die("Failed to add memory info to CBMEM.\n"); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 200 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 201 | |
Elyes HAOUAS | ce83f31 | 2019-05-20 18:31:38 +0200 | [diff] [blame^] | 202 | /* FIXME: Do we need to read MCHBAR32(0x5000) ? */ |
| 203 | MCHBAR32(0x5000); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 204 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 205 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 206 | |
| 207 | ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100; |
| 208 | |
| 209 | for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { |
| 210 | u32 ch_conf = addr_decode_ch[ch]; |
| 211 | /* DIMMs A/B */ |
| 212 | for (d_num = 0; d_num < 2; d_num++) { |
| 213 | dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; |
| 214 | if (dimm_size) { |
| 215 | dimm = &mem_info->dimm[dimm_cnt]; |
| 216 | dimm->dimm_size = dimm_size; |
| 217 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 218 | dimm->ddr_frequency = ddr_frequency; |
| 219 | dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); |
| 220 | dimm->channel_num = ch; |
| 221 | dimm->dimm_num = d_num; |
| 222 | dimm->bank_locator = ch * 2; |
| 223 | memcpy(dimm->serial, |
| 224 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM], |
| 225 | SPD_DIMM_SERIAL_LEN); |
| 226 | memcpy(dimm->module_part_number, |
| 227 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM], |
| 228 | SPD_DIMM_PART_LEN); |
| 229 | dimm->mod_id = |
| 230 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | |
| 231 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xFF); |
| 232 | dimm->mod_type = SPD_SODIMM; |
| 233 | dimm->bus_width = 0x3; /* 64-bit */ |
| 234 | dimm_cnt++; |
| 235 | } |
| 236 | } |
| 237 | } |
| 238 | mem_info->dimm_cnt = dimm_cnt; |
| 239 | } |