Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <string.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | #include <arch/io.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include <cbmem.h> |
| 20 | #include <arch/cbfs.h> |
| 21 | #include <cbfs.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 22 | #include <halt.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <ip_checksum.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 24 | #include <memory_info.h> |
Alexander Couzens | 81c5c76 | 2016-03-09 03:13:45 +0100 | [diff] [blame] | 25 | #include <northbridge/intel/common/mrc_cache.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <device/pci_def.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 28 | #include <device/dram/ddr3.h> |
| 29 | #include <smbios.h> |
| 30 | #include <spd.h> |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 31 | #include <vboot/vboot_common.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | #include "raminit.h" |
| 33 | #include "pei_data.h" |
| 34 | #include "haswell.h" |
| 35 | |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 36 | void save_mrc_data(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | /* Save the MRC S3 restore data to cbmem */ |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 39 | store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 43 | { |
| 44 | struct mrc_data_container *mrc_cache; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | |
| 46 | // preset just in case there is an error |
| 47 | pei_data->mrc_input = NULL; |
| 48 | pei_data->mrc_input_len = 0; |
| 49 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | if ((mrc_cache = find_current_mrc_cache()) == NULL) { |
| 51 | /* error message printed in find_current_mrc_cache */ |
| 52 | return; |
| 53 | } |
| 54 | |
| 55 | pei_data->mrc_input = mrc_cache->mrc_data; |
| 56 | pei_data->mrc_input_len = mrc_cache->mrc_data_size; |
| 57 | |
| 58 | printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", |
| 59 | __func__, pei_data->mrc_input, |
| 60 | pei_data->mrc_input_len, mrc_cache->mrc_checksum); |
| 61 | } |
| 62 | |
| 63 | static const char* ecc_decoder[] = { |
| 64 | "inactive", |
| 65 | "active on IO", |
| 66 | "disabled on IO", |
| 67 | "active" |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Dump in the log memory controller configuration as read from the memory |
| 72 | * controller registers. |
| 73 | */ |
| 74 | static void report_memory_config(void) |
| 75 | { |
| 76 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 77 | int i; |
| 78 | |
| 79 | addr_decoder_common = MCHBAR32(0x5000); |
| 80 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 81 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 82 | |
| 83 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 84 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 85 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 86 | addr_decoder_common & 3, |
| 87 | (addr_decoder_common >> 2) & 3, |
| 88 | (addr_decoder_common >> 4) & 3); |
| 89 | |
| 90 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 91 | u32 ch_conf = addr_decode_ch[i]; |
| 92 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 93 | i, ch_conf); |
| 94 | printk(BIOS_DEBUG, " ECC %s\n", |
| 95 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 96 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 97 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 98 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 99 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 100 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | ((ch_conf >> 0) & 0xff) * 256, |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 102 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 104 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 105 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | ((ch_conf >> 8) & 0xff) * 256, |
Ryan Salsamendi | dab81a4 | 2017-06-30 17:36:41 -0700 | [diff] [blame^] | 107 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 109 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | /** |
| 114 | * Find PEI executable in coreboot filesystem and execute it. |
| 115 | * |
| 116 | * @param pei_data: configuration data for UEFI PEI reference code |
| 117 | */ |
| 118 | void sdram_initialize(struct pei_data *pei_data) |
| 119 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | unsigned long entry; |
| 121 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 123 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | /* |
| 125 | * Do not pass MRC data in for recovery mode boot, |
| 126 | * Always pass it in for S3 resume. |
| 127 | */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 128 | if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | prepare_mrc_cache(pei_data); |
| 130 | |
| 131 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 132 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 133 | post_code(POST_RESUME_FAILURE); |
| 134 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: " |
| 135 | "No MRC data\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 136 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 137 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | /* Pass console handler in pei_data */ |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 141 | pei_data->tx_byte = do_putchar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | |
| 143 | /* Locate and call UEFI System Agent binary. */ |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 144 | entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin", |
| 145 | CBFS_TYPE_MRC, NULL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | if (entry) { |
| 147 | int rv; |
| 148 | asm volatile ( |
| 149 | "call *%%ecx\n\t" |
| 150 | :"=a" (rv) : "c" (entry), "a" (pei_data)); |
| 151 | if (rv) { |
| 152 | switch (rv) { |
| 153 | case -1: |
| 154 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 155 | break; |
| 156 | case -2: |
| 157 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 158 | break; |
| 159 | default: |
| 160 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 161 | } |
| 162 | die("Nonzero MRC return value.\n"); |
| 163 | } |
| 164 | } else { |
| 165 | die("UEFI PEI System Agent not found.\n"); |
| 166 | } |
| 167 | |
| 168 | /* For reference print the System Agent version |
| 169 | * after executing the UEFI PEI stage. |
| 170 | */ |
| 171 | u32 version = MCHBAR32(0x5034); |
| 172 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
| 173 | version >> 24 , (version >> 16) & 0xff, |
| 174 | (version >> 8) & 0xff, version & 0xff); |
| 175 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 176 | report_memory_config(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 177 | } |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 178 | |
| 179 | void setup_sdram_meminfo(struct pei_data *pei_data) |
| 180 | { |
| 181 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 182 | struct memory_info* mem_info; |
| 183 | struct dimm_info *dimm; |
| 184 | int ddr_frequency; |
| 185 | int dimm_size; |
| 186 | int ch, d_num; |
| 187 | int dimm_cnt = 0; |
| 188 | |
| 189 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
Nico Huber | acac02d | 2017-06-20 14:49:04 +0200 | [diff] [blame] | 190 | if (!mem_info) |
| 191 | die("Failed to add memory info to CBMEM.\n"); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 192 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 193 | |
| 194 | addr_decoder_common = MCHBAR32(0x5000); |
| 195 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 196 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 197 | |
| 198 | ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100; |
| 199 | |
| 200 | for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { |
| 201 | u32 ch_conf = addr_decode_ch[ch]; |
| 202 | /* DIMMs A/B */ |
| 203 | for (d_num = 0; d_num < 2; d_num++) { |
| 204 | dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; |
| 205 | if (dimm_size) { |
| 206 | dimm = &mem_info->dimm[dimm_cnt]; |
| 207 | dimm->dimm_size = dimm_size; |
| 208 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 209 | dimm->ddr_frequency = ddr_frequency; |
| 210 | dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); |
| 211 | dimm->channel_num = ch; |
| 212 | dimm->dimm_num = d_num; |
| 213 | dimm->bank_locator = ch * 2; |
| 214 | memcpy(dimm->serial, |
| 215 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM], |
| 216 | SPD_DIMM_SERIAL_LEN); |
| 217 | memcpy(dimm->module_part_number, |
| 218 | &pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM], |
| 219 | SPD_DIMM_PART_LEN); |
| 220 | dimm->mod_id = |
| 221 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | |
| 222 | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xFF); |
| 223 | dimm->mod_type = SPD_SODIMM; |
| 224 | dimm->bus_width = 0x3; /* 64-bit */ |
| 225 | dimm_cnt++; |
| 226 | } |
| 227 | } |
| 228 | } |
| 229 | mem_info->dimm_cnt = dimm_cnt; |
| 230 | } |