Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <string.h> |
| 22 | #include <arch/hlt.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/romcc_io.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <arch/cbfs.h> |
| 27 | #include <cbfs.h> |
| 28 | #include <ip_checksum.h> |
| 29 | #include <pc80/mc146818rtc.h> |
| 30 | #include <device/pci_def.h> |
| 31 | #include "raminit.h" |
| 32 | #include "pei_data.h" |
| 33 | #include "haswell.h" |
| 34 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | #if CONFIG_CHROMEOS |
| 36 | #include <vendorcode/google/chromeos/chromeos.h> |
| 37 | #else |
| 38 | #define recovery_mode_enabled(x) 0 |
| 39 | #endif |
| 40 | |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame^] | 41 | void save_mrc_data(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | struct mrc_data_container *mrcdata; |
| 44 | int output_len = ALIGN(pei_data->mrc_output_len, 16); |
| 45 | |
| 46 | /* Save the MRC S3 restore data to cbmem */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | mrcdata = cbmem_add |
| 48 | (CBMEM_ID_MRCDATA, |
| 49 | output_len + sizeof(struct mrc_data_container)); |
| 50 | |
| 51 | printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", |
| 52 | pei_data->mrc_output, mrcdata, output_len); |
| 53 | |
| 54 | mrcdata->mrc_signature = MRC_DATA_SIGNATURE; |
| 55 | mrcdata->mrc_data_size = output_len; |
| 56 | mrcdata->reserved = 0; |
| 57 | memcpy(mrcdata->mrc_data, pei_data->mrc_output, |
| 58 | pei_data->mrc_output_len); |
| 59 | |
| 60 | /* Zero the unused space in aligned buffer. */ |
| 61 | if (output_len > pei_data->mrc_output_len) |
| 62 | memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, |
| 63 | output_len - pei_data->mrc_output_len); |
| 64 | |
| 65 | mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, |
| 66 | mrcdata->mrc_data_size); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 70 | { |
| 71 | struct mrc_data_container *mrc_cache; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 72 | |
| 73 | // preset just in case there is an error |
| 74 | pei_data->mrc_input = NULL; |
| 75 | pei_data->mrc_input_len = 0; |
| 76 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | if ((mrc_cache = find_current_mrc_cache()) == NULL) { |
| 78 | /* error message printed in find_current_mrc_cache */ |
| 79 | return; |
| 80 | } |
| 81 | |
| 82 | pei_data->mrc_input = mrc_cache->mrc_data; |
| 83 | pei_data->mrc_input_len = mrc_cache->mrc_data_size; |
| 84 | |
| 85 | printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", |
| 86 | __func__, pei_data->mrc_input, |
| 87 | pei_data->mrc_input_len, mrc_cache->mrc_checksum); |
| 88 | } |
| 89 | |
| 90 | static const char* ecc_decoder[] = { |
| 91 | "inactive", |
| 92 | "active on IO", |
| 93 | "disabled on IO", |
| 94 | "active" |
| 95 | }; |
| 96 | |
| 97 | /* |
| 98 | * Dump in the log memory controller configuration as read from the memory |
| 99 | * controller registers. |
| 100 | */ |
| 101 | static void report_memory_config(void) |
| 102 | { |
| 103 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 104 | int i; |
| 105 | |
| 106 | addr_decoder_common = MCHBAR32(0x5000); |
| 107 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 108 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 109 | |
| 110 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 111 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 112 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 113 | addr_decoder_common & 3, |
| 114 | (addr_decoder_common >> 2) & 3, |
| 115 | (addr_decoder_common >> 4) & 3); |
| 116 | |
| 117 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 118 | u32 ch_conf = addr_decode_ch[i]; |
| 119 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 120 | i, ch_conf); |
| 121 | printk(BIOS_DEBUG, " ECC %s\n", |
| 122 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 123 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 124 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 125 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 126 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 127 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 128 | ((ch_conf >> 0) & 0xff) * 256, |
| 129 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 130 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 131 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 132 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 133 | ((ch_conf >> 8) & 0xff) * 256, |
| 134 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 135 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 136 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | /** |
| 141 | * Find PEI executable in coreboot filesystem and execute it. |
| 142 | * |
| 143 | * @param pei_data: configuration data for UEFI PEI reference code |
| 144 | */ |
| 145 | void sdram_initialize(struct pei_data *pei_data) |
| 146 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | unsigned long entry; |
| 148 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 149 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 150 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | /* |
| 152 | * Do not pass MRC data in for recovery mode boot, |
| 153 | * Always pass it in for S3 resume. |
| 154 | */ |
| 155 | if (!recovery_mode_enabled() || pei_data->boot_mode == 2) |
| 156 | prepare_mrc_cache(pei_data); |
| 157 | |
| 158 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 159 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
| 160 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); |
| 161 | outb(0x6, 0xcf9); |
| 162 | while(1) { |
| 163 | hlt(); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* Pass console handler in pei_data */ |
| 168 | pei_data->tx_byte = console_tx_byte; |
| 169 | |
| 170 | /* Locate and call UEFI System Agent binary. */ |
| 171 | entry = (unsigned long)cbfs_get_file_content( |
| 172 | CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); |
| 173 | if (entry) { |
| 174 | int rv; |
| 175 | asm volatile ( |
| 176 | "call *%%ecx\n\t" |
| 177 | :"=a" (rv) : "c" (entry), "a" (pei_data)); |
| 178 | if (rv) { |
| 179 | switch (rv) { |
| 180 | case -1: |
| 181 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 182 | break; |
| 183 | case -2: |
| 184 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 185 | break; |
| 186 | default: |
| 187 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 188 | } |
| 189 | die("Nonzero MRC return value.\n"); |
| 190 | } |
| 191 | } else { |
| 192 | die("UEFI PEI System Agent not found.\n"); |
| 193 | } |
| 194 | |
| 195 | /* For reference print the System Agent version |
| 196 | * after executing the UEFI PEI stage. |
| 197 | */ |
| 198 | u32 version = MCHBAR32(0x5034); |
| 199 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
| 200 | version >> 24 , (version >> 16) & 0xff, |
| 201 | (version >> 8) & 0xff, version & 0xff); |
| 202 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 203 | report_memory_config(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | struct cbmem_entry *get_cbmem_toc(void) |
| 207 | { |
| 208 | return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); |
| 209 | } |
| 210 | |
| 211 | unsigned long get_top_of_ram(void) |
| 212 | { |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 213 | /* |
| 214 | * Base of TSEG is top of usable DRAM below 4GiB. The register has |
| 215 | * 1 MiB alignement. |
| 216 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 217 | u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 218 | return (unsigned long) tom & ~((1 << 20) - 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 219 | } |