Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 16 | #include <device/mmio.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 17 | #include <assert.h> |
| 18 | #include <device/pci_def.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 20 | #include <commonlib/helpers.h> |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 21 | #include <cpu/x86/mtrr.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 22 | #include <fast_spi_def.h> |
| 23 | #include <intelblocks/fast_spi.h> |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 24 | #include <lib.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
| 26 | #include <spi_flash.h> |
| 27 | #include <spi-generic.h> |
| 28 | #include <stdlib.h> |
| 29 | #include <string.h> |
| 30 | |
| 31 | /* |
| 32 | * Get the FAST_SPIBAR. |
| 33 | */ |
| 34 | void *fast_spi_get_bar(void) |
| 35 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 36 | #if defined(__SIMPLE_DEVICE__) |
| 37 | pci_devfn_t dev = PCH_DEV_SPI; |
| 38 | #else |
| 39 | struct device *dev = PCH_DEV_SPI; |
| 40 | #endif |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 41 | uintptr_t bar; |
| 42 | |
| 43 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 44 | assert(bar != 0); |
| 45 | /* |
| 46 | * Bits 31-12 are the base address as per EDS for SPI, |
| 47 | * Don't care about 0-11 bit |
| 48 | */ |
| 49 | return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
| 50 | } |
| 51 | |
| 52 | /* |
| 53 | * Disable the BIOS write protect and Enable Prefetching and Caching. |
| 54 | */ |
| 55 | void fast_spi_init(void) |
| 56 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 57 | #if defined(__SIMPLE_DEVICE__) |
| 58 | pci_devfn_t dev = PCH_DEV_SPI; |
| 59 | #else |
| 60 | struct device *dev = PCH_DEV_SPI; |
| 61 | #endif |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 62 | uint8_t bios_cntl; |
| 63 | |
| 64 | bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |
| 65 | |
| 66 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 67 | bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS; |
| 68 | bios_cntl |= SPIBAR_BIOS_CONTROL_WPD; |
| 69 | /* Enable Prefetching and caching. */ |
| 70 | bios_cntl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; |
| 71 | bios_cntl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; |
| 72 | |
| 73 | pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl); |
| 74 | } |
| 75 | |
| 76 | /* |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame] | 77 | * Set FAST_SPIBAR BIOS Control register based on input bit field. |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 78 | */ |
| 79 | static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) |
| 80 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 81 | #if defined(__SIMPLE_DEVICE__) |
| 82 | pci_devfn_t dev = PCH_DEV_SPI; |
| 83 | #else |
| 84 | struct device *dev = PCH_DEV_SPI; |
| 85 | #endif |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 86 | uint8_t bc_cntl; |
| 87 | |
| 88 | assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); |
| 89 | bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |
| 90 | bc_cntl |= bios_cntl_bit; |
| 91 | pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl); |
| 92 | } |
| 93 | |
| 94 | /* |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame] | 95 | * Ensure an additional read back after performing lock down |
| 96 | */ |
| 97 | static void fast_spi_read_post_write(uint8_t reg) |
| 98 | { |
| 99 | pci_read_config8(PCH_DEV_SPI, reg); |
| 100 | } |
| 101 | |
| 102 | /* |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 103 | * Set FAST_SPIBAR BIOS Control BILD bit. |
| 104 | */ |
| 105 | void fast_spi_set_bios_interface_lock_down(void) |
| 106 | { |
| 107 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame] | 108 | |
| 109 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Set FAST_SPIBAR BIOS Control LE bit. |
| 114 | */ |
| 115 | void fast_spi_set_lock_enable(void) |
| 116 | { |
| 117 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame] | 118 | |
| 119 | |
| 120 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /* |
| 124 | * Set FAST_SPIBAR BIOS Control EISS bit. |
| 125 | */ |
| 126 | void fast_spi_set_eiss(void) |
| 127 | { |
| 128 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame] | 129 | |
| 130 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | /* |
| 134 | * Set FAST_SPI opcode menu. |
| 135 | */ |
| 136 | void fast_spi_set_opcode_menu(void) |
| 137 | { |
| 138 | void *spibar = fast_spi_get_bar(); |
| 139 | |
| 140 | write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); |
| 141 | write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); |
| 142 | write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); |
| 143 | write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * Lock FAST_SPIBAR. |
Barnali Sarkar | 8e51319 | 2017-07-19 16:09:56 +0530 | [diff] [blame] | 148 | * Use 16bit write to avoid touching two upper bytes what may cause the write |
| 149 | * cycle to fail in case a prior transaction has not completed. |
| 150 | * While WRSDIS is lockable with FLOCKDN, writing both in the same |
| 151 | * cycle is guaranteed to work by design. |
| 152 | * |
| 153 | * Avoid read->modify->write not to clear RW1C bits unintentionally. |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 154 | */ |
| 155 | void fast_spi_lock_bar(void) |
| 156 | { |
| 157 | void *spibar = fast_spi_get_bar(); |
Duncan Laurie | dc1e6bc | 2017-08-15 13:32:26 -0700 | [diff] [blame] | 158 | uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN; |
| 159 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 160 | if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS)) |
Duncan Laurie | dc1e6bc | 2017-08-15 13:32:26 -0700 | [diff] [blame] | 161 | hsfs |= SPIBAR_HSFSTS_WRSDIS; |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 162 | |
Barnali Sarkar | 8e51319 | 2017-07-19 16:09:56 +0530 | [diff] [blame] | 163 | write16(spibar + SPIBAR_HSFSTS_CTL, hsfs); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | /* |
Barnali Sarkar | 4f6e341 | 2017-08-17 11:49:27 +0530 | [diff] [blame] | 167 | * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the |
| 168 | * FAST_SPI Protected Range (PR) registers. |
| 169 | */ |
| 170 | void fast_spi_pr_dlock(void) |
| 171 | { |
| 172 | void *spibar = fast_spi_get_bar(); |
| 173 | uint32_t dlock; |
| 174 | |
| 175 | dlock = read32(spibar + SPIBAR_DLOCK); |
| 176 | dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN |
| 177 | | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN |
| 178 | | SPIBAR_DLOCK_PR4LOCKDN); |
| 179 | |
| 180 | write32(spibar + SPIBAR_DLOCK, dlock); |
| 181 | } |
| 182 | |
| 183 | /* |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 184 | * Set FAST_SPIBAR Soft Reset Data Register value. |
| 185 | */ |
| 186 | void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) |
| 187 | { |
| 188 | void *spibar = fast_spi_get_bar(); |
| 189 | uint32_t ssl, ssms; |
| 190 | |
| 191 | /* Set Strap Lock Disable */ |
| 192 | ssl = read32(spibar + SPIBAR_RESET_LOCK); |
| 193 | ssl &= ~SPIBAR_RESET_LOCK_ENABLE; |
| 194 | write32(spibar + SPIBAR_RESET_LOCK, ssl); |
| 195 | |
| 196 | /* Write Soft Reset Data register at SPIBAR0 offset 0xF8[0:15] */ |
| 197 | write32(spibar + SPIBAR_RESET_DATA, soft_reset_data); |
| 198 | |
| 199 | /* Set Strap Mux Select set to '1' */ |
| 200 | ssms = read32(spibar + SPIBAR_RESET_CTRL); |
| 201 | ssms |= SPIBAR_RESET_CTRL_SSMC; |
| 202 | write32(spibar + SPIBAR_RESET_CTRL, ssms); |
| 203 | |
| 204 | /* Set Strap Lock Enable */ |
| 205 | ssl = read32(spibar + SPIBAR_RESET_LOCK); |
| 206 | ssl |= SPIBAR_RESET_LOCK_ENABLE; |
| 207 | write32(spibar + SPIBAR_RESET_LOCK, ssl); |
| 208 | } |
| 209 | |
| 210 | /* |
| 211 | * Returns bios_start and fills in size of the BIOS region. |
| 212 | */ |
| 213 | size_t fast_spi_get_bios_region(size_t *bios_size) |
| 214 | { |
| 215 | size_t bios_start, bios_end; |
| 216 | /* |
| 217 | * BIOS_BFPREG provides info about BIOS Flash Primary Region |
| 218 | * Base and Limit. |
| 219 | * Base and Limit fields are in units of 4KiB. |
| 220 | */ |
| 221 | uint32_t val = read32(fast_spi_get_bar() + SPIBAR_BFPREG); |
| 222 | |
| 223 | bios_start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; |
| 224 | bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> |
| 225 | SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB; |
| 226 | *bios_size = bios_end - bios_start; |
| 227 | return bios_start; |
| 228 | } |
| 229 | |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 230 | void fast_spi_cache_bios_region(void) |
| 231 | { |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 232 | size_t bios_size; |
| 233 | uint32_t alignment; |
Aaron Durbin | 0b34fc6 | 2017-06-08 10:52:58 -0500 | [diff] [blame] | 234 | const int type = MTRR_TYPE_WRPROT; |
| 235 | uintptr_t base; |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 236 | |
| 237 | /* Only the IFD BIOS region is memory mapped (at top of 4G) */ |
| 238 | fast_spi_get_bios_region(&bios_size); |
| 239 | |
| 240 | if (!bios_size) |
| 241 | return; |
| 242 | |
Lijian Zhao | ad1e49a | 2018-11-29 16:24:24 -0800 | [diff] [blame] | 243 | /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will |
| 244 | * cause memory type conflict when setting memory type to write |
| 245 | * protection, so limit the cached bios region to be no more than 16MB. |
| 246 | * */ |
| 247 | bios_size = MIN(bios_size, 16 * MiB); |
| 248 | |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 249 | /* Round to power of two */ |
Paul Menzel | 64e8340 | 2017-10-27 11:05:14 +0200 | [diff] [blame] | 250 | alignment = 1UL << (log2_ceil(bios_size)); |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 251 | bios_size = ALIGN_UP(bios_size, alignment); |
Aaron Durbin | 0b34fc6 | 2017-06-08 10:52:58 -0500 | [diff] [blame] | 252 | base = 4ULL*GiB - bios_size; |
| 253 | |
| 254 | if (ENV_RAMSTAGE) { |
| 255 | mtrr_use_temp_range(base, bios_size, type); |
| 256 | } else { |
| 257 | int mtrr = get_free_var_mtrr(); |
| 258 | |
| 259 | if (mtrr == -1) |
| 260 | return; |
| 261 | |
| 262 | set_var_mtrr(mtrr, base, bios_size, type); |
| 263 | } |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 264 | } |
| 265 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 266 | /* |
| 267 | * Program temporary BAR for SPI in case any of the stages before ramstage need |
| 268 | * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI |
| 269 | * enumeration. |
| 270 | */ |
| 271 | void fast_spi_early_init(uintptr_t spi_base_address) |
| 272 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 273 | #if defined(__SIMPLE_DEVICE__) |
| 274 | pci_devfn_t dev = PCH_DEV_SPI; |
| 275 | #else |
| 276 | struct device *dev = PCH_DEV_SPI; |
| 277 | #endif |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 278 | uint8_t pcireg; |
| 279 | |
| 280 | /* Assign Resources to SPI Controller */ |
| 281 | /* Clear BIT 1-2 SPI Command Register */ |
| 282 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 283 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 284 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 285 | |
| 286 | /* Program Temporary BAR for SPI */ |
| 287 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, |
| 288 | spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 289 | |
| 290 | /* Enable Bus Master and MMIO Space */ |
| 291 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 292 | pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 293 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 294 | |
| 295 | /* Initialize SPI to allow BIOS to write/erase on flash. */ |
| 296 | fast_spi_init(); |
| 297 | } |
Ravi Sarawadi | b051a9f5 | 2017-09-07 12:15:45 -0700 | [diff] [blame] | 298 | |
| 299 | /* Read SPI Write Protect disable status. */ |
| 300 | bool fast_spi_wpd_status(void) |
| 301 | { |
| 302 | return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) & |
| 303 | SPIBAR_BIOS_CONTROL_WPD; |
| 304 | } |
| 305 | |
| 306 | /* Enable SPI Write Protect. */ |
| 307 | void fast_spi_enable_wp(void) |
| 308 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 309 | #if defined(__SIMPLE_DEVICE__) |
| 310 | pci_devfn_t dev = PCH_DEV_SPI; |
| 311 | #else |
| 312 | struct device *dev = PCH_DEV_SPI; |
| 313 | #endif |
Ravi Sarawadi | b051a9f5 | 2017-09-07 12:15:45 -0700 | [diff] [blame] | 314 | uint8_t bios_cntl; |
| 315 | |
| 316 | bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |
| 317 | bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD; |
| 318 | pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl); |
| 319 | } |