soc/intel/skylake: Fix SPI WP disable status check
Use SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.
Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 078e0ae1..87cafb9 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -274,3 +274,21 @@
/* Initialize SPI to allow BIOS to write/erase on flash. */
fast_spi_init();
}
+
+/* Read SPI Write Protect disable status. */
+bool fast_spi_wpd_status(void)
+{
+ return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &
+ SPIBAR_BIOS_CONTROL_WPD;
+}
+
+/* Enable SPI Write Protect. */
+void fast_spi_enable_wp(void)
+{
+ device_t dev = PCH_DEV_SPI;
+ uint8_t bios_cntl;
+
+ bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+ bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;
+ pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
+}