Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <assert.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <commonlib/helpers.h> |
| 20 | #include <console/console.h> |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 21 | #include <cpu/x86/mtrr.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 22 | #include <fast_spi_def.h> |
| 23 | #include <intelblocks/fast_spi.h> |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 24 | #include <lib.h> |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 25 | #include <soc/intel/common/spi_flash.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <spi_flash.h> |
| 28 | #include <spi-generic.h> |
| 29 | #include <stdlib.h> |
| 30 | #include <string.h> |
| 31 | |
| 32 | /* |
| 33 | * Get the FAST_SPIBAR. |
| 34 | */ |
| 35 | void *fast_spi_get_bar(void) |
| 36 | { |
| 37 | device_t dev = PCH_DEV_SPI; |
| 38 | uintptr_t bar; |
| 39 | |
| 40 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 41 | assert(bar != 0); |
| 42 | /* |
| 43 | * Bits 31-12 are the base address as per EDS for SPI, |
| 44 | * Don't care about 0-11 bit |
| 45 | */ |
| 46 | return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
| 47 | } |
| 48 | |
| 49 | /* |
| 50 | * Disable the BIOS write protect and Enable Prefetching and Caching. |
| 51 | */ |
| 52 | void fast_spi_init(void) |
| 53 | { |
| 54 | device_t dev = PCH_DEV_SPI; |
| 55 | uint8_t bios_cntl; |
| 56 | |
| 57 | bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |
| 58 | |
| 59 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 60 | bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS; |
| 61 | bios_cntl |= SPIBAR_BIOS_CONTROL_WPD; |
| 62 | /* Enable Prefetching and caching. */ |
| 63 | bios_cntl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; |
| 64 | bios_cntl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; |
| 65 | |
| 66 | pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl); |
| 67 | } |
| 68 | |
| 69 | /* |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame^] | 70 | * Set FAST_SPIBAR BIOS Control register based on input bit field. |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 71 | */ |
| 72 | static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) |
| 73 | { |
| 74 | device_t dev = PCH_DEV_SPI; |
| 75 | uint8_t bc_cntl; |
| 76 | |
| 77 | assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); |
| 78 | bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |
| 79 | bc_cntl |= bios_cntl_bit; |
| 80 | pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl); |
| 81 | } |
| 82 | |
| 83 | /* |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame^] | 84 | * Ensure an additional read back after performing lock down |
| 85 | */ |
| 86 | static void fast_spi_read_post_write(uint8_t reg) |
| 87 | { |
| 88 | pci_read_config8(PCH_DEV_SPI, reg); |
| 89 | } |
| 90 | |
| 91 | /* |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 92 | * Set FAST_SPIBAR BIOS Control BILD bit. |
| 93 | */ |
| 94 | void fast_spi_set_bios_interface_lock_down(void) |
| 95 | { |
| 96 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame^] | 97 | |
| 98 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | /* |
| 102 | * Set FAST_SPIBAR BIOS Control LE bit. |
| 103 | */ |
| 104 | void fast_spi_set_lock_enable(void) |
| 105 | { |
| 106 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame^] | 107 | |
| 108 | |
| 109 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Set FAST_SPIBAR BIOS Control EISS bit. |
| 114 | */ |
| 115 | void fast_spi_set_eiss(void) |
| 116 | { |
| 117 | fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS); |
Subrata Banik | 8e39009 | 2017-07-21 10:06:17 +0530 | [diff] [blame^] | 118 | |
| 119 | fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* |
| 123 | * Set FAST_SPI opcode menu. |
| 124 | */ |
| 125 | void fast_spi_set_opcode_menu(void) |
| 126 | { |
| 127 | void *spibar = fast_spi_get_bar(); |
| 128 | |
| 129 | write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); |
| 130 | write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); |
| 131 | write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); |
| 132 | write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); |
| 133 | } |
| 134 | |
| 135 | /* |
| 136 | * Lock FAST_SPIBAR. |
| 137 | */ |
| 138 | void fast_spi_lock_bar(void) |
| 139 | { |
| 140 | void *spibar = fast_spi_get_bar(); |
| 141 | uint32_t hsfs; |
| 142 | |
| 143 | hsfs = read32(spibar + SPIBAR_HSFSTS_CTL); |
| 144 | hsfs |= SPIBAR_HSFSTS_FLOCKDN; |
| 145 | write32(spibar + SPIBAR_HSFSTS_CTL, hsfs); |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * Set FAST_SPIBAR Soft Reset Data Register value. |
| 150 | */ |
| 151 | void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) |
| 152 | { |
| 153 | void *spibar = fast_spi_get_bar(); |
| 154 | uint32_t ssl, ssms; |
| 155 | |
| 156 | /* Set Strap Lock Disable */ |
| 157 | ssl = read32(spibar + SPIBAR_RESET_LOCK); |
| 158 | ssl &= ~SPIBAR_RESET_LOCK_ENABLE; |
| 159 | write32(spibar + SPIBAR_RESET_LOCK, ssl); |
| 160 | |
| 161 | /* Write Soft Reset Data register at SPIBAR0 offset 0xF8[0:15] */ |
| 162 | write32(spibar + SPIBAR_RESET_DATA, soft_reset_data); |
| 163 | |
| 164 | /* Set Strap Mux Select set to '1' */ |
| 165 | ssms = read32(spibar + SPIBAR_RESET_CTRL); |
| 166 | ssms |= SPIBAR_RESET_CTRL_SSMC; |
| 167 | write32(spibar + SPIBAR_RESET_CTRL, ssms); |
| 168 | |
| 169 | /* Set Strap Lock Enable */ |
| 170 | ssl = read32(spibar + SPIBAR_RESET_LOCK); |
| 171 | ssl |= SPIBAR_RESET_LOCK_ENABLE; |
| 172 | write32(spibar + SPIBAR_RESET_LOCK, ssl); |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * Returns bios_start and fills in size of the BIOS region. |
| 177 | */ |
| 178 | size_t fast_spi_get_bios_region(size_t *bios_size) |
| 179 | { |
| 180 | size_t bios_start, bios_end; |
| 181 | /* |
| 182 | * BIOS_BFPREG provides info about BIOS Flash Primary Region |
| 183 | * Base and Limit. |
| 184 | * Base and Limit fields are in units of 4KiB. |
| 185 | */ |
| 186 | uint32_t val = read32(fast_spi_get_bar() + SPIBAR_BFPREG); |
| 187 | |
| 188 | bios_start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; |
| 189 | bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> |
| 190 | SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB; |
| 191 | *bios_size = bios_end - bios_start; |
| 192 | return bios_start; |
| 193 | } |
| 194 | |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 195 | void fast_spi_cache_bios_region(void) |
| 196 | { |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 197 | size_t bios_size; |
| 198 | uint32_t alignment; |
Aaron Durbin | 0b34fc6 | 2017-06-08 10:52:58 -0500 | [diff] [blame] | 199 | const int type = MTRR_TYPE_WRPROT; |
| 200 | uintptr_t base; |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 201 | |
| 202 | /* Only the IFD BIOS region is memory mapped (at top of 4G) */ |
| 203 | fast_spi_get_bios_region(&bios_size); |
| 204 | |
| 205 | if (!bios_size) |
| 206 | return; |
| 207 | |
| 208 | /* Round to power of two */ |
| 209 | alignment = 1 << (log2_ceil(bios_size)); |
| 210 | bios_size = ALIGN_UP(bios_size, alignment); |
Aaron Durbin | 0b34fc6 | 2017-06-08 10:52:58 -0500 | [diff] [blame] | 211 | base = 4ULL*GiB - bios_size; |
| 212 | |
| 213 | if (ENV_RAMSTAGE) { |
| 214 | mtrr_use_temp_range(base, bios_size, type); |
| 215 | } else { |
| 216 | int mtrr = get_free_var_mtrr(); |
| 217 | |
| 218 | if (mtrr == -1) |
| 219 | return; |
| 220 | |
| 221 | set_var_mtrr(mtrr, base, bios_size, type); |
| 222 | } |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 223 | } |
| 224 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 225 | /* |
| 226 | * Program temporary BAR for SPI in case any of the stages before ramstage need |
| 227 | * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI |
| 228 | * enumeration. |
| 229 | */ |
| 230 | void fast_spi_early_init(uintptr_t spi_base_address) |
| 231 | { |
| 232 | device_t dev = PCH_DEV_SPI; |
| 233 | uint8_t pcireg; |
| 234 | |
| 235 | /* Assign Resources to SPI Controller */ |
| 236 | /* Clear BIT 1-2 SPI Command Register */ |
| 237 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 238 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 239 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 240 | |
| 241 | /* Program Temporary BAR for SPI */ |
| 242 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, |
| 243 | spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 244 | |
| 245 | /* Enable Bus Master and MMIO Space */ |
| 246 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 247 | pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 248 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 249 | |
| 250 | /* Initialize SPI to allow BIOS to write/erase on flash. */ |
| 251 | fast_spi_init(); |
| 252 | } |