soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR
registers 0 to 4.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index f7ef685..078e0ae1 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -153,6 +153,23 @@
}
/*
+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
+ * FAST_SPI Protected Range (PR) registers.
+ */
+void fast_spi_pr_dlock(void)
+{
+ void *spibar = fast_spi_get_bar();
+ uint32_t dlock;
+
+ dlock = read32(spibar + SPIBAR_DLOCK);
+ dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN
+ | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN
+ | SPIBAR_DLOCK_PR4LOCKDN);
+
+ write32(spibar + SPIBAR_DLOCK, dlock);
+}
+
+/*
* Set FAST_SPIBAR Soft Reset Data Register value.
*/
void fast_spi_set_strap_msg_data(uint32_t soft_reset_data)