Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 2 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 6 | #include <acpi/acpi_pm.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 7 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 9 | #include <console/console.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 12 | #include <intelblocks/msr.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 13 | #include <intelblocks/pmclib.h> |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 14 | #include <intelblocks/rtc.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 15 | #include <intelblocks/tco.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 16 | #include <soc/iomap.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 17 | #include <soc/cpu.h> |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 18 | #include <soc/pci_devs.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 19 | #include <soc/pm.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 20 | #include <soc/smbus.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 21 | #include <security/vboot/vbnv.h> |
Elyes HAOUAS | add76f9 | 2019-03-21 09:55:49 +0100 | [diff] [blame] | 22 | |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 23 | #include "chip.h" |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 24 | |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 25 | uint8_t *pmc_mmio_regs(void) |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 26 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 27 | return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 28 | } |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 29 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 30 | uintptr_t soc_read_pmc_base(void) |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 31 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 32 | return (uintptr_t)pmc_mmio_regs(); |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 33 | } |
| 34 | |
Michael Niewöhner | b4d960b | 2019-11-02 12:14:06 +0100 | [diff] [blame] | 35 | uint32_t *soc_pmc_etr_addr(void) |
| 36 | { |
| 37 | return (uint32_t *)(soc_read_pmc_base() + ETR); |
| 38 | } |
| 39 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 40 | const char *const *soc_smi_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 41 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 42 | static const char *const smi_sts_bits[] = { |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 43 | [BIOS_STS_BIT] = "BIOS", |
| 44 | [LEGACY_USB_STS_BIT] = "LEGACY USB", |
| 45 | [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", |
| 46 | [APM_STS_BIT] = "APM", |
| 47 | [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", |
| 48 | [PM1_STS_BIT] = "PM1", |
Angel Pons | 81e9263 | 2021-02-19 16:02:45 +0100 | [diff] [blame] | 49 | [GPE0_STS_BIT] = "GPE0 (reserved)", |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 50 | [GPIO_STS_BIT] = "GPIO_SMI", |
| 51 | [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", |
| 52 | [MC_SMI_STS_BIT] = "MCSMI", |
| 53 | [TCO_STS_BIT] = "TCO", |
| 54 | [PERIODIC_STS_BIT] = "PERIODIC", |
| 55 | [SERIRQ_SMI_STS_BIT] = "SERIRQ", |
| 56 | [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", |
| 57 | [XHCI_SMI_STS_BIT] = "XHCI", |
Elyes Haouas | 7fd39ff | 2023-01-14 20:09:52 +0100 | [diff] [blame] | 58 | [HSMBUS_SMI_STS_BIT] = "HOST_SMBUS", |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 59 | [SCS_SMI_STS_BIT] = "SCS", |
| 60 | [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", |
| 61 | [SCC2_SMI_STS_BIT] = "SCC2", |
| 62 | [SPI_SSMI_STS_BIT] = "SPI_SSMI", |
| 63 | [SPI_SMI_STS_BIT] = "SPI", |
| 64 | [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 65 | }; |
| 66 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 67 | *a = ARRAY_SIZE(smi_sts_bits); |
| 68 | return smi_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 69 | } |
| 70 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 71 | /* |
| 72 | * For APL/GLK this check for power button status if nothing else |
| 73 | * is indicating an SMI and SMIs aren't turned into SCIs. |
| 74 | * Apparently, there is no PM1 status bit in the SMI status |
| 75 | * register. That makes things difficult for |
| 76 | * determining if the power button caused an SMI. |
| 77 | */ |
| 78 | uint32_t soc_get_smi_status(uint32_t generic_sts) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 79 | { |
Furquan Shaikh | 43810d9 | 2017-10-16 22:22:46 -0700 | [diff] [blame] | 80 | if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 81 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 82 | |
| 83 | /* Fake PM1 status bit if power button pressed. */ |
| 84 | if (pm1_sts & PWRBTN_STS) |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 85 | generic_sts |= (1 << PM1_STS_BIT); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 86 | } |
| 87 | |
Angel Pons | 81e9263 | 2021-02-19 16:02:45 +0100 | [diff] [blame] | 88 | /* |
| 89 | * GPE0_STS is reserved in APL/GLK datasheets. For compatibility |
| 90 | * with common code, mask it out so that it is always zero. |
| 91 | */ |
| 92 | return generic_sts & ~(1 << GPE0_STS_BIT); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 93 | } |
| 94 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 95 | const char *const *soc_tco_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 96 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 97 | static const char *const tco_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 98 | [3] = "TIMEOUT", |
| 99 | [17] = "SECOND_TO", |
| 100 | }; |
| 101 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 102 | *a = ARRAY_SIZE(tco_sts_bits); |
| 103 | return tco_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 104 | } |
| 105 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 106 | const char *const *soc_std_gpe_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 107 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 108 | static const char *const gpe_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 109 | [0] = "PCIE_SCI", |
| 110 | [2] = "SWGPE", |
| 111 | [3] = "PCIE_WAKE0", |
| 112 | [4] = "PUNIT", |
| 113 | [6] = "PCIE_WAKE1", |
| 114 | [7] = "PCIE_WAKE2", |
| 115 | [8] = "PCIE_WAKE3", |
| 116 | [9] = "PCI_EXP", |
| 117 | [10] = "BATLOW", |
| 118 | [11] = "CSE_PME", |
| 119 | [12] = "XDCI_PME", |
| 120 | [13] = "XHCI_PME", |
| 121 | [14] = "AVS_PME", |
| 122 | [15] = "GPIO_TIER1_SCI", |
| 123 | [16] = "SMB_WAK", |
| 124 | [17] = "SATA_PME", |
| 125 | }; |
| 126 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 127 | *a = ARRAY_SIZE(gpe_sts_bits); |
| 128 | return gpe_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 129 | } |
| 130 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 131 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
Duncan Laurie | 2e79009 | 2016-09-19 12:05:49 -0700 | [diff] [blame] | 132 | { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 133 | uint32_t gen_pmcon1; |
| 134 | |
Elyes Haouas | f12c2b0 | 2022-12-11 10:28:59 +0100 | [diff] [blame] | 135 | gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 136 | /* Clear the status bits. The RPS field is cleared on a 0 write. */ |
Elyes Haouas | f12c2b0 | 2022-12-11 10:28:59 +0100 | [diff] [blame] | 137 | write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 138 | } |
| 139 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 140 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 141 | { |
Aaron Durbin | e4d7abc | 2017-04-16 22:05:36 -0500 | [diff] [blame] | 142 | DEVTREE_CONST struct soc_intel_apollolake_config *config; |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 143 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 144 | config = config_of_soc(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 145 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 146 | /* Assign to out variable */ |
| 147 | *dw0 = config->gpe0_dw1; |
| 148 | *dw1 = config->gpe0_dw2; |
| 149 | *dw2 = config->gpe0_dw3; |
| 150 | } |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 151 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 152 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 153 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 154 | uintptr_t pmc_bar0 = soc_read_pmc_base(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 155 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 156 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 157 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
| 158 | |
Elyes Haouas | f12c2b0 | 2022-12-11 10:28:59 +0100 | [diff] [blame] | 159 | ps->prsts = read32p(pmc_bar0 + PRSTS); |
| 160 | ps->gen_pmcon1 = read32p(pmc_bar0 + GEN_PMCON1); |
| 161 | ps->gen_pmcon2 = read32p(pmc_bar0 + GEN_PMCON2); |
| 162 | ps->gen_pmcon3 = read32p(pmc_bar0 + GEN_PMCON3); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 163 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 164 | printk(BIOS_DEBUG, "prsts: %08x\n", |
| 165 | ps->prsts); |
| 166 | printk(BIOS_DEBUG, "tco_sts: %04x %04x\n", |
| 167 | ps->tco1_sts, ps->tco2_sts); |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 168 | printk(BIOS_DEBUG, |
| 169 | "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 170 | ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 171 | } |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 172 | |
Hannah Williams | cdecc0d | 2018-01-04 11:57:14 -0800 | [diff] [blame] | 173 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 174 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 175 | int prev_sleep_state) |
| 176 | { |
| 177 | /* WAK_STS bit will not be set when waking from G3 state */ |
| 178 | |
| 179 | if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS)) |
| 180 | prev_sleep_state = ACPI_S5; |
| 181 | return prev_sleep_state; |
| 182 | } |
| 183 | |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 184 | static int rtc_failed(uint32_t gen_pmcon1) |
| 185 | { |
| 186 | return !!(gen_pmcon1 & RPS); |
| 187 | } |
| 188 | |
| 189 | int soc_get_rtc_failed(void) |
| 190 | { |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 191 | const struct chipset_power_state *ps; |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 192 | |
Fabio Aiuto | fdcf698 | 2022-09-11 12:25:13 +0200 | [diff] [blame] | 193 | if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0) |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 194 | return 1; |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 195 | |
| 196 | return rtc_failed(ps->gen_pmcon1); |
| 197 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 198 | |
| 199 | int vbnv_cmos_failed(void) |
| 200 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 201 | uintptr_t pmc_bar = soc_read_pmc_base(); |
Elyes Haouas | f12c2b0 | 2022-12-11 10:28:59 +0100 | [diff] [blame] | 202 | uint32_t gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1); |
Furquan Shaikh | 9d07910 | 2018-02-02 15:11:29 -0800 | [diff] [blame] | 203 | int rtc_failure = rtc_failed(gen_pmcon1); |
| 204 | |
| 205 | if (rtc_failure) { |
| 206 | printk(BIOS_INFO, "RTC failed!\n"); |
| 207 | |
| 208 | /* We do not want to write 1 to clear-1 bits. Set them to 0. */ |
| 209 | gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS; |
| 210 | |
| 211 | /* RPS is write 0 to clear. */ |
| 212 | gen_pmcon1 &= ~RPS; |
| 213 | |
Elyes Haouas | f12c2b0 | 2022-12-11 10:28:59 +0100 | [diff] [blame] | 214 | write32p(pmc_bar + GEN_PMCON1, gen_pmcon1); |
Furquan Shaikh | 9d07910 | 2018-02-02 15:11:29 -0800 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | return rtc_failure; |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 218 | } |
Eugene Myers | ebc8423 | 2020-01-21 16:46:16 -0500 | [diff] [blame] | 219 | |
| 220 | /* STM Support */ |
| 221 | uint16_t get_pmbase(void) |
| 222 | { |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 223 | return (uint16_t)ACPI_BASE_ADDRESS; |
Eugene Myers | ebc8423 | 2020-01-21 16:46:16 -0500 | [diff] [blame] | 224 | } |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 225 | |
Sean Rhodes | 3b56cff | 2023-05-03 21:15:24 +0100 | [diff] [blame] | 226 | /* Set which power state system will be after reapplying the power (from G3 State) */ |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 227 | void pmc_soc_set_afterg3_en(const bool on) |
| 228 | { |
Sean Rhodes | 3b56cff | 2023-05-03 21:15:24 +0100 | [diff] [blame] | 229 | uint8_t reg8; |
| 230 | uint8_t *const pmcbase = pmc_mmio_regs(); |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 231 | |
Sean Rhodes | 3b56cff | 2023-05-03 21:15:24 +0100 | [diff] [blame] | 232 | reg8 = read8(pmcbase + GEN_PMCON_A); |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 233 | if (on) |
Sean Rhodes | 3b56cff | 2023-05-03 21:15:24 +0100 | [diff] [blame] | 234 | reg8 &= ~SLEEP_AFTER_POWER_FAIL; |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 235 | else |
Sean Rhodes | 3b56cff | 2023-05-03 21:15:24 +0100 | [diff] [blame] | 236 | reg8 |= SLEEP_AFTER_POWER_FAIL; |
| 237 | write8(pmcbase + GEN_PMCON_A, reg8); |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 238 | } |