Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <boot/tables.h> |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 6 | #include <cbmem.h> |
Angel Pons | b9bbed2 | 2020-08-03 15:11:55 +0200 | [diff] [blame] | 7 | #include <commonlib/helpers.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 9 | #include <cpu/cpu.h> |
Arthur Heymans | 98c9257 | 2022-11-07 11:39:58 +0100 | [diff] [blame] | 10 | #include <cpu/intel/speedstep.h> |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 11 | #include <cpu/intel/smm_reloc.h> |
Arthur Heymans | f06e993 | 2023-07-05 08:25:55 +0200 | [diff] [blame] | 12 | #include <cpu/x86/smm.h> |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 13 | #include <device/device.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 14 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 15 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | #include <stdint.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 17 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | #include "chip.h" |
| 19 | #include "gm45.h" |
| 20 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 21 | static uint64_t get_touud(void) |
| 22 | { |
| 23 | uint64_t touud = pci_read_config16(__pci_0_00_0, D0F0_TOUUD); |
| 24 | touud <<= 20; |
| 25 | return touud; |
| 26 | } |
| 27 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 28 | static void mch_domain_read_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 29 | { |
| 30 | u64 tom, touud; |
Arthur Heymans | f06e993 | 2023-07-05 08:25:55 +0200 | [diff] [blame] | 31 | u32 tolud; |
Kyösti Mälkki | c1d4d0b | 2021-06-26 19:09:05 +0300 | [diff] [blame] | 32 | int idx = 3; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 33 | |
| 34 | /* Total Memory 2GB example: |
| 35 | * |
| 36 | * 00000000 0000MB-2014MB 2014MB RAM (writeback) |
| 37 | * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) |
| 38 | * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) |
| 39 | * 80000000 2048MB TOLUD |
| 40 | * 80000000 2048MB TOM |
| 41 | * |
| 42 | * Total Memory 4GB example: |
| 43 | * |
| 44 | * 00000000 0000MB-3038MB 3038MB RAM (writeback) |
| 45 | * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) |
| 46 | * be000000 3040MB-3072MB 32MB GFX UMA (uncached) |
| 47 | * be000000 3072MB TOLUD |
| 48 | * 100000000 4096MB TOM |
| 49 | * 100000000 4096MB-5120MB 1024MB RAM (writeback) |
| 50 | * 140000000 5120MB TOUUD |
| 51 | */ |
| 52 | |
| 53 | pci_domain_read_resources(dev); |
| 54 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 55 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 56 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 57 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 58 | touud = get_touud(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 59 | |
| 60 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 61 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 62 | tolud <<= 16; |
| 63 | |
| 64 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 65 | tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 66 | tom <<= 27; |
| 67 | |
| 68 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 69 | touud, tolud, tom); |
| 70 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 71 | /* Report lowest memory region */ |
Arthur Heymans | f06e993 | 2023-07-05 08:25:55 +0200 | [diff] [blame] | 72 | ram_range(dev, idx++, 0, 0xa0000); |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * Reserve everything between A segment and 1MB: |
| 76 | * |
| 77 | * 0xa0000 - 0xbffff: Legacy VGA |
| 78 | * 0xc0000 - 0xfffff: RAM |
| 79 | */ |
Arthur Heymans | f06e993 | 2023-07-05 08:25:55 +0200 | [diff] [blame] | 80 | mmio_from_to(dev, idx++, 0xa0000, 0xc0000); |
| 81 | reserved_ram_from_to(dev, idx++, 0xc0000, 1*MiB); |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 82 | |
| 83 | /* Report < 4GB memory */ |
Arthur Heymans | f06e993 | 2023-07-05 08:25:55 +0200 | [diff] [blame] | 84 | ram_range(dev, idx++, 1*MiB, (uintptr_t)cbmem_top()); |
| 85 | |
| 86 | /* TSEG */ |
| 87 | uintptr_t tseg_base; |
| 88 | size_t tseg_size; |
| 89 | smm_region(&tseg_base, &tseg_size); |
| 90 | mmio_range(dev, idx++, tseg_base, tseg_size); |
| 91 | |
| 92 | /* cbmem_top can be shifted downwards due to alignment. |
| 93 | Mark the region between cbmem_top and tseg_base as unusable */ |
| 94 | if ((uintptr_t)cbmem_top() < tseg_base) { |
| 95 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n", |
| 96 | tseg_base - (uintptr_t)cbmem_top()); |
| 97 | mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base); |
| 98 | } |
| 99 | |
| 100 | /* graphic memory above TSEG */ |
| 101 | if (tseg_base + tseg_size < tolud) |
| 102 | mmio_from_to(dev, idx++, tseg_base + tseg_size, tolud); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 106 | * is remapped above TOM, TOUUD will account for both |
| 107 | */ |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 108 | upper_ram_end(dev, idx++, touud); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 109 | |
Kyösti Mälkki | c1d4d0b | 2021-06-26 19:09:05 +0300 | [diff] [blame] | 110 | mmconf_resource(dev, idx++); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 111 | } |
| 112 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 113 | static void mch_domain_set_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 114 | { |
| 115 | struct resource *resource; |
| 116 | int i; |
| 117 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 118 | for (i = 3; i <= 9; ++i) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 119 | /* Report read resources. */ |
Vladimir Serbinenko | 40412c6 | 2014-11-12 00:09:20 +0100 | [diff] [blame] | 120 | resource = probe_resource(dev, i); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 121 | if (resource) |
| 122 | report_resource_stored(dev, resource, ""); |
| 123 | } |
| 124 | |
Arthur Heymans | 7fcd4d5 | 2023-08-24 15:12:19 +0200 | [diff] [blame] | 125 | assign_resources(dev->downstream); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 126 | } |
| 127 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 128 | static void mch_domain_init(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 129 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 130 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 131 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 132 | /* Enable SERR */ |
Elyes HAOUAS | 5ac723e | 2020-04-29 09:09:12 +0200 | [diff] [blame] | 133 | pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 134 | } |
| 135 | |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 136 | static const char *northbridge_acpi_name(const struct device *dev) |
| 137 | { |
| 138 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 139 | return "PCI0"; |
| 140 | |
Fabio Aiuto | 61ed4ef | 2022-09-30 14:55:53 +0200 | [diff] [blame] | 141 | if (!is_pci_dev_on_bus(dev, 0)) |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 142 | return NULL; |
| 143 | |
| 144 | switch (dev->path.pci.devfn) { |
| 145 | case PCI_DEVFN(0, 0): |
| 146 | return "MCHC"; |
| 147 | } |
| 148 | |
| 149 | return NULL; |
| 150 | } |
| 151 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 152 | void northbridge_write_smram(u8 smram) |
| 153 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 154 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 155 | |
Elyes Haouas | 5e6b0f0 | 2022-09-13 09:55:49 +0200 | [diff] [blame] | 156 | if (!dev) |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 157 | die("could not find pci 00:00.0!\n"); |
| 158 | |
| 159 | pci_write_config8(dev, D0F0_SMRAM, smram); |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 160 | } |
| 161 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 162 | static void set_above_4g_pci(const struct device *dev) |
| 163 | { |
| 164 | const uint64_t touud = get_touud(); |
| 165 | const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; |
| 166 | |
| 167 | const char *scope = acpi_device_path(dev); |
| 168 | acpigen_write_scope(scope); |
| 169 | acpigen_write_name_qword("A4GB", touud); |
| 170 | acpigen_write_name_qword("A4GS", len); |
| 171 | acpigen_pop_len(); |
| 172 | |
| 173 | printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); |
| 174 | } |
| 175 | |
| 176 | static void pci_domain_ssdt(const struct device *dev) |
| 177 | { |
| 178 | generate_cpu_entries(dev); |
| 179 | set_above_4g_pci(dev); |
| 180 | } |
| 181 | |
Arthur Heymans | 2fb6f68 | 2022-11-07 09:45:19 +0100 | [diff] [blame] | 182 | struct device_operations gm45_pci_domain_ops = { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 183 | .read_resources = mch_domain_read_resources, |
| 184 | .set_resources = mch_domain_set_resources, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 185 | .init = mch_domain_init, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 186 | .scan_bus = pci_host_bridge_scan_bus, |
Vladimir Serbinenko | 33769a5 | 2014-08-30 22:39:20 +0200 | [diff] [blame] | 187 | .write_acpi_tables = northbridge_write_acpi_tables, |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 188 | .acpi_fill_ssdt = pci_domain_ssdt, |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 189 | .acpi_name = northbridge_acpi_name, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 190 | }; |
| 191 | |
Arthur Heymans | 2fb6f68 | 2022-11-07 09:45:19 +0100 | [diff] [blame] | 192 | struct device_operations gm45_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 193 | .read_resources = noop_read_resources, |
| 194 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 195 | .init = mp_cpu_bus_init, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 196 | }; |
| 197 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 198 | static void gm45_init(void *const chip_info) |
| 199 | { |
| 200 | int dev, fn, bit_base; |
| 201 | |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 202 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 203 | |
| 204 | /* Hide internal functions based on devicetree info. */ |
| 205 | for (dev = 3; dev > 0; --dev) { |
| 206 | switch (dev) { |
| 207 | case 3: /* ME */ |
| 208 | fn = 3; |
| 209 | bit_base = 6; |
| 210 | break; |
| 211 | case 2: /* IGD */ |
| 212 | fn = 1; |
| 213 | bit_base = 3; |
| 214 | break; |
| 215 | case 1: /* PEG */ |
| 216 | fn = 0; |
| 217 | bit_base = 1; |
| 218 | break; |
| 219 | } |
| 220 | for (; fn >= 0; --fn) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 221 | const struct device *const d = pcidev_on_root(dev, fn); |
| 222 | if (!d || d->enabled) |
| 223 | continue; |
| 224 | /* FIXME: Using bitwise ops changes the binary */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 225 | pci_write_config32(d0f0, D0F0_DEVEN, |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 226 | pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
| 230 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 231 | if (!(deven & (0xf << 6))) |
| 232 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 233 | } |
| 234 | |
| 235 | struct chip_operations northbridge_intel_gm45_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame] | 236 | .name = "Intel GM45 Northbridge", |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 237 | .init = gm45_init, |
| 238 | }; |
Arthur Heymans | 98c9257 | 2022-11-07 11:39:58 +0100 | [diff] [blame] | 239 | |
| 240 | bool northbridge_support_slfm(void) |
| 241 | { |
| 242 | struct device *gmch = __pci_0_00_0; |
| 243 | struct northbridge_intel_gm45_config *config = gmch->chip_info; |
| 244 | return config->slfm == 1; |
| 245 | } |