cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 31e3de4..c6fa0e0 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -7,6 +7,7 @@
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/cpu.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/intel/smm_reloc.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -257,3 +258,10 @@
CHIP_NAME("Intel GM45 Northbridge")
.init = gm45_init,
};
+
+bool northbridge_support_slfm(void)
+{
+ struct device *gmch = __pci_0_00_0;
+ struct northbridge_intel_gm45_config *config = gmch->chip_info;
+ return config->slfm == 1;
+}