nb/intel: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index cd64dfe..b3dbe16 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -178,14 +178,10 @@
static void mch_domain_init(struct device *dev)
{
- u32 reg32;
-
struct device *mch = pcidev_on_root(0, 0);
/* Enable SERR */
- reg32 = pci_read_config32(mch, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(mch, PCI_COMMAND, reg32);
+ pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR);
}
static const char *northbridge_acpi_name(const struct device *dev)