Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
Duncan Laurie | 73ff0fb | 2017-04-10 21:07:06 -0700 | [diff] [blame] | 4 | register "deep_s3_enable_ac" = "0" |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # FSP Configuration |
| 25 | register "ProbelessTrace" = "0" |
| 26 | register "EnableLan" = "0" |
| 27 | register "EnableSata" = "0" |
| 28 | register "SataSalpSupport" = "0" |
| 29 | register "SataMode" = "0" |
| 30 | register "SataPortsEnable[0]" = "0" |
| 31 | register "EnableAzalia" = "1" |
| 32 | register "DspEnable" = "1" |
| 33 | register "IoBufferOwnership" = "3" |
| 34 | register "EnableTraceHub" = "0" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 35 | register "SsicPortEnable" = "0" |
| 36 | register "SmbusEnable" = "1" |
| 37 | register "Cio2Enable" = "0" |
| 38 | register "ScsEmmcEnabled" = "1" |
| 39 | register "ScsEmmcHs400Enabled" = "1" |
| 40 | register "ScsSdCardEnabled" = "0" |
| 41 | register "IshEnable" = "0" |
| 42 | register "PttSwitch" = "0" |
| 43 | register "InternalGfx" = "1" |
| 44 | register "SkipExtGfxScan" = "1" |
| 45 | register "Device4Enable" = "1" |
| 46 | register "HeciEnabled" = "0" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 47 | register "SaGv" = "3" |
| 48 | register "SerialIrqConfigSirqEnable" = "1" |
| 49 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 50 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 51 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 52 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 53 | register "PmTimerDisabled" = "1" |
Duncan Laurie | d60b493 | 2017-11-01 13:23:45 -0700 | [diff] [blame] | 54 | register "VmxEnable" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 55 | |
| 56 | register "pirqa_routing" = "PCH_IRQ11" |
| 57 | register "pirqb_routing" = "PCH_IRQ10" |
| 58 | register "pirqc_routing" = "PCH_IRQ11" |
| 59 | register "pirqd_routing" = "PCH_IRQ11" |
| 60 | register "pirqe_routing" = "PCH_IRQ11" |
| 61 | register "pirqf_routing" = "PCH_IRQ11" |
| 62 | register "pirqg_routing" = "PCH_IRQ11" |
| 63 | register "pirqh_routing" = "PCH_IRQ11" |
| 64 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 65 | # VR Settings Configuration for 4 Domains |
| 66 | #+----------------+-------+-------+-------+-------+ |
| 67 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 68 | #+----------------+-------+-------+-------+-------+ |
| 69 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 70 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 71 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 72 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 73 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 74 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 75 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 76 | #| IccMax | 4A | 24A | 24A | 24A | |
| 77 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 78 | #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | |
| 79 | #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 80 | #+----------------+-------+-------+-------+-------+ |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 81 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 82 | .vr_config_enable = 1, |
| 83 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 84 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 85 | .psi3threshold = VR_CFG_AMP(1), |
| 86 | .psi3enable = 1, |
| 87 | .psi4enable = 1, |
| 88 | .imon_slope = 0x0, |
| 89 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 90 | .icc_max = VR_CFG_AMP(4), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 91 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 92 | .ac_loadline = 1490, |
| 93 | .dc_loadline = 1420, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 94 | }" |
| 95 | |
| 96 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 97 | .vr_config_enable = 1, |
| 98 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 99 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 100 | .psi3threshold = VR_CFG_AMP(1), |
| 101 | .psi3enable = 1, |
| 102 | .psi4enable = 1, |
| 103 | .imon_slope = 0x0, |
| 104 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 105 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 106 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 107 | .ac_loadline = 500, |
| 108 | .dc_loadline = 486, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 109 | }" |
| 110 | |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 111 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 112 | .vr_config_enable = 1, |
| 113 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 114 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 115 | .psi3threshold = VR_CFG_AMP(1), |
| 116 | .psi3enable = 1, |
| 117 | .psi4enable = 1, |
| 118 | .imon_slope = 0x0, |
| 119 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 120 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 121 | .voltage_limit = 1520, |
Duncan Laurie | 57e9e3b | 2017-03-14 16:42:33 -0700 | [diff] [blame] | 122 | .ac_loadline = 570, |
| 123 | .dc_loadline = 420, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 124 | }" |
| 125 | |
| 126 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 127 | .vr_config_enable = 1, |
| 128 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 129 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 130 | .psi3threshold = VR_CFG_AMP(1), |
| 131 | .psi3enable = 1, |
| 132 | .psi4enable = 1, |
| 133 | .imon_slope = 0x0, |
| 134 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 135 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 136 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 137 | .ac_loadline = 457, |
| 138 | .dc_loadline = 430, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 139 | }" |
| 140 | |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 141 | # Enable Root port 1 with SRCCLKREQ1# |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 142 | register "PcieRpEnable[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 143 | register "PcieRpClkReqSupport[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 144 | register "PcieRpClkReqNumber[0]" = "1" |
Furquan Shaikh | ebd67c2 | 2017-09-18 14:21:48 -0700 | [diff] [blame] | 145 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 146 | register "PcieRpLtrEnable[0]" = "1" |
Duncan Laurie | 25874b8 | 2018-01-29 12:02:41 -0800 | [diff] [blame] | 147 | register "PcieRpHotPlug[0]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 148 | #RP 1 uses CLK SRC 1 |
| 149 | register "PcieRpClkSrcNumber[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 150 | |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 151 | # Enable Root port 5 with SRCCLKREQ4# |
| 152 | register "PcieRpEnable[4]" = "1" |
| 153 | register "PcieRpClkReqSupport[4]" = "1" |
| 154 | register "PcieRpClkReqNumber[4]" = "4" |
Furquan Shaikh | ebd67c2 | 2017-09-18 14:21:48 -0700 | [diff] [blame] | 155 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 156 | register "PcieRpLtrEnable[4]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 157 | #RP 5 uses CLK SRC 4 |
| 158 | register "PcieRpClkSrcNumber[4]" = "4" |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 159 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 160 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 |
| 161 | register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 162 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 163 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 164 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 165 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 166 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 167 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 168 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 169 | register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty |
| 170 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 171 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame^] | 172 | # Intel Common SoC Config |
| 173 | #+-------------------+---------------------------+ |
| 174 | #| Field | Value | |
| 175 | #+-------------------+---------------------------+ |
| 176 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 177 | #| I2C0 | Touchscreen | |
| 178 | #| I2C1 | Early TPM access | |
| 179 | #| I2C2 | Touchpad | |
| 180 | #| I2C4 | Audio | |
| 181 | #+-------------------+---------------------------+ |
| 182 | register "common_soc_config" = "{ |
| 183 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 184 | .i2c[0] = { |
| 185 | .speed = I2C_SPEED_FAST_PLUS, |
| 186 | .rise_time_ns = 98, |
| 187 | .fall_time_ns = 38, |
| 188 | }, |
| 189 | .i2c[1] = { |
| 190 | .early_init = 1, |
| 191 | .speed = I2C_SPEED_FAST, |
| 192 | .rise_time_ns = 112, |
| 193 | .fall_time_ns = 34, |
| 194 | }, |
| 195 | .i2c[2] = { |
| 196 | .speed = I2C_SPEED_FAST, |
| 197 | .speed_config[0] = { |
| 198 | .speed = I2C_SPEED_FAST, |
| 199 | .scl_lcnt = 186, |
| 200 | .scl_hcnt = 93, |
| 201 | .sda_hold = 36, |
| 202 | } |
| 203 | }, |
| 204 | .i2c[4] = { |
| 205 | .speed = I2C_SPEED_FAST, |
| 206 | .speed_config[0] = { |
| 207 | .speed = I2C_SPEED_FAST, |
| 208 | .scl_lcnt = 176, |
| 209 | .scl_hcnt = 95, |
| 210 | .sda_hold = 36, |
| 211 | } |
| 212 | }, |
| 213 | }" |
| 214 | |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 215 | # Touchscreen |
| 216 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 217 | |
| 218 | # Enable I2C1 bus early for TPM access |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 219 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 220 | |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 221 | # Touchpad |
| 222 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 223 | |
| 224 | # Audio |
| 225 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 226 | |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 227 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 228 | register "SerialIoDevMode" = "{ |
| 229 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 230 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 231 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Duncan Laurie | 93eb8c4 | 2016-12-12 10:43:45 -0800 | [diff] [blame] | 232 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 233 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 234 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 235 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Duncan Laurie | c5eab98 | 2017-05-16 19:06:04 -0700 | [diff] [blame] | 236 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Duncan Laurie | e49b866 | 2017-04-13 01:40:53 -0700 | [diff] [blame] | 237 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 238 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 239 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 240 | }" |
| 241 | |
| 242 | register "speed_shift_enable" = "1" |
| 243 | register "dptf_enable" = "1" |
Duncan Laurie | 07a597f | 2017-05-26 15:55:04 -0700 | [diff] [blame] | 244 | register "tdp_pl2_override" = "15" |
Duncan Laurie | 690831d | 2016-12-16 08:01:09 -0800 | [diff] [blame] | 245 | register "tcc_offset" = "10" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 246 | |
| 247 | device cpu_cluster 0 on |
| 248 | device lapic 0 on end |
| 249 | end |
| 250 | device domain 0 on |
| 251 | device pci 00.0 on end # Host Bridge |
| 252 | device pci 02.0 on end # Integrated Graphics Device |
Duncan Laurie | 283b01d | 2018-05-07 15:39:37 -0700 | [diff] [blame] | 253 | device pci 14.0 on |
| 254 | chip drivers/usb/acpi |
| 255 | register "desc" = ""Root Hub"" |
| 256 | register "type" = "UPC_TYPE_HUB" |
| 257 | device usb 0.0 on |
| 258 | chip drivers/usb/acpi |
| 259 | register "desc" = ""USB2 Type-C Left"" |
| 260 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 261 | device usb 2.0 on end |
| 262 | end |
| 263 | chip drivers/usb/acpi |
| 264 | register "desc" = ""USB2 Camera"" |
| 265 | register "type" = "UPC_TYPE_INTERNAL" |
| 266 | device usb 2.1 on end |
| 267 | end |
| 268 | chip drivers/usb/acpi |
| 269 | register "desc" = ""USB2 Bluetooth"" |
| 270 | register "type" = "UPC_TYPE_INTERNAL" |
| 271 | device usb 2.2 on end |
| 272 | end |
| 273 | chip drivers/usb/acpi |
| 274 | register "desc" = ""USB2 Type-C Right"" |
| 275 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 276 | device usb 2.4 on end |
| 277 | end |
| 278 | chip drivers/usb/acpi |
| 279 | register "desc" = ""USB2 H1 TPM"" |
| 280 | register "type" = "UPC_TYPE_INTERNAL" |
| 281 | device usb 2.6 on end |
| 282 | end |
| 283 | chip drivers/usb/acpi |
| 284 | register "desc" = ""USB3 Type-C Left"" |
| 285 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 286 | device usb 3.0 on end |
| 287 | end |
| 288 | chip drivers/usb/acpi |
| 289 | register "desc" = ""USB3 Type-C Right"" |
| 290 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 291 | device usb 3.1 on end |
| 292 | end |
| 293 | end |
| 294 | end |
| 295 | end # USB xHCI |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 296 | device pci 14.1 off end # USB xDCI (OTG) |
| 297 | device pci 14.2 on end # Thermal Subsystem |
| 298 | device pci 15.0 on |
Furquan Shaikh | 5360c7e | 2017-02-19 01:18:09 -0800 | [diff] [blame] | 299 | chip drivers/i2c/hid |
| 300 | register "generic.hid" = ""WCOM50C1"" |
| 301 | register "generic.desc" = ""WCOM Digitizer"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 302 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
Duncan Laurie | 658a6dc | 2017-02-17 17:27:51 -0800 | [diff] [blame] | 303 | register "generic.speed" = "I2C_SPEED_FAST_PLUS" |
Duncan Laurie | 2d14021 | 2016-12-15 18:51:29 -0800 | [diff] [blame] | 304 | register "hid_desc_reg_offset" = "0x1" |
| 305 | device i2c 0a on end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 306 | end |
| 307 | end # I2C #0 |
| 308 | device pci 15.1 on |
| 309 | chip drivers/i2c/tpm |
| 310 | register "hid" = ""GOOG0005"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 311 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 312 | device i2c 50 on end |
| 313 | end |
| 314 | end # I2C #1 |
| 315 | device pci 15.2 on |
Wei-Ning Huang | 267e4a5 | 2017-04-24 18:53:22 +0800 | [diff] [blame] | 316 | chip drivers/i2c/hid |
| 317 | register "generic.hid" = ""ACPI0C50"" |
| 318 | register "generic.desc" = ""Touchpad"" |
| 319 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" |
| 320 | register "hid_desc_reg_offset" = "0x1" |
Duncan Laurie | 2d14021 | 2016-12-15 18:51:29 -0800 | [diff] [blame] | 321 | device i2c 49 on end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 322 | end |
Wei-Ning Huang | 267e4a5 | 2017-04-24 18:53:22 +0800 | [diff] [blame] | 323 | chip drivers/i2c/generic |
| 324 | register "hid" = ""GOOG0008"" |
| 325 | register "desc" = ""Touchpad EC Interface"" |
| 326 | device i2c 1e on end |
| 327 | end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 328 | end # I2C #2 |
Duncan Laurie | 93eb8c4 | 2016-12-12 10:43:45 -0800 | [diff] [blame] | 329 | device pci 15.3 off end # I2C #3 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 330 | device pci 16.0 on end # Management Engine Interface 1 |
| 331 | device pci 16.1 off end # Management Engine Interface 2 |
| 332 | device pci 16.2 off end # Management Engine IDE-R |
| 333 | device pci 16.3 off end # Management Engine KT Redirection |
| 334 | device pci 16.4 off end # Management Engine Interface 3 |
| 335 | device pci 17.0 off end # SATA |
| 336 | device pci 19.0 on end # UART #2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 337 | device pci 19.1 off end # I2C #5 |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 338 | device pci 19.2 on |
| 339 | chip drivers/i2c/max98927 |
| 340 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 341 | register "vmon_slot_no" = "4" |
| 342 | register "imon_slot_no" = "5" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 343 | register "uid" = "0" |
| 344 | register "desc" = ""Right Speaker Amp"" |
| 345 | register "name" = ""MAXR"" |
| 346 | device i2c 39 on end |
| 347 | end |
| 348 | chip drivers/i2c/max98927 |
| 349 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 350 | register "vmon_slot_no" = "6" |
| 351 | register "imon_slot_no" = "7" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 352 | register "uid" = "1" |
| 353 | register "desc" = ""Left Speaker Amp"" |
| 354 | register "name" = ""MAXL"" |
| 355 | device i2c 3a on end |
| 356 | end |
Duncan Laurie | f8e4eb8 | 2017-08-10 18:42:08 -0700 | [diff] [blame] | 357 | chip drivers/i2c/rt5663 |
Harsha Priya | ad12610 | 2018-05-02 14:39:29 -0700 | [diff] [blame] | 358 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(GPP_D9)" |
Duncan Laurie | f8e4eb8 | 2017-08-10 18:42:08 -0700 | [diff] [blame] | 359 | register "dc_offset_l_manual" = "0xffd160" |
| 360 | register "dc_offset_r_manual" = "0xffd1c0" |
| 361 | register "dc_offset_l_manual_mic" = "0xff8a10" |
| 362 | register "dc_offset_r_manual_mic" = "0xff8ab0" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 363 | device i2c 13 on end |
| 364 | end |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 365 | chip drivers/i2c/generic |
| 366 | register "hid" = ""10EC5514"" |
| 367 | register "name" = ""RT54"" |
| 368 | register "desc" = ""Realtek RT5514"" |
Cheng-Yi Chiang | 09ab157 | 2017-11-01 15:01:34 +0800 | [diff] [blame] | 369 | register "property_count" = "3" |
Duncan Laurie | f10c8f9 | 2017-08-29 08:36:55 -0700 | [diff] [blame] | 370 | # Set the DMIC initial delay to 16ms to avoid pop noise |
| 371 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 372 | register "property_list[0].name" = ""realtek,dmic-init-delay"" |
| 373 | register "property_list[0].integer" = "16" |
Cheng-Yi Chiang | 09ab157 | 2017-11-01 15:01:34 +0800 | [diff] [blame] | 374 | # Set clock name for RT5514 to calibrate DSP clock. |
| 375 | register "property_list[1].type" = "ACPI_DP_TYPE_STRING" |
| 376 | register "property_list[1].name" = ""realtek,dsp-calib-clk-name"" |
| 377 | register "property_list[1].string" = ""ssp1_mclk"" |
| 378 | # Set clock rate for RT5514 to calibrate DSP clock. |
| 379 | register "property_list[2].type" = "ACPI_DP_TYPE_INTEGER" |
| 380 | register "property_list[2].name" = ""realtek,dsp-calib-clk-rate"" |
| 381 | register "property_list[2].integer" = "24000000" |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 382 | device i2c 57 on end |
| 383 | end |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 384 | end # I2C #4 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 385 | device pci 1c.0 on |
| 386 | chip drivers/intel/wifi |
| 387 | register "wake" = "GPE0_PCI_EXP" |
| 388 | device pci 00.0 on end |
| 389 | end |
| 390 | end # PCI Express Port 1 |
| 391 | device pci 1c.1 off end # PCI Express Port 2 |
| 392 | device pci 1c.2 off end # PCI Express Port 3 |
| 393 | device pci 1c.3 off end # PCI Express Port 4 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 394 | device pci 1c.4 on end # PCI Express Port 5 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 395 | device pci 1c.5 off end # PCI Express Port 6 |
| 396 | device pci 1c.6 off end # PCI Express Port 7 |
| 397 | device pci 1c.7 off end # PCI Express Port 8 |
| 398 | device pci 1d.0 off end # PCI Express Port 9 |
| 399 | device pci 1d.1 off end # PCI Express Port 10 |
| 400 | device pci 1d.2 off end # PCI Express Port 11 |
| 401 | device pci 1d.3 off end # PCI Express Port 12 |
| 402 | device pci 1e.0 on end # UART #0 |
| 403 | device pci 1e.1 off end # UART #1 |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 404 | device pci 1e.2 on |
| 405 | chip drivers/spi/acpi |
| 406 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 407 | register "compat_string" = ""realtek,rt5514"" |
Duncan Laurie | 9692f31 | 2017-06-30 02:01:02 -0700 | [diff] [blame] | 408 | register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F10_IRQ)" |
Duncan Laurie | 37da884 | 2017-09-27 03:45:53 -0700 | [diff] [blame] | 409 | register "speed" = "12 * MHz" |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 410 | device spi 0 on end |
| 411 | end |
| 412 | end # GSPI #0 |
Duncan Laurie | c5eab98 | 2017-05-16 19:06:04 -0700 | [diff] [blame] | 413 | device pci 1e.3 off end # GSPI #1 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 414 | device pci 1e.4 on end # eMMC |
| 415 | device pci 1e.5 off end # SDIO |
| 416 | device pci 1e.6 off end # SDCard |
| 417 | device pci 1f.0 on |
| 418 | chip ec/google/chromeec |
| 419 | device pnp 0c09.0 on end |
| 420 | end |
| 421 | end # LPC Interface |
| 422 | device pci 1f.1 on end # P2SB |
| 423 | device pci 1f.2 on end # Power Management Controller |
| 424 | device pci 1f.3 on end # Intel HDA |
| 425 | device pci 1f.4 on end # SMBus |
| 426 | device pci 1f.5 on end # PCH SPI |
| 427 | device pci 1f.6 off end # GbE |
| 428 | end |
| 429 | end |