commit e49b866c7cd67202853cd6e2177a294b9ab0c056
author Duncan Laurie <dlaurie@chromium.org> Thu Apr 13 01:40:53 2017 -0700
committer Duncan Laurie <dlaurie@chromium.org> Fri Apr 14 04:21:37 2017 +0200
tree 164f12761d23c7f431e931545c26a6bb6acfd18d
parent 30783d84cffcb5a997e8d0f4061e3a7962b6417c

mainboard/google/eve: Set UART0 to skip initialization in FSP

Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.

Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.

BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.

Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19264
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/eve/devicetree.cb

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 7db97b7..99ddb2e 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -204,7 +204,7 @@
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
 		[PchSerialIoIndexSpi1]  = PchSerialIoPci,
-		[PchSerialIoIndexUart0] = PchSerialIoPci,
+		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"