Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
Duncan Laurie | 73ff0fb | 2017-04-10 21:07:06 -0700 | [diff] [blame] | 4 | register "deep_s3_enable_ac" = "0" |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # FSP Configuration |
| 25 | register "ProbelessTrace" = "0" |
| 26 | register "EnableLan" = "0" |
| 27 | register "EnableSata" = "0" |
| 28 | register "SataSalpSupport" = "0" |
| 29 | register "SataMode" = "0" |
| 30 | register "SataPortsEnable[0]" = "0" |
| 31 | register "EnableAzalia" = "1" |
| 32 | register "DspEnable" = "1" |
| 33 | register "IoBufferOwnership" = "3" |
| 34 | register "EnableTraceHub" = "0" |
| 35 | register "XdciEnable" = "0" |
| 36 | register "SsicPortEnable" = "0" |
| 37 | register "SmbusEnable" = "1" |
| 38 | register "Cio2Enable" = "0" |
| 39 | register "ScsEmmcEnabled" = "1" |
| 40 | register "ScsEmmcHs400Enabled" = "1" |
| 41 | register "ScsSdCardEnabled" = "0" |
| 42 | register "IshEnable" = "0" |
| 43 | register "PttSwitch" = "0" |
| 44 | register "InternalGfx" = "1" |
| 45 | register "SkipExtGfxScan" = "1" |
| 46 | register "Device4Enable" = "1" |
| 47 | register "HeciEnabled" = "0" |
| 48 | register "FspSkipMpInit" = "1" |
| 49 | register "SaGv" = "3" |
| 50 | register "SerialIrqConfigSirqEnable" = "1" |
| 51 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 52 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 53 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 54 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 55 | register "PmTimerDisabled" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 56 | |
| 57 | register "pirqa_routing" = "PCH_IRQ11" |
| 58 | register "pirqb_routing" = "PCH_IRQ10" |
| 59 | register "pirqc_routing" = "PCH_IRQ11" |
| 60 | register "pirqd_routing" = "PCH_IRQ11" |
| 61 | register "pirqe_routing" = "PCH_IRQ11" |
| 62 | register "pirqf_routing" = "PCH_IRQ11" |
| 63 | register "pirqg_routing" = "PCH_IRQ11" |
| 64 | register "pirqh_routing" = "PCH_IRQ11" |
| 65 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 66 | # VR Settings Configuration for 4 Domains |
| 67 | #+----------------+-------+-------+-------+-------+ |
| 68 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 69 | #+----------------+-------+-------+-------+-------+ |
| 70 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 71 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 72 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 73 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 74 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 75 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 76 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 77 | #| IccMax | 4A | 24A | 24A | 24A | |
| 78 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 79 | #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | |
| 80 | #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 81 | #+----------------+-------+-------+-------+-------+ |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 82 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 83 | .vr_config_enable = 1, |
| 84 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 85 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 86 | .psi3threshold = VR_CFG_AMP(1), |
| 87 | .psi3enable = 1, |
| 88 | .psi4enable = 1, |
| 89 | .imon_slope = 0x0, |
| 90 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 91 | .icc_max = VR_CFG_AMP(4), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 92 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 93 | .ac_loadline = 1490, |
| 94 | .dc_loadline = 1420, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 95 | }" |
| 96 | |
| 97 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 98 | .vr_config_enable = 1, |
| 99 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 100 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 101 | .psi3threshold = VR_CFG_AMP(1), |
| 102 | .psi3enable = 1, |
| 103 | .psi4enable = 1, |
| 104 | .imon_slope = 0x0, |
| 105 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 106 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 107 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 108 | .ac_loadline = 500, |
| 109 | .dc_loadline = 486, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 110 | }" |
| 111 | |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 112 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 113 | .vr_config_enable = 1, |
| 114 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 115 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 116 | .psi3threshold = VR_CFG_AMP(1), |
| 117 | .psi3enable = 1, |
| 118 | .psi4enable = 1, |
| 119 | .imon_slope = 0x0, |
| 120 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 121 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 122 | .voltage_limit = 1520, |
Duncan Laurie | 57e9e3b | 2017-03-14 16:42:33 -0700 | [diff] [blame] | 123 | .ac_loadline = 570, |
| 124 | .dc_loadline = 420, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 125 | }" |
| 126 | |
| 127 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 128 | .vr_config_enable = 1, |
| 129 | .psi1threshold = VR_CFG_AMP(20), |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 130 | .psi2threshold = VR_CFG_AMP(2), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 131 | .psi3threshold = VR_CFG_AMP(1), |
| 132 | .psi3enable = 1, |
| 133 | .psi4enable = 1, |
| 134 | .imon_slope = 0x0, |
| 135 | .imon_offset = 0x0, |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 136 | .icc_max = VR_CFG_AMP(24), |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 137 | .voltage_limit = 1520, |
V Sowmya | 41f9373 | 2017-05-23 14:17:01 +0530 | [diff] [blame] | 138 | .ac_loadline = 457, |
| 139 | .dc_loadline = 430, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 140 | }" |
| 141 | |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 142 | # Enable Root port 1 with SRCCLKREQ1# |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 143 | register "PcieRpEnable[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 144 | register "PcieRpClkReqSupport[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 145 | register "PcieRpClkReqNumber[0]" = "1" |
Furquan Shaikh | ebd67c2 | 2017-09-18 14:21:48 -0700 | [diff] [blame^] | 146 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 147 | register "PcieRpLtrEnable[0]" = "1" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 148 | |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 149 | # Enable Root port 5 with SRCCLKREQ4# |
| 150 | register "PcieRpEnable[4]" = "1" |
| 151 | register "PcieRpClkReqSupport[4]" = "1" |
| 152 | register "PcieRpClkReqNumber[4]" = "4" |
Furquan Shaikh | ebd67c2 | 2017-09-18 14:21:48 -0700 | [diff] [blame^] | 153 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 154 | register "PcieRpLtrEnable[4]" = "1" |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 155 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 156 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 |
| 157 | register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 158 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 159 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 160 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 161 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 162 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 163 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 164 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 165 | register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty |
| 166 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 167 | |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 168 | # Touchscreen |
| 169 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 170 | register "i2c[0]" = "{ |
| 171 | .speed = I2C_SPEED_FAST_PLUS, |
Duncan Laurie | 92dde2f | 2017-04-07 02:03:45 -0700 | [diff] [blame] | 172 | .rise_time_ns = 98, |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 173 | .fall_time_ns = 38, |
| 174 | }" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 175 | |
| 176 | # Enable I2C1 bus early for TPM access |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 177 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
Duncan Laurie | c86fa6d | 2017-02-17 17:26:04 -0800 | [diff] [blame] | 178 | register "i2c[1]" = "{ |
| 179 | .early_init = 1, |
| 180 | .speed = I2C_SPEED_FAST, |
Duncan Laurie | 92dde2f | 2017-04-07 02:03:45 -0700 | [diff] [blame] | 181 | .rise_time_ns = 112, |
| 182 | .fall_time_ns = 34, |
Duncan Laurie | c86fa6d | 2017-02-17 17:26:04 -0800 | [diff] [blame] | 183 | }" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 184 | |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 185 | # Touchpad |
| 186 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
| 187 | register "i2c[2]" = "{ |
| 188 | .speed = I2C_SPEED_FAST, |
Duncan Laurie | 4f7d536 | 2017-05-16 19:04:16 -0700 | [diff] [blame] | 189 | .speed_config[0] = { |
| 190 | .speed = I2C_SPEED_FAST, |
| 191 | .scl_lcnt = 186, |
| 192 | .scl_hcnt = 93, |
| 193 | .sda_hold = 36, |
| 194 | } |
Duncan Laurie | d4d6ba1 | 2017-02-24 12:28:12 -0800 | [diff] [blame] | 195 | }" |
| 196 | |
| 197 | # Audio |
| 198 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| 199 | register "i2c[4]" = "{ |
| 200 | .speed = I2C_SPEED_FAST, |
| 201 | .rise_time_ns = 240, |
| 202 | .fall_time_ns = 30, |
| 203 | }" |
| 204 | |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 205 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 206 | register "SerialIoDevMode" = "{ |
| 207 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 208 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 209 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Duncan Laurie | 93eb8c4 | 2016-12-12 10:43:45 -0800 | [diff] [blame] | 210 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 211 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 212 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 213 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Duncan Laurie | c5eab98 | 2017-05-16 19:06:04 -0700 | [diff] [blame] | 214 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Duncan Laurie | e49b866 | 2017-04-13 01:40:53 -0700 | [diff] [blame] | 215 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 216 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 217 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 218 | }" |
| 219 | |
| 220 | register "speed_shift_enable" = "1" |
| 221 | register "dptf_enable" = "1" |
Duncan Laurie | 07a597f | 2017-05-26 15:55:04 -0700 | [diff] [blame] | 222 | register "tdp_pl2_override" = "15" |
Duncan Laurie | 690831d | 2016-12-16 08:01:09 -0800 | [diff] [blame] | 223 | register "tcc_offset" = "10" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 224 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 225 | # Lock Down |
| 226 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 227 | |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 228 | device cpu_cluster 0 on |
| 229 | device lapic 0 on end |
| 230 | end |
| 231 | device domain 0 on |
| 232 | device pci 00.0 on end # Host Bridge |
| 233 | device pci 02.0 on end # Integrated Graphics Device |
| 234 | device pci 14.0 on end # USB xHCI |
| 235 | device pci 14.1 off end # USB xDCI (OTG) |
| 236 | device pci 14.2 on end # Thermal Subsystem |
| 237 | device pci 15.0 on |
Furquan Shaikh | 5360c7e | 2017-02-19 01:18:09 -0800 | [diff] [blame] | 238 | chip drivers/i2c/hid |
| 239 | register "generic.hid" = ""WCOM50C1"" |
| 240 | register "generic.desc" = ""WCOM Digitizer"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 241 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
Duncan Laurie | 658a6dc | 2017-02-17 17:27:51 -0800 | [diff] [blame] | 242 | register "generic.speed" = "I2C_SPEED_FAST_PLUS" |
Duncan Laurie | 2d14021 | 2016-12-15 18:51:29 -0800 | [diff] [blame] | 243 | register "hid_desc_reg_offset" = "0x1" |
| 244 | device i2c 0a on end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 245 | end |
| 246 | end # I2C #0 |
| 247 | device pci 15.1 on |
| 248 | chip drivers/i2c/tpm |
| 249 | register "hid" = ""GOOG0005"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 250 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 251 | device i2c 50 on end |
| 252 | end |
| 253 | end # I2C #1 |
| 254 | device pci 15.2 on |
Wei-Ning Huang | 267e4a5 | 2017-04-24 18:53:22 +0800 | [diff] [blame] | 255 | chip drivers/i2c/hid |
| 256 | register "generic.hid" = ""ACPI0C50"" |
| 257 | register "generic.desc" = ""Touchpad"" |
| 258 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" |
| 259 | register "hid_desc_reg_offset" = "0x1" |
Duncan Laurie | 2d14021 | 2016-12-15 18:51:29 -0800 | [diff] [blame] | 260 | device i2c 49 on end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 261 | end |
Wei-Ning Huang | 267e4a5 | 2017-04-24 18:53:22 +0800 | [diff] [blame] | 262 | chip drivers/i2c/generic |
| 263 | register "hid" = ""GOOG0008"" |
| 264 | register "desc" = ""Touchpad EC Interface"" |
| 265 | device i2c 1e on end |
| 266 | end |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 267 | end # I2C #2 |
Duncan Laurie | 93eb8c4 | 2016-12-12 10:43:45 -0800 | [diff] [blame] | 268 | device pci 15.3 off end # I2C #3 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 269 | device pci 16.0 on end # Management Engine Interface 1 |
| 270 | device pci 16.1 off end # Management Engine Interface 2 |
| 271 | device pci 16.2 off end # Management Engine IDE-R |
| 272 | device pci 16.3 off end # Management Engine KT Redirection |
| 273 | device pci 16.4 off end # Management Engine Interface 3 |
| 274 | device pci 17.0 off end # SATA |
| 275 | device pci 19.0 on end # UART #2 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 276 | device pci 19.1 off end # I2C #5 |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 277 | device pci 19.2 on |
| 278 | chip drivers/i2c/max98927 |
| 279 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 280 | register "vmon_slot_no" = "4" |
| 281 | register "imon_slot_no" = "5" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 282 | register "uid" = "0" |
| 283 | register "desc" = ""Right Speaker Amp"" |
| 284 | register "name" = ""MAXR"" |
| 285 | device i2c 39 on end |
| 286 | end |
| 287 | chip drivers/i2c/max98927 |
| 288 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 289 | register "vmon_slot_no" = "6" |
| 290 | register "imon_slot_no" = "7" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 291 | register "uid" = "1" |
| 292 | register "desc" = ""Left Speaker Amp"" |
| 293 | register "name" = ""MAXL"" |
| 294 | device i2c 3a on end |
| 295 | end |
Duncan Laurie | f8e4eb8 | 2017-08-10 18:42:08 -0700 | [diff] [blame] | 296 | chip drivers/i2c/rt5663 |
Duncan Laurie | 887e793 | 2017-03-15 11:34:04 -0700 | [diff] [blame] | 297 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
Duncan Laurie | f8e4eb8 | 2017-08-10 18:42:08 -0700 | [diff] [blame] | 298 | register "dc_offset_l_manual" = "0xffd160" |
| 299 | register "dc_offset_r_manual" = "0xffd1c0" |
| 300 | register "dc_offset_l_manual_mic" = "0xff8a10" |
| 301 | register "dc_offset_r_manual_mic" = "0xff8ab0" |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 302 | device i2c 13 on end |
| 303 | end |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 304 | chip drivers/i2c/generic |
| 305 | register "hid" = ""10EC5514"" |
| 306 | register "name" = ""RT54"" |
| 307 | register "desc" = ""Realtek RT5514"" |
Duncan Laurie | f10c8f9 | 2017-08-29 08:36:55 -0700 | [diff] [blame] | 308 | register "property_count" = "1" |
| 309 | # Set the DMIC initial delay to 16ms to avoid pop noise |
| 310 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 311 | register "property_list[0].name" = ""realtek,dmic-init-delay"" |
| 312 | register "property_list[0].integer" = "16" |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 313 | device i2c 57 on end |
| 314 | end |
Duncan Laurie | 5492bfb5 | 2017-02-17 17:40:10 -0800 | [diff] [blame] | 315 | end # I2C #4 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 316 | device pci 1c.0 on |
| 317 | chip drivers/intel/wifi |
| 318 | register "wake" = "GPE0_PCI_EXP" |
| 319 | device pci 00.0 on end |
| 320 | end |
| 321 | end # PCI Express Port 1 |
| 322 | device pci 1c.1 off end # PCI Express Port 2 |
| 323 | device pci 1c.2 off end # PCI Express Port 3 |
| 324 | device pci 1c.3 off end # PCI Express Port 4 |
Duncan Laurie | 949e34c | 2017-01-21 19:11:37 -0800 | [diff] [blame] | 325 | device pci 1c.4 on end # PCI Express Port 5 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 326 | device pci 1c.5 off end # PCI Express Port 6 |
| 327 | device pci 1c.6 off end # PCI Express Port 7 |
| 328 | device pci 1c.7 off end # PCI Express Port 8 |
| 329 | device pci 1d.0 off end # PCI Express Port 9 |
| 330 | device pci 1d.1 off end # PCI Express Port 10 |
| 331 | device pci 1d.2 off end # PCI Express Port 11 |
| 332 | device pci 1d.3 off end # PCI Express Port 12 |
| 333 | device pci 1e.0 on end # UART #0 |
| 334 | device pci 1e.1 off end # UART #1 |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 335 | device pci 1e.2 on |
| 336 | chip drivers/spi/acpi |
| 337 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 338 | register "compat_string" = ""realtek,rt5514"" |
Duncan Laurie | 9692f31 | 2017-06-30 02:01:02 -0700 | [diff] [blame] | 339 | register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F10_IRQ)" |
Duncan Laurie | 2661a9f | 2017-03-02 10:15:23 -0800 | [diff] [blame] | 340 | device spi 0 on end |
| 341 | end |
| 342 | end # GSPI #0 |
Duncan Laurie | c5eab98 | 2017-05-16 19:06:04 -0700 | [diff] [blame] | 343 | device pci 1e.3 off end # GSPI #1 |
Duncan Laurie | 81485d2 | 2016-10-28 09:13:52 -0700 | [diff] [blame] | 344 | device pci 1e.4 on end # eMMC |
| 345 | device pci 1e.5 off end # SDIO |
| 346 | device pci 1e.6 off end # SDCard |
| 347 | device pci 1f.0 on |
| 348 | chip ec/google/chromeec |
| 349 | device pnp 0c09.0 on end |
| 350 | end |
| 351 | end # LPC Interface |
| 352 | device pci 1f.1 on end # P2SB |
| 353 | device pci 1f.2 on end # Power Management Controller |
| 354 | device pci 1f.3 on end # Intel HDA |
| 355 | device pci 1f.4 on end # SMBus |
| 356 | device pci 1f.5 on end # PCH SPI |
| 357 | device pci 1f.6 off end # GbE |
| 358 | end |
| 359 | end |