Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | 5daa1d3 | 2020-06-14 12:01:58 +0300 | [diff] [blame] | 3 | #include <acpi/acpi_gnvs.h> |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 9 | #include <device/mmio.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 10 | #include <soc/adsp.h> |
| 11 | #include <soc/device_nvs.h> |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 12 | #include <soc/device_nvs.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 13 | #include <soc/pch.h> |
| 14 | #include <soc/ramstage.h> |
| 15 | #include <soc/rcba.h> |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 16 | #include <soc/intel/broadwell/pch/chip.h> |
Angel Pons | c423ce2 | 2021-04-19 16:13:31 +0200 | [diff] [blame^] | 17 | #include <southbridge/intel/lynxpoint/iobp.h> |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 18 | |
| 19 | static void adsp_init(struct device *dev) |
| 20 | { |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 21 | const struct soc_intel_broadwell_pch_config *config = config_of(dev); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 22 | struct resource *bar0, *bar1; |
| 23 | u32 tmp32; |
| 24 | |
| 25 | /* Ensure memory and bus master are enabled */ |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 26 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 27 | |
| 28 | /* Find BAR0 and BAR1 */ |
| 29 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 30 | if (!bar0) |
| 31 | return; |
| 32 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 33 | if (!bar1) |
| 34 | return; |
| 35 | |
| 36 | /* |
| 37 | * Set LTR value in DSP shim LTR control register to 3ms |
| 38 | * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h |
| 39 | */ |
| 40 | tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 41 | write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0), |
| 42 | ADSP_SHIM_LTRC_VALUE); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 43 | |
| 44 | /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ |
| 45 | pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); |
| 46 | |
| 47 | /* Program ADSP IOBP VDLDAT1 to 0x040100 */ |
| 48 | pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); |
| 49 | |
| 50 | /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ |
| 51 | tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 52 | if (pch_is_wpt()) { |
| 53 | if (config->adsp_d3_pg_enable) { |
| 54 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; |
| 55 | if (config->adsp_sram_pg_enable) |
| 56 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
| 57 | else |
| 58 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 59 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 60 | tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 61 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 62 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 63 | if (config->adsp_d3_pg_enable) { |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 64 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 65 | if (config->adsp_sram_pg_enable) |
| 66 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 67 | else |
| 68 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 69 | } else { |
| 70 | tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 71 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 72 | } |
| 73 | pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); |
| 74 | |
| 75 | /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ |
| 76 | RCBA32_OR(0x3350, (1 << 10)); |
| 77 | |
| 78 | /* Set DSP IOBP PMCTL 0x1e0=0x3f */ |
| 79 | pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); |
| 80 | |
| 81 | if (config->sio_acpi_mode) { |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 82 | struct device_nvs *dev_nvs = acpi_get_device_nvs(); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 83 | |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 84 | /* Configure for ACPI mode */ |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 85 | printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); |
| 86 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 87 | /* Save BAR0 and BAR1 to ACPI NVS */ |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 88 | dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base; |
| 89 | dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base; |
| 90 | dev_nvs->enable[SIO_NVS_ADSP] = 1; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 91 | |
| 92 | /* Set PCI Config Disable Bit */ |
| 93 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); |
| 94 | |
| 95 | /* Set interrupt de-assert/assert opcode override to IRQ3 */ |
| 96 | pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); |
| 97 | |
| 98 | /* Enable IRQ3 in RCBA */ |
| 99 | RCBA32_OR(ACPIIRQEN, ADSP_ACPI_IRQEN); |
| 100 | |
| 101 | /* Set ACPI Interrupt Enable Bit */ |
| 102 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, |
| 103 | ADSP_PCICFGCTL_ACPIIE); |
| 104 | |
| 105 | /* Put ADSP in D3hot */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 106 | tmp32 = read32(res2mmio(bar1, PCH_PCS, 0)); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 107 | tmp32 |= PCH_PCS_PS_D3HOT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 108 | write32(res2mmio(bar1, PCH_PCS, 0), tmp32); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 109 | } else { |
| 110 | printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); |
| 111 | |
| 112 | /* Configure for PCI mode */ |
Elyes HAOUAS | fac2893 | 2020-05-03 08:30:09 +0200 | [diff] [blame] | 113 | pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 114 | |
| 115 | /* Clear ACPI Interrupt Enable Bit */ |
| 116 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, |
| 117 | ~(ADSP_PCICFGCTL_SPCBAD | ADSP_PCICFGCTL_ACPIIE), 0); |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | static struct device_operations adsp_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 122 | .read_resources = pci_dev_read_resources, |
| 123 | .set_resources = pci_dev_set_resources, |
| 124 | .enable_resources = pci_dev_enable_resources, |
| 125 | .init = adsp_init, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 126 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | static const unsigned short pci_device_ids[] = { |
| 130 | 0x9c36, /* LynxPoint */ |
| 131 | 0x9cb6, /* WildcatPoint */ |
| 132 | 0 |
| 133 | }; |
| 134 | |
| 135 | static const struct pci_driver pch_adsp __pci_driver = { |
| 136 | .ops = &adsp_ops, |
| 137 | .vendor = PCI_VENDOR_ID_INTEL, |
| 138 | .devices = pci_device_ids, |
| 139 | }; |