ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c
index 06dd38b..a65ff4b 100644
--- a/src/soc/intel/broadwell/pch/adsp.c
+++ b/src/soc/intel/broadwell/pch/adsp.c
@@ -10,7 +10,7 @@
#include <soc/adsp.h>
#include <soc/device_nvs.h>
#include <soc/iobp.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pch.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
@@ -79,20 +79,15 @@
pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
if (config->sio_acpi_mode) {
- /* Configure for ACPI mode */
- struct global_nvs *gnvs;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
+ /* Configure for ACPI mode */
printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
-
/* Save BAR0 and BAR1 to ACPI NVS */
- gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base;
- gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base;
- gnvs->dev.enable[SIO_NVS_ADSP] = 1;
+ dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
+ dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
+ dev_nvs->enable[SIO_NVS_ADSP] = 1;
/* Set PCI Config Disable Bit */
pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);