commit d9f95070650675599e0c1dee67f0b0074eced678
author Duncan Laurie <dlaurie@chromium.org> Wed Oct 01 13:47:20 2014 -0700
committer Patrick Georgi <pgeorgi@google.com> Thu Apr 02 17:28:15 2015 +0200
tree 611c5bf95691496a8556ff33d2923367e5b15079
parent 767d245ebf2d6d797bf759d23778553ed6f2a0b2

broadwell: Disable ADSP power gating feature by default

Disable ADSP D3 and SRAM power gating features by default, and make
the devicetree.cb flags into enable flags instead of disable.

BUG=chrome-os-partner:31588
BRANCH=samus,auron
TEST=build and boot on samus

Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89
Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9218
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/broadwell/adsp.c

diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 9ecbe95..bf77763 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,21 +69,25 @@
 
 	/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
 	tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
-	if (config->adsp_d3_pg_disable) {
-		if (pch_is_wpt()) {
-			tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
-			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+	if (pch_is_wpt()) {
+		if (config->adsp_d3_pg_enable) {
+			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+			if (config->adsp_sram_pg_enable)
+				tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+			else
+				tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
 		} else {
-			tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
-			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
 		}
 	} else {
-		if (pch_is_wpt()) {
-			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
-			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
-		} else {
+		if (config->adsp_d3_pg_enable) {
 			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
-			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			if (config->adsp_sram_pg_enable)
+				tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+			else
+				tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+		} else {
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
 		}
 	}
 	pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);